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PLLs and
DLLs
Outline
Clock System Architecture
Phase-Locked Loops
Delay-Locked Loops
Phase-Locked
Loop (PLL)
Delay-Locked
Loop (PLL)
Linear Model
Δf out
Δf fb =
N
ΔΦ out
ΔΦ fb =
N
I pd ( s ) I cp
= = K pd
Φ err ( s ) 2π
Vctrl ( s ) 1
= +R (negligible)
I pd ( s ) sC
Linear Model
ΔTout ( s )
= K vcdl
ΔVctrl ( s )
I pd ( s ) I cp
=
Terr ( s ) Tc
ΔVctrl ( s ) K I 1
= =
I pd ( s ) s sC