Pegatron T14NH REV 2.0 (Incompleto) PDF

5 4 3 2 1
T14NH Block Diagram

D
Penryn D
FAN + SENSOR CPU VCORE

PAG E 50 PAG E 3, 4,5 PAG E 80 SYSTEM PWR
PAG E 81
FSB 1066MHz BAT & CHARGER

PAG E 88
CRT
PAG E 46 Other PWR
PAG E 82, 83, 84, 85, 90, 91, 92, 93, 94
DDR2 800MHz
LVDS Dual Channel DDR2
PAG E 45
SO-DIMM x2 PAG E 7, 8,9
C HDMI C
PAG E 47
MCP79MH
TPM
PAG E 62
BGA1437
INTERNAL 10/100 LAN
KEYBOARD LPC Realtek RTL8102EL
PAG E 31
EC PAG E 33
ITE/IT8512 RJ-45 CON

BIOS SPI ROM PAG E 30 ,31
PCI-E x1 PAG E 34
PAG E 30
NewCard/DebugCard
Azalia PAG E 43,44
PAG E 10,11 ,12,13,14, 15 ,16,17 ,18,19 ,20

B B
USB MINICARD
MIC IN WLAN
PAG E 38
Azalia Codec PAG E 53
Realtek/ALC663 USB 2.0 CON x2

PAG E 46
PAG E 36, 37, 38, 39
AUDIO AMP
PAG E 37
CMOS Camera
PAG E 46
MDC A
PAGE 35 T B
A S
S U CARD READER
Realtek/RTS5158E PAG E 42
USB 2.0 CON x2

SATA ODD PAG E 52
PAG E 51
A A
Blue Tooth
PAG E 61
SATA HDD Title : BLOCK DIAGRAM

PAG E 51
Engineer: Iverson_Qiu
Size Proj e ct N am e Re v
Cus to m
T14NH 2.0
Date: Mon da y, Ju ne 22 , 2 00 9 She et 1 of 94

5 4 3 2 1
A B C D E
T14NH Schematic Index

Page System page Ref. MCP79MH GPIO Use As Signal Name Power MCP79MH GPIO Use As Signal Name Power
1
01 Block Diagram GPIO 01 / / / GPIO 34 GPO BT_ON +3VSUS 1
02 Schematic Information GPIO 02 / / / GPIO 35 / / /

03-05 CPU-Penryn GPIO 03 / / / GPIO 36 / / /
07-09 DDR II SO-DIMM GPIO 04 / / / GPIO 37 / / /
10-20 MCP79MH GPIO 05 / / / GPIO 38 / / /
28 HDCP GPIO 06 / / / GPIO 39 / / /
30-31 EC_IT8512 GPIO 07 / / / GPIO 40 / / /
32 SW GPIO 08 / / / GPIO 41 / / /
33 Realtek RTL8102EL GPIO 09 / / / GPIO 42 / / /
34 RJ45 + RJ11 GPIO 10 / / / GPIO 43 / / /
35 MDC GPIO 11 / / / GPIO 44 / / /
36 ALC663 Codec GPIO 12 / / / GPIO 45 / / /
2
37 AUDIO_G1431F2U GPIO 13 / / / GPIO 46 / / / 2
38 AUDIO_HP_MIC GPIO 14 / / / GPIO 47 / / /

42 CardReader GPIO 15 / / / GPIO 48 / / /
43 NewCard PWR SW & CON GPIO 16 / / / GPIO 49 / / /
44 Debug GPIO 17 / / / GPIO 50 / / /
45 LVDS & INVERTER CONNECTOR GPIO 18 / / / GPIO 51 / / /
46 I/O Board Connector GPIO 19 / / / GPIO 52 / / /
47 HDMI GPIO 20 / / / GPIO 53 / / /
50 THER SENSOR & FAN GPIO 21 / / / GPIO 54 / / /
51 HDD & CDROM GPIO 22 / / / GPIO 56
52 USB Port x 2 GPIO 23 / / / GPIO 57 / / /
53 MINICARD GPIO 24 / / / GPIO 58 / / /
3 3
56 LED GPIO 25 / / / GPIO 59 / / /

57 DISCHARGE GPIO 26 / / / GPIO 60 GPO WLAN_ON +3VS
60 DC & BAT IN GPIO 27 / / / GPIO 61 / / /
61 Blue Tooth GPIO 28 / / / GPIO 62 GPO WLAN_LED +3VS
62 TPM GPIO 30 / / / GPIO 63 / / /
65 MDC NUT & Hinksink NUT GPIO 31 GPIO 64 / / /
68 Power On Sequence GPIO 32 / / /
80 POWER_VCORE
81 POWER_SYSTEM
82 POWER_I/O_+VCCP & +1.5VS
83 POWER_I/O_DDR & VTT
4
84 POWER_I/O_ +2.5VS(Empty) 4
85 POWER_+VCORE_MCP & +1.1VSUS

86 POWER_+VCCFGX (Empty)
87 POWER_+12VSUS
88 POWER_CHARGER
89 POWER_WLED_DRIVER(Empty)
90 POWER_DETECT
91 POWER_LOAD SWITCH
92 POWER_PROTECT
93 POWER_SIGNAL
94 POWER_FLOWCHART
5 5
Title : Schematic Information

Cus to m
T14NH 2.0

A B C D E
5 4 3 2 1
H_D#[63:0 ]
10 H_D#[63:0 ]
H_A#[35:3 ]
10 H_A#[35:3 ]
H_REQ #[4:0 ]
10 H_RE Q #[4:0 ]
T031 8
T0319
D D
1
U030 1A U030 1B
1
H_A#3 J4 A H1 H_A DS # 10
H_D#0 E22 Y22 H_D #32
H_A#4
A[3]# D ADS# H_D#1
D[0]# D[32]# H_D #33
L5 E2 H_BN R# 10 F24 AB24
H_A#5
A[4]# D BNR#
H_D#2
D[1]# D[33]#
H_D #34
L4 R G5 H_BP R I# 10 E26 V24
A[5]# BPRI# D[2]# D[34]#
H_A#6 K5 G H_D#3 G22 D V26 H_D #35
A[6]# D[3]# A D[35]#
H_A#7 M3 H5 H_D#4 F23 V23 H_D #36
A[7]# R DEFER# H_D EF ER# 10 D[4]# T D[36]#
H_A#8 H_D#5 H_D #37
N2 O F21 G25 A T22
A[8]# DRDY# H_D R DY# 10 D[5]# D[37]#
H_A#9
J1 U E1 H_D#6
E25 G U25 H_D #38
A[9]# P DBSY# H_D B SY# 10 D[6]# D[38]#
H_A#1 0 H_D#7 H_D #39
N3 A[10]# 0 E23 D[7]# R D[39]# U23
+VC C P
H_A#1 1
P5 F1 H_BR 0# H_D#8
K24 P Y25 H_D #40
A[11]# BR0# H_BR 0# 10 D[8]# D[40]#
H_A#1 2 H_D#9 0 H_D #41
P2 G24 W22
H_A#1 3 A[12]# L H_IER R# R03 09 1% 56O hm H_D#10 D[9]# P
2 D[41]# H_D #42
L2 O IERR# D20 1 2 J24 R Y23
A[13]# D[10]# D[42]#
H_A#1 4 H_D#11 H_D #43
P4
A[14]#
R INIT# B3 H_INI T# 10 J23
D[11]# D[43]#
W24
H_A#1 5 P1 T H_D#12 H22 A W25 H_D #44
A[15]# N D[12]# G D[44]#
H_A#1 6 R1 H4 H_D#13 F26 T AA23 H_D #45
A[16]# OLOCK# H_L OC K# 10 D[13]# A D[45]#
M1 H_D#14 K22 AA24 H_D #46
10 H_A DS TB#0 ADSTB[0]# C D[14]# D D[46]#
C1 H_CP UR ST# H_D#15 H23 AB25 H_D #47
RESET# H_CP UR ST# 10 D[15]# D[47]#
H_REQ #0 K3 F3 J26 Y26
REQ[0]# RS[0]# H_RS #0 10 10 H_D ST BN# 0 DSTBN[0]# DSTBN[2]# H_D ST BN# 2 10
H_REQ #1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS #1 10 10 H_D ST BP #0 DSTBP[0]# DSTBP[2]# H_D ST BP #2 10
H_REQ #2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS #2 10 10 H_D INV #0 DINV[0]# DINV[2]# H_D INV #2 10
H_REQ #3 J3 G2
REQ[3]# TRDY# H_T RD Y# 10
H_REQ #4
L1 REQ[4]#
H_D#16 H_D #48
G6 N22 AE24
HIT# H_H IT# 10 D[16]# D[48]#
H_A#1 7 H_D#17 H_D #49
Y2 E4 H_H ITM # 10 K25 AD24
H_A#1 8 A[17]# HITM# H_D#18 D[17]# D[49]# H_D #50
U5 P26 AA21
H_A#1 9 A[18]# T032 5 H_D#19 D[18]# D[50]# H_D #51
R3 A AD4 1 R23 AB22
A[19]# D BPM[0]# D[19]# D[51]#
H_A#2 0 W6 AD3 XDP_B P M #1 H_D#20 L23 D AB21 H_D #52
C H_A#2 1
A[20]# D BPM[1]#
T032 6 H_D#21
D[20]# A D[52]#
H_D #53 C
U4 R AD1 1 M24 AC26
A[21]# S BPM[2]# D[21]# T D[53]#
H_A#2 2 G T032 7 H_D#22 H_D #54
Y5 L AC4 1 L22 A AD20
A[22]#
H_A#2 3 U1 A BPM[3]# AC2 1 T032 8 H_D#23 M23
D[22]#
G
D[54]#
AE22 H_D #55
A[23]# R N PRDY# D[23]# D[55]#
XDP_B P M #5 H_D#24 H_D #56
H_A#2 4 R4
A[24]#
O PREQ#
AC1 P25
D[24]# R D[56]#
AF23
H_A#2 5 T5 U I AC5 XDP_T CK H_D#25 P23 P AC25 H_D #57
A[25]# P G TCK D[25]# 1 D[57]#
H_A#2 6 T3 AA6 XDP_T DI H_D#26 P22 AE21 H_D #58
H_A#2 7
A[26]# 1 P
S TDI
XDP_T DO +VC C P H_D#27
D[26]# D[58]#
H_D #59
W2 AB3 T24 P AD21
A[27]# TDO D[27]# 3 D[59]#
H_A#2 8 W5 / AB5 XDP_T MS H_D#28 R24 R AC22 H_D #60
A[28]# TMS D[28]# D[60]#
H_A#2 9
Y4 IP AB6
XDP_T RS T# H_D#29
L25 AD23
H_D #61
H_A#3 0
A[29]# D
T TRST#
XDP_D BR #
2
H_D#30
D[29]# D[61]#
H_D #62
U2 A[30]# X DBR# C20 T25 D[30]#
A
G D[62]# AF22
H_A#3 1
V4 R03 15 H_D#31
N25
T AC23 H_D #63
H_A#3 2 A[31]# 1K Ohm D[31]# A D[63]# Comp 0,2: Zo=27.4 Ohm, trace length < 0.5"
W3 10 H_DST BN# 1 L26 D AE25 H_D ST BN# 3 10
H_A#3 3 A[32]# 1% DSTBN[1]# DSTBN[3]# Comp 1,3: Z0=55 Ohm, trace length < 0.5"
AA4 THERMAL 10 H_DST BP #1 M26 AF24 H_D ST BP #3 10
H_A#3 4
A[33]# DSTBP[1]# DSTBP[3]#
AB2 1 10 H_DINV #1 N24 AC20 H_D INV #3 10
H_A#3 5
A[34]# H_PR OC HOT_S #
DINV[1]# DINV[3]#
AA3 D21
A[35]# PROCHOT# GTL_R EF H_CO MP 0 R03 11 27.4Ohm 1%
10 H_A DS TB#1 V1 A24 CP U_THR M _D A 50 AD26 R26 1 2
ADSTB[1]# THRMDA GTLREF COMP[0]
T0320 1 B25 CP U_THR M _D C 50 2
R03 17 2 @ 1% 1 1K Ohm CP U_TES T1 C23 MISC U26 H_CO MP 1 R03 12 1 2 54.9Ohm 1%
IC THRMDC R03 18 @ 1% 1K Ohm CP U_TES T2
TEST1 COMP[1] H_CO MP 2 R03 13 27.4Ohm 1%
A6 2 1 D25 AA1 1 2
10 H_A20M # A20M# 1 TEST2 COMP[2]
H_FER R # A5 C7 R03 16 T03 04 1 CP U_TES T3 C24 Y1 H_CO MP 3 R03 14 1 2 54.9Ohm 1%
10 H_FER R # FERR# H THERMTRIP# H_T HR M TRI P# 5,10,31 TEST3 COMP[3]
C4 C03 01 2K Ohm T03 05 1 CP U_TES T4 AF26 1
10 H_IGNN E# IGNNE# TEST4
T0321 1 0.1UF /1 0V 1% T03 06 1 CP U_TES T5 AF1 E5 H_DPR S TP# T032 2
2 TEST5 DPRSTP# H_D PR S TP# 10,80
D5 1 T032 4 @ T03 07 1 CP U_TES T6 A26 B5
10 H_STP C LK# STPCLK# 1 TEST6 DPSLP# H_D PS LP # 10
H_INTR
C6 H CLK D24
10 H_INTR
H_NM I
LINT0 DPWR# H_PW RGD
H_D PW R# 10
10 H_NM I B4 LINT1 BCLK[0] A22 CLK _C P U_B CLK 10 20 CP U_B SEL 0 B22 BSEL[0] PWRGOOD D6 H_PW RGD 10
H_CP US LP#
10 H_SM I# A3 A21 CLK _C P U_B CLK # 10 20 CP U_B SEL 1 B23 D7 H_CP US LP# 10
SMI# BCLK[1] BSEL[1] SLP#
20 CP U_B SEL 2 C21 AE6 PM _PS I# 80
T032 3 BSEL[2] PSI#
M4 1
RSVD1
N5 SOC KET478B
RSVD2 Zo=55 Ohm, 0.5" max
T2
B RSVD3 for GTL_REF B
V3
RSVD4
BCLK FSB BSEL2 BSEL1 BSEL0
B2 D
TE ST 7 T0314 CP U_R SVD 7
RSVD5 E
1 C3
RSVD6 V 166 667 L H H
D2
RSVD7
R
+VC C P
D22 E 200 800 L H L
RSVD8 S @ R03 19 150 Ohm 1%
D3 E 2 1
T0317 CP U_R SVD 10
RSVD9
1 F6
RSVD10
R
266 1067 L L L
+VC C P
SOC KET478 B
@ R03 41 62O hm H_BR 0# +VC C P
2 1
2 R03 42 1 62O hm H_FER R #
@ R03 43 150 Ohm 1% +3V S

2 1 H_INTR
2
@ 2 R03 44 1 150 Ohm 1% H_N M I
@ 2 R03 45 1 200 Ohm H_CP UR ST# R03 10
@ 2 R03 46 1 51O hm H_CP US LP#
Default Strapping When Not Used @ 2 R03 47 1 220 Ohm 1% H_DPR S TP#
68 Ohm 2
+VC C P 1 R03 38 2 0Ohm H_PR OC HOT_S #

10 H_PR OC HOT# 1 3
3 R03 21
D
@ 10K Ohm
3
XDP_B P M #1 R03 01 @ 54.9Ohm 1% 3
1 2 30 ,90 PW R LIM IT# 2 1 D 1
2N 700 2
XDP_B P M #5 R03 02 54.9Ohm 1% D0301 RB 75 1V -40 Q03 01 1
1 2 1
XDP_T DI R03 03 54.9Ohm 1% Q03 02 G
1 2 H2N 700 2
S 3
XDP_T DO R03 04 @ 54.9Ohm 1% 1 2 3
1 2 1 THRO _CP U 30 2 D
XDP_T MS R03 05 54.9Ohm 1% G
1 2 S
2
2 2N 7002
XDP_D BR # R03 48 @ 1KOhm 1% 1
1 2 +3V S 1 PM _THER M #_E C 30
Q030 3 G
A S A
XDP_T CK R03 07 54.9Ohm 1% 2
1 2 2
XDP_T RS T# R03 08 1 2 649O hm 1%
Place R0304 & R0348 for XDP function

Title : CPU-Penryn(1)
Cus to m
T14NH 2.0

5 4 3 2 1
5 4 3 2 1
U030 1D
A4 P6
VSS1 VSS82
A8 P21
VSS2 VSS83
A11 P24
+VC OR E +VC OR E
VSS3 VSS84
A14 R2
VSS4 VSS85
A16 R5
U0301 C VSS5 VSS86
A19 R22
VSS6 VSS87
A7 AB20 A23 R25
VCC1 VCC68 VSS7 VSS88
D A9 AB7 AF2 T1 D
A10 AC7 B6 T4
A12 AC9 B8 T23
A13 AC12 B11 T26
A15 AC13 B13 U3
A17 AC15 B16 U6
A18 AC17 B19 U21
A20 AC18 B21 U24
B7 AD7 B24 V2
B9 VCC11 VCC78 AD9 C5 VSS17 VSS98 V5
B10 AD10 C8 V22
B12 AD12 C11 V25
B14 AD14 C14 W1
B15 AD15 C16 W4
B17 AD17 C19 W23
B18 AD18 C2 W26
B20 AE9 C22 Y3
C9 AE10 C25 Y6
C10 AE12 D1 Y21
C12 AE13 D4 Y24
C13 AE15 D8 AA2
C15 AE17 D11 AA5
C17 AE18 D13 AA8
C18 AE20 D16 AA11
D9 VCC26 VCC93 AF9 D19 VSS32 VSS113 AA14
D10 AF10 D23 AA16
D12 AF12 D26 AA19
D14 AF14 E3 AA22
D15 AF15 E6 AA25
C VCC30 VCC97 VSS36 VSS117 C
D17 AF17 E8 AB1
D18 AF18 E11 AB4
E7 AF20 E14 AB8
E9 E16 AB11
VCC34 2.5 A VSS40 VSS121
E10 G21 +VC C P E19 AB13
VCC35 VCCP1 VSS41 VSS122
E12 V6 E21 AB16
E13 J6 E24 AB19
E15 K6 F5 AB23
E17 VCC39 VCCP5 M6 F8 VSS45 VSS126 AB26
E18 J21 F11 AC3
E20 K21 F13 AC6
VCC41 VCCP7 +1. 5V S VSS47 VSS128
F7 M21 F16 AC8
F9 N21 L04 01 F19 AC11
VCC43 VCCP9 +VCCA_CPU VSS49 VSS130
F10 N6 12 0Ohm /100 M hz F2 AC14
VCC44 VCCP10 130 mA VSS50 VSS131
F12 R21 +VC C A_C PU 1 2 F22 AC16
F14 R6 1 1 F25 AC19
F15 T21 l060 3 G4 AC21
F17 T6 C04 02 C04 01 Ira t= 40 0m A G1 AC24
F18 V21 2 0.01U F /1 6V 2 10U F/6 .3V G23 AD2
F20 W21 MLC C /+/ -10% MLC C /+/ -10% G26 AD5
AA7 H3 AD8
VCC51 VSS57 VSS138
AA9 B26 H6 AD11
VCC52 VCCA1 VSS58 VSS139
AA10 C26 H21 AD13
VCC53 VCCA2 VSS59 VSS140
AA12 H24 AD16
VCC54 VSS60 VSS141
H_V ID0 RNX 040 1A
AA13 AD6 1 0O hm 2 VR_V ID0 80 J2 AD19
VCC55 VID[0] H_V ID1 RNX 040 1B VSS61 VSS142
AA15 AF5 3 0O hm 4 VR_V ID1 80 J5 AD22
VCC56 VID[1] H_V ID2 RNX 040 1C VSS62 VSS143
AA17 AE5 5 0O hm 6 VR_V ID2 80 J22 AD25
VCC57 VID[2] H_V ID3 RNX 040 2A
VSS63 VSS144
AA18 AF4 1 0O hm 2 VR_V ID3 80 J25 AE1
VCC58 VID[3] H_V ID4 RNX 040 2B
VSS64 VSS145
AA20 AE3 3 0O hm 4 VR_V ID4 80 K1 AE4
B VCC59 VID[4] H_V ID5 RNX 040 2C
VSS65 VSS146 B
AB9 AF3 5 0O hm 6 VR_V ID5 80 K4 AE8
VCC60 VID[5] H_V ID6 RNX 040 2D
VSS66 VSS147
AC10 AE2 7 0O hm 8 VR_V ID6 80 K23 AE11
VCC61 VID[6] RNX 040 1D
VSS67 VSS148
AB10 7 0O hm 8 K26 AE14
VCC62 VSS68 VSS149
AB12 L3 AE16
VCC63 VSS69 VSS150
AB14 AF7 1 2 L6 AE19
VCC64 VCCSENSE R04 01 100O hm 1%
+VC OR E VSS70 VSS151
AB15 L21 AE23
VCC65 VSS71 VSS152
AB17 L24 AE26
VCC66 VCC S ENSE 80 VSS72 VSS153
AB18 AE7 M2 A2
VCC67 VSSSENSE VSS SEN SE 80 VSS73 VSS154
M5 AF6
SOC KET478B
1 VSS74 VSS155
M22 AF8
VSS75 VSS156
M25 AF11
VSS76 VSS157
R04 02 N1 AF13
VSS77 VSS158
100 Ohm N4 AF16
VSS78 VSS159
1% N23 AF19
2 VSS79 VSS160
N26 AF21
VSS80 VSS161
P3 A25
VSS81 VSS162
AF25
VSS163
SOC KET478B
A A
Title : CPU-Penryn(2)
Cus to m
T14NH 2.0

5 4 3 2 1
5 4 3 2 1
+VC OR E +VCCP Decoupling Capacitor

38A for Penryn
(Place near CPU)
+VC C P
1 1 1 1 1 1 1 1 1 1
C05 08 C05 31 C05 18 C05 15 C05 23 C05 02 C05 30 C05 21 C05 19 C05 27
1
D 10 UF/6 .3V 10U F/6 .3V 10 UF/6 .3V 10 UF/6 .3V 10UF/6 .3V 10U F/6 .3V 10 UF/6 .3V 10 UF/6 .3V 10UF/6 .3V 10U F/6 .3V + D
2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1
MLC C /+/ -10% CE0 50 1
C05 14 C05 38 C05 35 C05 34 C05 37 C05 36
2 2 0.1UF /1 0V 2 0.1UF /1 0V 2 0.1UF /1 0V 2 0.1UF /1 0V 2 0.1UF /1 0V 2 0.1UF /1 0V

100 UF/2 .5V
MLC C /+/ -10%
1 1 1 1 1 1 1 1 1 1
C05 25 C05 17 C05 24 C05 28 C05 22 C05 11 C05 20 C05 03 C05 10 C05 09
10 UF/6 .3V 10U F/6 .3V 10 UF/6 .3V 10 UF/6 .3V 10UF/6 .3V 10U F/6 .3V 10 UF/6 .3V 10 UF/6 .3V 10UF/6 .3V 10U F/6 .3V
2 2 2 2 2 2 2 2 2 2 Decoupling guide from Intel
VCORE 22uF/10V r 10uF * 36pcs

330uF/2V * 4pcs
1 1 1 1 1 1 1 1 1 1 VCCP 0.1uF * 6pcs
C05 12 C05 39 C05 16 C05 04 C05 07 C05 01 C05 06 C05 13 C05 26 C05 29 270uF * 1pcs
10 UF/6 .3V 10U F/6 .3V 10 UF/6 .3V 10 UF/6 .3V 10UF/6 .3V 10U F/6 .3V 10 UF/6 .3V 10 UF/6 .3V 10UF/6 .3V 10U F/6 .3V
2 2 2 2 2 2 2 2 2 2
+VCORE Mid-Frequency Capacitor

1 1 1 1 1 1 Intel: 22UF *32
C05 05 C05 32 C05 45 C05 46 C05 47 C05 48 F3S: 10U F *16
10U F/6 .3V 10U F/6 .3V 10 UF/6 .3V 10 UF/6 .3V 10UF/6 .3V 10U F/6 .3V
2 2 2 2 2 2 A7S: 10U F *10 ....11/17
C V1V: ? C
+VCCP Decoupling Capacitor

Intel: 270UF *1, 0.1UF *6
F3S: 100UF *1, 0.1UF *4
V1V: ?
+VC C P +VC C P
B B
R05 05
1
33 0O hm
R05 04
2
49 .9Ohm
1%
2 1 2
C05 42 0.1UF /1 6V
1
Q050 3
B
2N 70 02
S D
22 3 3 FOR C E_OFF #
3,10, 31 H_THR M TRI P# 2 E C 3 FOR C E_OFF # 30,60, 81,92
G
Q0502 1
PM B S39 04
1
15 ,56 PC I_R ST# 0
Thermal Trip signal (From CPU to ICH-9M and sequence)
A A
Title : CPU CAPS

Cus to m
T14NH 2.0

5 4 3 2 1
5 4 3 2 1
5.2H M_A _D Q[63: 0] 11

D
12G02533200D
J07 01 A
9,11 M_A _A[13: 0]
M_A _A0 102 5 M_A _D Q0
A0 DQ0
M_A _A1 101 7 M_A _D Q3
M_A _A2
A1 DQ1 M_A _D Q6
100 A2 DQ2 17
M_A _A3 M_A _D Q7
99 19
M_A _A4
A3 DQ3
98 4 M_A _D Q1
M_A _A5 A4 DQ4
97 6 M_A _D Q5
M_A _A6 A5 DQ5
94 14 M_A _D Q4
A6 DQ6
M_A _A7 92 16 M_A _D Q2
A7 DQ7
M_A _A8 93 23 M_A _D Q16
A8 DQ8
M_A _A9 91 25 M_A _D Q18
A9 DQ9 +1. 8V
M_A _A10 105 35 M_A _D Q17
A10/AP DQ10
M_A _A11 90 37 M_A _D Q22
A11 DQ11 J07 01 B
M_A _A12 89 20 M_A _D Q20
A12 DQ12
M_A _A13 116 22 M_A _D Q21 112 18
A13 DQ13 VDD1 VSS16
86 36 M_A _D Q19 111 24
9,11 M_A _A14 A14 DQ14 VDD2 VSS17
M_C LK_D DR0 84 38 M_A _D Q23 117 41
A15 DQ15 1 2 2 2 2 VDD3 VSS18
M_A _D Q13 C07 03 C07 08 C07 09 C07 10 C07 11
85 43 96 53
1 9,11 M_A _BS 2 A16_BA2 DQ16 VDD4 VSS19
C07 01 M_A _D Q12 10UF/1 0V 0.1UF /1 6V 0.1UF /1 6V 0.1UF /1 6V 0.1UF /1 6V
DQ17 45 95 VDD5 VSS20 42
8.2P F/5 0V M_A _D Q15 @
9,11 M_A _BS 0 107 55 2 1 1 1 1 118 54
@ BA0 DQ18 M_A _D Q11 VDD6 VSS21
2 9,11 M_A _BS 1 106 57 81 59
M_C LK_D DR#0 BA1 DQ19 M_A _D Q8 VDD7 VSS22
9,11 M_C S #0 110 44 82 65
S0# DQ20 M_A _D Q9
VDD8 VSS23
9,11 M_C S #1 115 46 87 60
C M_C LK_D DR0
S1# DQ21 M_A _D Q10
VDD9 VSS24 C
11 M_C LK_D DR0 30 56 GND GND GND GND GND 103 66
M_C LK_D DR1 M_C LK_D DR#0
CK0 DQ22 M_A _D Q14
VDD10 VSS25
11 M_C LK_D DR#0 32 58 88 127
M_C LK_D DR1
CK0# DQ23 VDD11 VSS26
164 61 M_A _D Q29 104 139
1 11 M_C LK_D DR1 CK1 DQ24 VDD12 VSS27
C07 02 M_C LK_D DR#1 166 63 M_A _D Q25 128
11 M_C LK_D DR#1 CK1# DQ25 VSS28
8.2P F/5 0V 79 73 M_A _D Q31 199 145
9,11 M_C KE0 CKE0 DQ26 +3V S VDDSPD VSS29
@ 80 75 M_A _D Q30 165
2 9,11 M_C KE1 CKE1 DQ27 1 1 VSS30
M_C LK_D DR#1 113 62 M_A _D Q28 C07 06 C07 07 83 171
9,11 M_A _CAS # CAS# DQ28 NC1 VSS31
108 64 M_A _D Q24 1UF/1 0V 0.1UF /1 6V 120 172
9,11 M_A _RAS # RAS# DQ29 M_A _D Q27 T07 01
NC2 VSS32
9,11 M_A _W E# 109 WE# DQ30 74 2 2 1 50 NC3 VSS33 177
M_A _D Q26
198 76 69 187
SA0 DQ31 M_A _D Q36
NC4 VSS34
200 123 163 178
SA1 DQ32 M_A _D Q37 GND NCTEST VSS35
8,20 SM B _CLK _ME M 197 125 GND 190
SCL DQ33 M_A _D Q39 R07 04 0Ohm M_V REF _DIM M 0 VSS36
8,20 SM B _DAT_M EM 195 135 8,11 M_V REF _M CP 79 1 2 1 9
SDA DQ34 VREF VSS37
GND 137 M_A _D Q38 21
DQ35 1 1 VSS38
114 124 M_A _D Q33 C07 04 C07 05 201 33
9,11 M_O DT0 ODT0 DQ36 GND0 VSS39
119 126 M_A _D Q32 1UF/1 0V 0.1UF /1 0V 202 155
9,11 M_O DT1 ODT1 DQ37 GND1 VSS40
134 M_A _D Q35 MLC C /+/ -10 % MLC C /+/ -10% 34
11 M_A _DM [7:0 ] DQ38 2 2 VSS41
M_A _DM 0 10 136 M_A _D Q34 203 132
DM0 DQ39 NP_NC1 VSS42
M_A _DM 2 26 141 M_A _D Q44 204 144
DM1 DQ40 NP_NC2 VSS43
M_A _DM 1 52 143 M_A _D Q41 GND GND 156
DM2 DQ41 VSS44
M_A _DM 3 67 151 M_A _D Q47 47 168
DM3 DQ42 VSS1 VSS45
M_A _DM 4 130 153 M_A _D Q46 133 2
DM4 DQ43 VSS2 VSS46
M_A _DM 5 M_A _D Q45
147 140 183 3
DM5 DQ44 VSS3 VSS47
170 142 77 15
DM6 DQ45 VSS4 VSS48
185 152 12 27
DM7 DQ46 M_A _D Q42 VSS5 VSS49
11 M_A _D QS [7:0 ] 154 48 39
M_A _DQS 0 DQ47 M_A _D Q52 VSS6 VSS50
13 157 184 149
M_A _DQS 2
DQS0 DQ48 M_A _D Q48
VSS7 VSS51
31 159 78 161
M_A _DQS 1
VSS8 VSS52
51 173 71 28
B
M_A _DQS 3
VSS9 VSS53 B
70 175 72 40
M_A _DQS 4
VSS10 VSS54
131 158 121 138
M_A _DQS 5
DQS4 DQ52 VSS11 VSS55
148 160 M_A _D Q53 122 150
M_A _DQS 6
169 174 M_A _D Q50 196 162
M_A _DQS 7
VSS13 VSS57
188 176 193
11 M_A _D QS #[7:0 ]
M_A _DQS #0
VSS14
11 179 8
DQS#0 DQ56 M_A _D Q57
VSS15
M_A _DQS #2 29 181
M_A _DQS #1 49 189 GND
DQS#2 DQ58 DDR _DIM M _200 P
M_A _DQS #3 M_A _D Q62
68 191
M_A _DQS #4
129 180 GND
M_A _DQS #5 DQS#4 DQ60 M_A _D Q61
146 182
M_A _DQS #6 DQS#5 DQ61 M_A _D Q59
167 192
DQS#6 DQ62
M_A _DQS #7 186 194 M_A _D Q63
DQS#7 DQ63
DDR _DIM M _2 00P
+1. 8V
Layout Note: Place these Caps near SO DIMM 0
1 1 1 1 1 1
C07 15 C07 16 C07 17 C07 18 C07 19 +
2.2UF /6 .3V 2.2UF /6 .3V 2.2UF /6 .3V 2.2UF /6 .3V 2.2UF /6 .3V CE0 701
15 0U F/4 V
2 2 2 2 2
ID Assignment for DIMM Modules 2
@
SO-DIMM0 : SA[1:0] = 00
A A
SO-DIMM1 : SA[1:0] = 01
SO-DIMM2 : SA[1:0] = 10 GND
SO-DIMM3 : SA[1:0] = 11
Title : DDR2 SO-DIMM_0

Cus to m
T14NH 2.0

5 4 3 2 1
5 4 3 2 1
D
9.2H M_B _DQ[ 63 :0 ] 11
D
12G025C2200A
J080 1A
9,11 M_B _A[ 13 :0]
M_B _A0 102 5 M_B _DQ7
A0 DQ0
M_B _A1 M_B _DQ1
101 7
A1 DQ1
M_B _A2 M_B _DQ2
100 A2 DQ2 17
M_B _A3 M_B _DQ6
99 19
M_B _A4 A3 DQ3 M_B _DQ4
98 4
M_B _A5 A4 DQ4 M_B _DQ0
97 6
A5 DQ5
M_B _A6 94 14 M_B _DQ5
A6 DQ6
M_B _A7 92 16 M_B _DQ3
A7 DQ7
M_B _A8 93 23 M_B _DQ1 3
A8 DQ8
M_B _A9 91 25 M_B _DQ1 5
A9 DQ9
M_B _A10 105 35 M_B _DQ1 0
A10/AP DQ10 +1. 8V
M_B _A11 90 37 M_B _DQ1 1
A11 DQ11
M_B _A12 89 20 M_B _DQ1 2
A12 DQ12 J08 01B
M_B _A13 116 22 M_B _DQ9
A13 DQ13
86 36 M_B _DQ8 112 18
9,11 M_B _A14 A14 DQ14 VDD1 VSS16
M_B _DQ1 4
84 A15 DQ15 38 111 VDD2 VSS17 24
M_B _DQ1 7
85 43 117 41
9,11 M_B _B S2 A16_BA2 DQ16 1 2 2 2 2 VDD3 VSS18
M_B _DQ2 1 C08 03 C08 08 C08 09 C08 10 C08 11
45 96 53
DQ17 M_B _DQ2 2 VDD4 VSS19
107 55 10U F/1 0V 0.1UF /1 6V 0.1UF /1 6V 0.1UF /1 6V 0.1UF /1 6V 95 42
9,11 M_B _B S0 BA0 DQ18 VDD5 VSS20
M_B _DQ1 8 @
9,11 M_B _B S1 106 57 2 1 1 1 1 118 54
BA1 DQ19 VDD6 VSS21
110 44 M_B _DQ2 0 81 59
9,11 M_C S #2 S0# DQ20 VDD7 VSS22
C M_C LK_D DR2 M_B _DQ1 6 C
9,11 M_C S #3 115 46 82 65
+3V S S1# DQ21 VDD8 VSS23
M_C LK_D DR2 30 56 M_B _DQ1 9 87 60
C08 01 M_C LK_D DR#2 32 58 M_B _DQ2 3 GND GND GND GND GND 103 66
11 M_C LK_D DR#2 CK0# DQ23 VDD10 VSS25
8.2P F/5 0V M_C LK_D DR3 164 61 M_B _DQ2 5 88 127
@ M_C LK_D DR#3 166 63 M_B _DQ2 4 104 139
2 11 M_C LK_D DR#3 CK1# DQ25 VDD12 VSS27
M_C LK_D DR#2 R08 01 79 73 M_B _DQ2 6 128
9,11 M_C KE2 CKE0 DQ26 VSS28
10K Ohm 80 75 M_B _DQ2 7 199 145
9,11 M_C KE3 CKE1 DQ27 +3V S VDDSPD VSS29
113 62 M_B _DQ2 9 165
9,11 M_B _C AS # CAS# DQ28 1 1 VSS30
M_C LK_D DR3 M_B _DQ2 8 C08 06
2 9,11 M_B _R AS # 108 RAS# DQ29 64 C08 07 83 NC1 VSS31 171
M_B _DQ3 0 1UF/1 0V
1 9,11 M_B _W E# 109 WE# DQ30 74 0.1UF /1 6V 120 NC2 VSS32 172
C08 02 DIM M _1_ SA 1 M_B _DQ3 1 T08 01
198 76 2 2 1 50 177
SA0 DQ31 M_B _DQ3 7 NC3 VSS33
8.2P F/5 0V 200 123 69 187
@ SA1 DQ32 M_B _DQ3 6 NC4 VSS34
2 7,20 SM B _CLK _ME M 197 125 163 178
M_C LK_D DR#3
SCL DQ33 M_B _DQ3 8 GND GND
NCTEST VSS35
7,20 SM B _DAT_M EM 195 135 190
SDA DQ34 M_B _DQ3 5 R08 04 0Ohm M_V REF _DIM M 1
VSS36
137 7,11 M_V REF _M CP 79 1 2 1 9
GND
DQ35 M_B _DQ3 3
VREF VSS37
9,11 M_O DT2 114 124 1 1 21
ODT0 DQ36 M_B _DQ3 2
VSS38
9,11 M_O DT3 119 126 C08 04 C08 05 201 33
ODT1 DQ37 M_B _DQ3 4
GND0 VSS39
11 M_B _D M [7:0 ] 134 1UF/1 0V 0.1UF /1 0V 202 155
M_B _DM 0
DQ38 M_B _DQ3 9 MLC C /+/ -10 % MLC C /+/ -10%
GND1 VSS40
10 136 2 2 34
M_B _DM 1
DM0 DQ39 M_B _DQ4 0
VSS41
26 141 203 132
M_B _DM 2
DM1 DQ40 M_B _DQ4 7
NP_NC1 VSS42
52 143 204 144
M_B _DM 3
DM2 DQ41 M_B _DQ4 1
NP_NC2 VSS43
67 151 GND GND 156
M_B _DM 4
DM3 DQ42 M_B _DQ4 6
VSS44
130 153 47 168
M_B _DM 5
DM4 DQ43 M_B _DQ4 5
VSS1 VSS45
147 DM5 DQ44 140 133 VSS2 VSS46 2
M_B _DM 6 M_B _DQ4 4
170 142 183 3
M_B _DM 7 DM6 DQ45 M_B _DQ4 3 VSS3 VSS47
185 152 77 15
DM7 DQ46 M_B _DQ4 2 VSS4 VSS48
11 M_B _D QS [7:0 ] 154 12 27
DQ47 VSS5 VSS49
M_B _DQS 0 13 157 M_B _DQ5 3 48 39
M_B _DQS 1 31 159 M_B _DQ5 2 184 149
B
M_B _DQS 2
DQS1 DQ49 M_B _DQ5 5
VSS7 VSS51 B
51 173 78 161
M_B _DQS 3
VSS8 VSS52
70 175 71 28
M_B _DQS 4
VSS9 VSS53
131 158 72 40
M_B _DQS 5 148 160 M_B _DQ4 8 121 138
VSS11 VSS55
M_B _DQS 6 169 174 122 150
M_B _DQS 7
VSS12 VSS56
188 176 196 162
11 M_B _DQS #[7:0 ]
M_B _DQS #0
11 179 M_B _DQ6 1 193
M_B _DQS #1
DQS#0 DQ56 VSS14
29 181 M_B _DQ6 0 8
DQS#1 DQ57 VSS15
M_B _DQS #2 M_B _DQ6 3
49 189 GND
DQS#2 DQ58
M_B _DQS #3 M_B _DQ6 2
68 191 DDR 2_ DIM M _2 00 P
M_B _DQS #4 DQS#3 DQ59
129 180 M_B _DQ5 6 GND
M_B _DQS #5 DQS#4 DQ60
146 182 M_B _DQ5 7
DQS#5 DQ61
M_B _DQS #6 167 192 M_B _DQ5 8
DQS#6 DQ62
M_B _DQS #7 186 194 M_B _DQ5 9
DQS#7 DQ63 +1. 8V
DDR 2_DIM M _200 P Layout Note: Place these CAPs near the SO DIMM1
1
+
1 1 1 1 1
C08 18 C08 19 C08 20 C08 21 C08 22 CE0 80 1
2.2UF /6 .3V 2.2UF /6 .3V 2.2UF /6 .3V 2.2UF /6 .3V 2.2UF /6 .3V 15 0UF/4 V
@
2 2 2 2 2 2
ID Assignment for DIMM Modules
SO-DIMM0 : SA[1:0] = 00
SO-DIMM1 : SA[1:0] = 01 GND
A
SO-DIMM2 : SA[1:0] = 10 A
SO-DIMM3 : SA[1:0] = 11
Title : DDR2 SO-DIMM_1

Cus to m
T14NH 2.0

5 4 3 2 1
5 4 3 2 1
7,11 M_A _A[13:0 ]
8,11 M_B _A[ 13 :0]
+0. 9VS
D M_A _A 2 1 47Ohm 16 RN0 90 1A D
M_A _A 0 2 47Ohm 15 RN0 90 1B
3 47Ohm 14 RN0 90 1C @ C09 15 1 2 0.1UF /1 6V

7,11 M_A _BS 1
M_A _A 6 4 47Ohm 13 RN0 90 1D @ C09 16 1 2 0.1UF /1 6V
M_A _A 4 5 47Ohm 12 RN0 90 1E @ C09 17 1 2 0.1UF /1 6V
M_A _A 11 6 47Ohm 11 RN0 90 1F @ C09 18 1 2 0.1UF /1 6V
M_A _A 7 7 47Ohm 10 RN0 90 1G
M_A _A 14 8 47Ohm 9 RN0 90 1H

7,11 M_A _A14
GND
47Ohm R09 05
7,11 M_C KE1 2 1
M_A _A 5 47Ohm RN0 90 2A
1 16
M_A _A 8 47Ohm RN0 90 2B
2 15
M_A _A 9 3 47Ohm 14 RN0 90 2C @ C09 19 1 2 0.1UF /1 6V
M_A _A 12 4 47Ohm 13 RN0 90 2D @ C09 20 1 2 0.1UF /1 6V
5 47Ohm 12 RN0 90 2E @ C09 21 1 2 0.1UF /1 6V

7,11 M_A _BS 2
6 47Ohm 11 RN0 90 2F @ C09 22 1 2 0.1UF /1 6V
7 47Ohm 10 RN0 90 2G
8 47Ohm 9 RN0 90 2H
7,11 M_C KE0
GND
47Ohm RN0 90 3A
7,11 M_O DT1 1 16
47Ohm RN0 90 3B
7,11 M_C S #1 2 15
47Ohm RN0 90 3C C09 14 0.1UF /1 6V
7,11 M_A _CAS # 3 14 1 2
47Ohm RN0 90 3D C09 13 0.1UF /1 6V
7,11 M_A _W E# 4 13 1 2
5 47Ohm 12 RN0 90 3E C09 12 1 2 0.1UF /1 6V
7,11 M_A _BS 0
C 47Ohm RN0 90 3F C09 11 0.1UF /1 6V C
M_A _A 10 6 11 1 2
M_A _A 1 7 47Ohm 10 RN0 90 3G
M_A _A 3 8 47Ohm 9 RN0 90 3H
GND
2 47Ohm 1 R09 01 C09 01 1 2 0.1UF /1 6V

7,11 M_A _RA S #
M_A _A 13 47Ohm R09 02
2 1
47Ohm R09 07
7,11 M_C S #0 2 1
47Ohm R09 08
7,11 M_O DT0 2 1 GND
+0. 9V S
C09 27
2 10 UF/1 0V
M_B _A14 2 47Ohm 1 R09 06 MLC C /+8 0 -20 %

8,11 M_B _A 14
M_B _A13 47Ohm RN0 90 4A
1 16
M_B _A1 47Ohm RN0 90 4B
2 15
M_B _A10 47Ohm RN0 90 4C C09 10 0.1UF /1 6V
3 14 1 2 GND
47Ohm RN0 90 4D C09 09 0.1UF /1 6V
8,11 M_B _B S0 4 13 1 2
47Ohm RN0 90 4E C09 08 0.1UF /1 6V
8,11 M_B _W E# 5 12 1 2
6 47Ohm 11 RN0 90 4F C09 07 1 2 0.1UF /1 6V
8,11 M_C S #3
7 47Ohm 10 RN0 90 4G
B
8,11 M_B _C AS # B
8 47Ohm 9 RN0 90 4H
8,11 M_O DT3
GND
M_B _A6 1 47Ohm 16 RN0 90 5A

M_B _A4 2 47Ohm 15 RN0 90 5B
M_B _A2 47Ohm RN0 90 5C C09 06 0.1UF /1 6V

3 14 1 2
M_B _A0 47Ohm RN0 90 5D C09 05 0.1UF /1 6V
4 13 1 2
47Ohm RN0 90 5E C09 04 0.1UF /1 6V
8,11 M_B _B S1 5 12 1 2
47Ohm RN0 90 5F C09 03 0.1UF /1 6V
8,11 M_B _R AS # 6 11 1 2
47Ohm RN0 90 5G
8,11 M_C S #2 7 10
8 47Ohm 9 RN0 90 5H
8,11 M_O DT2
GND
1 47Ohm 16 RN0 90 6A
8,11 M_B _B S2
M_B _A12 2 47Ohm 15 RN0 90 6B
M_B _A5 3 47Ohm 14 RN0 90 6C @ C09 23 1 2 0.1UF /1 6V
M_B _A8 4 47Ohm 13 RN0 90 6D @ C09 24 1 2 0.1UF /1 6V

M_B _A9 47Ohm RN0 90 6E @ C09 25 0.1UF /1 6V
5 12 1 2
M_B _A11 47Ohm RN0 90 6F @ C09 26 0.1UF /1 6V
6 11 1 2
M_B _A3 47Ohm RN0 90 6G
7 10
M_B _A7 47Ohm RN0 90 6H
8 9
GND
A A
2 47Ohm 1 R09 03 C09 02 1 2 0.1UF /1 6V
8,11 M_C KE2
2 47Ohm 1 R09 04
8,11 M_C KE3
GND
Title : DDR2 termination

Cus to m
T14NH 2.0

5 4 3 2 1
5 4 3 2 1
U10 01A
T40 Y43 H_D#0

H_A #[35: 3]
3 H_DST BP #0 CPU_DSTBP0# CPU_D0#
U40 W42 H_D#1
3 H_A #[35: 3] 3 H_DST BN# 0 CPU_DSTBN0# CPU_D1# H_D#2
V41 Y40
3 H_DINV #0 CPU_DBI0# CPU_D2# H_D#3
W41
H_D #[63: 0] CPU_D3# H_D#4
3 H_D #[63: 0] 3 H_DST BP #1 W39 Y39
CPU_DSTBP1# CPU_D4# H_D#5
3 H_DST BN# 1 W37 V42
CPU_DSTBN1# CPU_D5#
D V35 Y41 H_D#6 D
3 H_DINV #1 CPU_DBI1# CPU_D6#
H_RE Q #[4:0 ] H_D#7
3 H_RE Q #[4:0 ] Y42
CPU_D7#
N37 P42 H_D#8
L36 U41 H_D#9
3 H_DST BN# 2 CPU_DSTBN2# CPU_D9#
N35 R42 H_D#1 0
T39 H_D#1 1
CPU_D11#
M39 T42 H_D#1 2
M41 T41 H_D#1 3
3 H_DST BN# 3 CPU_DSTBN3# CPU_D13# H_D#1 4
J41 R41
H_D#1 5
T43
CPU_D15#
H_A#3 H_D#1 6
AC34 CPU_A3# CPU_D16# W35
H_A#4 H_D#1 7
AE38 AA37
H_A#5 CPU_A4# CPU_D17# H_D#1 8
AE34 W33
H_A#6 CPU_A5# CPU_D18# H_D#1 9
AC37 W34
CPU_A6# CPU_D19#
H_A#7 AE37 AA36 H_D#2 0
CPU_A7# CPU_D20#
H_A#8 AE35 AA34 H_D#2 1
CPU_A8# CPU_D21#
H_A#9 AB35 AA38 H_D#2 2
CPU_A9# CPU_D22#
H_A#10 AF35 AA35 H_D#2 3
CPU_A10# CPU_D23#
H_A#11 AG35 U38 H_D#2 4
CPU_A11# CPU_D24#
H_A#12 AG39 U36 H_D#2 5
CPU_A12# CPU_D25#
H_A#13 AE33 U35 H_D#2 6
CPU_A13# CPU_D26#
H_A#14 AG37 U33 H_D#2 7
CPU_A14# CPU_D27#
H_A#15 AG38 U34 H_D#2 8
CPU_A15# CPU_D28#
H_A#16 H_D#2 9
AG34 CPU_A16# CPU_D29# W38
H_A#17 H_D#3 0
AN38 R33
CPU_A17# CPU_D30#
H_A#18 H_D#3 1
AL39 U37
H_A#19 CPU_A18# CPU_D31# H_D#3 2
AG33 N34
H_A#20 CPU_A19# CPU_D32# H_D#3 3
AL33 N33
H_A#21
CPU_A20# CPU_D33# H_D#3 4
AJ33 R34
C CPU_A21# CPU_D34# C
H_A#22 AN36 R35 H_D#3 5
CPU_A22# CPU_D35#
H_A#23 AJ35 P35 H_D#3 6
H_A#24
AJ37 R39
CPU_A24# CPU_D37#
H_A#25 AJ36 R37 H_D#3 8
H_A#26
AJ38 R38
CPU_A26# CPU_D39#
H_A#27 AL37 L37 H_D#4 0
CPU_A27# CPU_D40#
H_A#28 AL34 L39 H_D#4 1
CPU_A28# CPU_D41#
H_A#29 AN37 L38 H_D#4 2
H_A#30
AJ34 CPU_A30# CPU_D43# N36
+VC C P H_A#31 H_D#4 4
AL38 CPU_A31# CPU_D44# N38
H_A#32 H_D#4 5
AL35 J39
R10 12 62O hm H_BR 1# CPU_A32# CPU_D45# H_D#4 6
2 1 H_A#33 AN34 J38
H_A#34 AR39 J37
H_A#35 AN35 L42
CPU_A35# CPU_D48#
M42 H_D#4 9
CPU_D49#
3 H_ADS TB#0 AE36 P41 H_D#5 0
CPU_ADSTB0# CPU_D50# H_D#5 1
3 H_ADS TB#1 AK35 N41
CPU_ADSTB1# CPU_D51# H_D#5 2
N40
H_REQ #0
CPU_D52# H_D#5 3
AC38 M40
H_REQ #1
CPU_REQ0# CPU_D53# H_D#5 4
AA33 H40
H_REQ #2
AC39 K42
H_REQ #3
AC33 H41
H_REQ #4
AC35 L41
CPU_D58# H43
H_D#5 9
3 H_A DS # AD42 H42
CPU_ADS# CPU_D59# H_D#6 0
3 H_BN R# AD43 K41
CPU_BNR# CPU_D60# H_D#6 1
3 H_BR 0# AE40 J40
CPU_BR0# CPU_D61#
H_BR 1# H_D#6 2
Decoupling guide from Nvidia AL32
CPU_BR1# CPU_D62#
H39
AD39 M43 H_D#6 3
B
3 H_D B SY# CPU_DBSY# CPU_D63# B
3 H_D R DY# AD41
CPU_DRDY#
AB42 AA41
+V_DLL_DLCELL_AVDD 3 H_HIT# CPU_HIT# CPU_BPRI# H_BP R I# 3
3 H_HITM # AD40 AA40
CPU_HITM# CPU_DEFER# H_DEF ER# 3
+V_PLL_MCLK 3 H_L OC K# AC43
CPU_LOCK#
AE41 G42
+V_PLL_FSB 3 H_TRD Y# CPU_TRDY# BCLK_OUT_CPU_P
G41
CLK _C P U_B CLK 3
BCLK_OUT_CPU_N CLK _C P U_B CLK # 3

+V_PLL_CPU T100 3 1 E41
CPU_PECI T100 4
AJ41 AL43 1
1× ferrite bead 3 H_PR OC HOT#
AG43
CPU_PROCHOT# BCLK_OUT_ITP_P
AL42 1 T100 5
2 2
3,5,31 H_THR M TRI P# CPU_THERMTRIP# BCLK_OUT_ITP_N
1× 4.7 µF X5R ceramic 3 H_FE R R # AH40
CPU_FERR#
C10 03 C10 04
AL41 BC LK_F EEDB AC K_P 15PF /50V 15PF /50 V

1 1
1× 2.2 µF X7R ceramic F42
BCLK_OUT_NB_P
AK42 BC LK_F EEDB AC K_N @ @
20 MC P 79_ BS EL2 CPU_BSEL2 BCLK_OUT_NB_N
D42
20 MC P 79_ BS EL1 CPU_BSEL1 ( BCLK_FEEDBACK_P, BCLK_FEEDBACK_N) length:
20 MC P 79_ BS EL0 F41 AK41
CPU_BSEL0 BCLK_IN_N
+1. 05 VS
AJ40 (CLK_CPU_BCLK, CLK_CPU_BCLK#) + 1315 mil
BCLK_IN_P
217 mA L1001
1 2 3 H_RS #0 AC41 AF41

CPU_RS0# CPU_A20M# H_A20M # 3
1 1 3 H_RS #1 AB41 AH39
CPU_RS1# CPU_IGNNE# H_IGNN E# 3
60Ohm /100 M hz AC42 AH42
3 H_RS #2 CPU_RS2# CPU_INIT# H_INI T# 3
C10 02 C10 01 AF42
CPU_INTR H_INTR 3
Ira t= 500m A +1. 05 VS_F S BP LL_L AG27 AG41
2 4.7uF /6.3V 2 2.2UF /6 .3V
V_DLL_DLCELL_AVDD CPU_NMI H_NM I 3
MLC C /+/ -10 % MLC C /+/ -10%
AH27 AH41
V_PLL_MCLK CPU_SMI# H_SM I# 3
AG28
V_PLL_FSB
AH28 AH43
+VC C P V_PLL_CPU CPU_PWRGD H_PW RGD 3
081003 To change the C1002 from H38
1% R10 04 49.9Ohm CP U_VM L_C OM P_V CC CPU_RESET# H_CP UR ST# 3
1 2 AM39
2.2uF into 4.7uF --- Iverson BCLK_VML_COMP_VDD
1% 2 R10 03 1 49.9Ohm CP U_VM L_C OM P_G ND AM40 AM33
+VC C P BCLK_VML_COMP_GND CPU_SLP# H_CP US LP# 3
AN33
1% R10 01 49.9Ohm
CPU_DPSLP# H_DPS LP # 3
A
1 2 CP U_C OM P_V C C AM43 AM32 A
1% R10 02 49.9Ohm
CPU_COMP_VCC CPU_DPWR# H_DPW R# 3
1 2 CP U_C OM P_G N D AM42 AG42
CPU_COMP_GND CPU_STPCLK# H_STP C LK# 3
AN32
CPU_DPRSTP# H_DPR S TP# 3,80
MC P 79MH
1" max for BCLK_VML_COMP_VCC/GND
T/S : 5.5/8 mil
Title : MCP79:FSB
1" max for CPU_COMP_VCC/GND
T/S : 5.5/8 mil
Cus to m
T14NH 2.0

5 4 3 2 1
5 4 3 2 1
M_A _D QS [0:7 ] 7 M_B _DQS [0:7 ] 8
M_A _D QS #[0: 7] 7 M_B _DQS #[0:7 ] 8

U10 01B U1001 C
7 M_A _DQ[0:6 3]
8 M_B _DQ[ 0: 63]
M_A _DQ63 M_A _D QS 7
AL8 AL10
M_A _DQ62
MDQ0_63 MDQS0_7_P M_A _D QS #7 M_B _D Q6 3 M_B _D QS 7
AL9 AL11 AT4 AT2
M_A _DQ61 MDQ0_62 MDQS0_7_N M_A _D QS 6 M_B _D Q6 2 MDQ1_63 MDQS1_7_P M_B _D QS #7
AP9 AR8 AT3 AT1
M_A _DQ60 MDQ0_61 MDQS0_6_P M_A _D QS #6 M_B _D Q6 1 MDQ1_62 MDQS1_7_N M_B _D QS 6
AN9 AR9 AV2 AY2
M_A _DQ59
MDQ0_60 MDQS0_6_N M_A _D QS 5 M_B _D Q6 0
MDQ1_61 MDQS1_6_P M_B _D QS #6
D AL6 AW7 AV3 AY1 D
MDQ0_59 MDQS0_5_P MDQ1_60 MDQS1_6_N
M_A _DQ58 AL7 AW8 M_A _D QS #5 M_B _D Q5 9 AR4 BB6 M_B _D QS 5
MDQ0_58 MDQS0_5_N MDQ1_59 MDQS1_5_P
M_A _DQ57 AN6 AP13 M_A _D QS 4 M_B _D Q5 8 AR3 BA6 M_B _D QS #5
M_A _DQ56 AN7 AR13 M_A _D QS #4 M_B _D Q5 7 AU2 BA10 M_B _D QS 4
M_A _DQ55
MDQ0_56 MDQS0_4_N M_A _D QS 3 M_B _D Q5 6
MDQ1_57 MDQS1_4_P M_B _D QS #4
AR6 AV25 AU3 AY11
M_A _DQ54
MDQ0_55 MDQS0_3_P M_A _D QS #3 M_B _D Q5 5
MDQ1_56 MDQS1_4_N M_B _D QS 3
AR7 AW25 AY4 BB33
M_A _DQ53 AV6 AU30 M_A _D QS 2 M_B _D Q5 4 AY3 BA33 M_B _D QS #3
M_A _DQ52 AW5 AU29 M_A _D QS #2 M_B _D Q5 3 BB3 BB37 M_B _D QS 2
M_A _DQ51 AN10 AT35 M_A _D QS 1 M_B _D Q5 2 BC3 BA37 M_B _D QS #2
M_A _DQ50
AR5 MDQ0_50 MDQS0_1_N AU35 AW4 MDQ1_51 MDQS1_1_P BA43
M_A _DQ49 M_A _D QS 0 M_B _D Q5 0 M_B _D QS #1
AU6 AU39 AW3 AY42
M_A _DQ48
AV5 AT39 BA3 AT42
M_A _DQ47 MDQ0_48 MDQS0_0_N M_B _D Q4 8 MDQ1_49 MDQS1_0_P M_B _D QS #0
AU7 BB2 AT43
M_A _DQ46 MDQ0_47 M_B _D Q4 7 MDQ1_48 MDQS1_0_N
AU8 BB5
MDQ0_46 MDQ1_47
M_A _DQ45 AW9 M_B _D Q4 6 BA5
MDQ0_45 MDQ1_46
M_A _DQ44 AP11 M_B _D Q4 5 BA8
MDQ0_44 MDQ1_45
M_A _DQ43 AW6 M_B _D Q4 4 BC8
MDQ0_43 MDQ1_44
M_A _DQ42 AY5 AV17 M_B _D Q4 3 BB4
MDQ0_42 MRAS0# M_A _RA S # 7,9 MDQ1_43
M_A _DQ41 AU9 AP17 M_B _D Q4 2 BC4 AW16
MDQ0_41 MCAS0# M_A _CA S # 7,9 MDQ1_42 MRAS1# M_B _R AS # 8,9
M_A _DQ40 AV9 AR17 M_B _D Q4 1 BA7 BA15
MDQ0_40 MWE0# M_A _W E# 7,9 MDQ1_41 MCAS1# M_B _C AS # 8,9
M_A _DQ39 AU11 M_B _D Q4 0 AY8 BA16
MDQ0_39 MDQ1_40 MWE1# M_B _W E# 8,9
M_A _DQ38 AV11 M_B _D Q3 9 BA9
MDQ0_38 MDQ1_39
M_A _DQ37 AV13 AP23 M_B _D Q3 8 BB10
MDQ0_37 MBA0_2 M_A _BS 2 7, 9 MDQ1_38
M_A _DQ36 M_B _D Q3 7
AW13 AP19 BB12 BB29
MDQ0_36 MBA0_1 M_A _BS 1 7, 9 MDQ1_37 MBA1_2 M_B _B S2 8,9
M_A _DQ35 M_B _D Q3 6
AR11 MDQ0_35 MBA0_0 AW17 AW12 MDQ1_36 MBA1_1 BB18 M_B _B S1 8,9
M_A _BS 0 7, 9
M_A _DQ34 M_B _D Q3 5
AT11 BB8 BB17 M_B _B S0 8,9
M_A _DQ33 MDQ0_34 M_B _D Q3 4 MDQ1_35 MBA1_0
AR14 BB9
M_A _DQ32 MDQ0_33 M_B _D Q3 3 MDQ1_34
AU13 M_A _A[0:1 4] 7,9 AY12
M_A _DQ31
MDQ0_32 M_B _D Q3 2
MDQ1_33
AR26 AR23 M_A _A14 BA12 M_B _A [ 0:14 ] 8, 9
C M_A _DQ30
MDQ0_31 MA0_14 M_B _D Q3 1
MDQ1_32 M_B _A14 C
AU25 AU15 M_A _A13 BC32 BA29
M_A _DQ29
MDQ0_30 MA0_13 M_A _A12 M_B _D Q3 0
MDQ1_31 MA1_14 M_B _A13
AT27 AN23 AW32 BA14
M_A _DQ28
MDQ0_29 MA0_12 M_A _A11 M_B _D Q2 9
MDQ1_30 MA1_13 M_B _A12
AU27 AW21 BA35 AW28
M_A _DQ27
MDQ0_28 MA0_11 M_A _A10 M_B _D Q2 8
MDQ1_29 MA1_12 M_B _A11
AP25 AN19 AY36 BC28
M_A _DQ26
MDQ0_27 MA0_10 M_A _A9 M_B _D Q2 7
MDQ1_28 MA1_11 M_B _A10
AR25 AV21 BA32 BA17
M_A _DQ25
MDQ0_26 MA0_9 M_A _A8 M_B _D Q2 6
MDQ1_27 MA1_10 M_B _A9
AP27 AR22 BB32 BB28
M_A _DQ24
MDQ0_25 MA0_8 M_A _A7 M_B _D Q2 5
MDQ1_26 MA1_9 M_B _A8
AR27 AU21 BA34 AY28
M_A _DQ23
MDQ0_24 MA0_7 M_A _A6 M_B _D Q2 4
MDQ1_25 MA1_8 M_B _A7
AP29 AP21 AY35 BA28
M_A _DQ22
MDQ0_23 MA0_6 M_A _A5 M_B _D Q2 3
MDQ1_24 MA1_7 M_B _A6
AR29 MDQ0_22 MA0_5 AR21 BC36 MDQ1_23 MA1_6 AY27
M_A _DQ21 M_A _A4 M_B _D Q2 2 M_B _A5
AP31 AN21 AW36 BA27
M_A _DQ20
MDQ0_21 MA0_4 M_A _A3 M_B _D Q2 1
MDQ1_22 MA1_5 M_B _A4
AR31 AV19 BA39 BA26
M_A _DQ19 MDQ0_20 MA0_3 M_A _A2 M_B _D Q2 0 MDQ1_21 MA1_4 M_B _A3
AV27 AU19 AY40 BB26
M_A _DQ18 MDQ0_19 MA0_2 M_B _D Q1 9 MDQ1_20 MA1_3 M_B _A2
AN29 AT19 M_A _A1 BA36 BA25
MDQ0_18 MA0_1 MDQ1_19 MA1_2
M_A _DQ17 AV29 AR19 M_A _A0 M_B _D Q1 8 BB36 BB25 M_B _A1
MDQ0_17 MA0_0 MDQ1_18 MA1_1
M_A _DQ16 AN31 M_B _D Q1 7 BA38 BA18 M_B _A0
MDQ0_16 MDQ1_17 MA1_0
M_A _DQ15 AU31 M_B _D Q1 6 AY39
MDQ0_15 MDQ1_16
M_A _DQ14 AR33 M_B _D Q1 5 BB40
MDQ0_14 MDQ1_15
M_A _DQ13 AV37 M_B _D Q1 4 AW40
MDQ0_13 MDQ1_14
M_A _DQ12 AW37 M_B _D Q1 3 AV42
MDQ0_12 MDQ1_13
M_A _DQ11 AT31 M_B _D Q1 2 AV41
MDQ0_11 MDQ1_12
M_A _DQ10 AV31 AW33 M_B _D Q1 1 BA40
MDQ0_10 MCLK0A_2_P MDQ1_11
M_A _DQ9 AT37 AV33 M_B _D Q1 0 BC40 BA42
MDQ0_9 MCLK0A_2_N MDQ1_10 MCLK1A_2_P
M_A _DQ8 M_B _D Q9
AU37 AW42 BB42
MDQ0_8 MDQ1_9 MCLK1A_2_N
M_A _DQ7 M_B _D Q8
AW39 BA24 AW41
MDQ0_7 MCLK0A_1_P M_C LK_D DR1 7 MDQ1_8
M_A _DQ6 M_B _D Q7
AV39 AY24 AT40 BB22
M_A _DQ5 MDQ0_6 MCLK0A_1_N M_C LK_D DR#1 7
M_B _D Q6 MDQ1_7 MCLK1A_1_P M_C LK_D DR3 8
AR37 AT41 BA22
M_A _DQ4 MDQ0_5 M_B _D Q5 MDQ1_6 MCLK1A_1_N M_C LK_D DR#3 8
AR38 BB20 AP41
M_A _DQ3
MDQ0_4 MCLK0A_0_P M_C LK_D DR0 7
M_B _D Q4
MDQ1_5
AV38 BC20 AN40 BA19
M_A _DQ2
MDQ0_3 MCLK0A_0_N M_C LK_D DR#0 7
M_B _D Q3
MDQ1_4 MCLK1A_0_P M_C LK_D DR2 8
AW38 AU40 AY19
B
M_A _DQ1
MDQ0_2 M_B _D Q2
MDQ1_3 MCLK1A_0_N M_C LK_D DR#2 8 B
AR35 AU41
M_A _DQ0
MDQ0_1 M_B _D Q1
MDQ1_2
AP35 AT15 M_C S #1 7,9 AR41
MDQ0_0 MCS0A_1# M_B _D Q0
MDQ1_1
AR18 M_C S #0 7,9 AP42 BB14 M_C S #3 8,9
MCS0A_0# MDQ1_0 MCS1A_1#
7 M_A _DM [0..7] BB16 M_C S #2 8,9
M_A _DM 7
MCS1A_0#
AN5
M_A _DM 6
MDQM0_7 8 M_B _D M [0:7 ]
M_B _DM 7
AU5 AP15 AT5
M_A _DM 5
MDQM0_6 MODT0A_1 M_O DT1 7,9
M_B _DM 6
MDQM1_7
AR10 AV15 BA2 BB13
M_A _DM 4
M_B _DM 5
AN13 AY7 AY15
M_A _DM 3
MDQM0_4 MDQM1_5 MODT1A_0 M_O DT2 8,9
AN27 M_B _DM 4 BA11
M_A _DM 2
MDQM0_3 MDQM1_4
AW29 AU23 M_B _DM 3 BB34
MDQM0_2 MCKE0A_1 M_C KE1 7,9 MDQM1_3
M_A _DM 1 M_B _DM 2
AV35 AT23 M_C KE0 7,9 BB38 AY31 M_C KE3 8,9
M_A _DM 0 MDQM0_1 MCKE0A_0 MDQM1_2 MCKE1A_1
AR34 M_B _DM 1 AY43 BB30
MDQM0_0 MDQM1_1 MCKE1A_0 M_C KE2 8,9
M_B _DM 0 AR42
MDQM1_0
MC P 79MH MC P 79 MH
0.9V_VT T_REF 83
+1. 8V
2
2
R11 03
R11 01
0O hm
1KOhm
1%
1
@
1
A M_V REF _M CP 79 7,8 A
2
1
R11 02 C11 01
1KOhm
1%
2
0.1UF /1 0V
MLC C /+/ -10% Title : MCP79:MEM PARTS 0&1
@
1 Engineer: Iverson_Qiu
GND GND
Cus to m
T14NH 2.0

5 4 3 2 1

Pegatron T14NH REV 2.0 (Incompleto) PDF

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Pegatron T14NH REV 2.0 (Incompleto) PDF

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5 4 3 2 1

T14NH Block Diagram

FAN + SENSOR CPU VCORE

FSB 1066MHz BAT & CHARGER

ITE/IT8512 RJ-45 CON

PAG E 10,11 ,12,13,14, 15 ,16,17 ,18,19 ,20

Realtek/ALC663 USB 2.0 CON x2

USB 2.0 CON x2

SATA HDD Title : BLOCK DIAGRAM

Date: Mon da y, Ju ne 22 , 2 00 9 She et 1 of 94

T14NH Schematic Index

02 Schematic Information GPIO 02 / / / GPIO 35 / / /

38 AUDIO_HP_MIC GPIO 14 / / / GPIO 47 / / /

56 LED GPIO 25 / / / GPIO 59 / / /

85 POWER_+VCORE_MCP & +1.1VSUS

Title : Schematic Information

Date: Mon da y, Ju ne 22 , 2 00 9 She et 2 of 94

@ R03 43 150 Ohm 1% +3V S

+VC C P 1 R03 38 2 0Ohm H_PR OC HOT_S #

Place R0304 & R0348 for XDP function

Date: Mon da y, Ju ne 22 , 2 00 9 She et 3 of 94

Date: Mon da y, Ju ne 22 , 2 00 9 She et 4 of 94

+VC OR E +VCCP Decoupling Capacitor

C05 14 C05 38 C05 35 C05 34 C05 37 C05 36

2 2 0.1UF /1 0V 2 0.1UF /1 0V 2 0.1UF /1 0V 2 0.1UF /1 0V 2 0.1UF /1 0V 2 0.1UF /1 0V

VCORE 22uF/10V r 10uF * 36pcs

+VCORE Mid-Frequency Capacitor

+VCCP Decoupling Capacitor

15 ,56 PC I_R ST# 0

Thermal Trip signal (From CPU to ICH-9M and sequence)

Title : CPU CAPS

Date: Mon da y, Ju ne 22 , 2 00 9 She et 5 of 94

5.2H M_A _D Q[63: 0] 11

DDR _DIM M _2 00P

Layout Note: Place these Caps near SO DIMM 0

Title : DDR2 SO-DIMM_0

Date: Mon da y, Ju ne 22 , 2 00 9 She et 7 of 94

Title : DDR2 SO-DIMM_1

Date: Mon da y, Ju ne 22 , 2 00 9 She et 8 of 94

7,11 M_A _A[13:0 ]

8,11 M_B _A[ 13 :0]

D M_A _A 2 1 47Ohm 16 RN0 90 1A D

M_A _A 0 2 47Ohm 15 RN0 90 1B

3 47Ohm 14 RN0 90 1C @ C09 15 1 2 0.1UF /1 6V

M_A _A 4 5 47Ohm 12 RN0 90 1E @ C09 17 1 2 0.1UF /1 6V

M_A _A 11 6 47Ohm 11 RN0 90 1F @ C09 18 1 2 0.1UF /1 6V

M_A _A 7 7 47Ohm 10 RN0 90 1G

M_A _A 14 8 47Ohm 9 RN0 90 1H

M_A _A 12 4 47Ohm 13 RN0 90 2D @ C09 20 1 2 0.1UF /1 6V

5 47Ohm 12 RN0 90 2E @ C09 21 1 2 0.1UF /1 6V

M_A _A 3 8 47Ohm 9 RN0 90 3H

2 47Ohm 1 R09 01 C09 01 1 2 0.1UF /1 6V

M_B _A14 2 47Ohm 1 R09 06 MLC C /+8 0 -20 %

M_B _A6 1 47Ohm 16 RN0 90 5A

M_B _A2 47Ohm RN0 90 5C C09 06 0.1UF /1 6V

M_B _A8 4 47Ohm 13 RN0 90 6D @ C09 24 1 2 0.1UF /1 6V

Title : DDR2 termination

Date: Mon da y, Ju ne 22 , 2 00 9 She et 9 of 94

T40 Y43 H_D#0

BCLK_OUT_CPU_N CLK _C P U_B CLK # 3

AL41 BC LK_F EEDB AC K_P 15PF /50V 15PF /50 V

1 2 3 H_RS #0 AC41 AF41

Date: Mon da y, Ju ne 22 , 2 00 9 She et 10 of 94