DISCUSSION/COMPARISON OF RISC AND CISC ARCHITECTURES

Abstract
Reduced Instruction Set Computers (RISC) have received much attention
in the last few years. The RISC design philosophy has led to a profound
re-evaluation of long held beliefs in the computer architecture community.
Yet the precise definition of what "RISC design" really means, is
something which has been obscured by the unfounded claims of some
microprocessor manufacturers and by the reductionist definitions found
in the popular computer literature. The recent emergence of PowerPC
(RISC)-based computers as serious contenders in a marketplace dominated
by Intel (CISC - Complex Instruction Set Computers) has stoked the
fires of a great debate. Which is better: RISC or CISC? RISC backers
contend that their chips run faster and are generally more powerful
than CISC chips, but Intel and other CISC proponents adamantly oppose
this view. Reduced instruction set would seem to imply that RISC processors
support fewer instructions than their CISC counterparts. But is this
really the case? And if it is, wouldn't that mean that a RISC processor
runs software more slowly, since it has to execute more instructions
to carry out complex tasks such as recalculating cells in a large
spreadsheet or drawing a graphical image on-screen? What, if anything,
is the advantage of a smaller instruction set?
Abstract
In this paper we seek to answer these questions and outline exactly
what it is that makes a processor RISC or CISC. The truth may be surprising.
We will be concentrating on Power PC (RISC) and Intel (CISC) as a
basis of comparison as an example whereever required through out the
discussion.
1 INTRODUCTION
RISC architectures are quickly becoming the dominant CPU design philosophy.
Although new implementations of the major CISC architectures appeared,
most of the investment on new architectures went towards RISC. In
the chapters to come we are going to present a perspective on RISC
and CISC architectures intended to help the readers understand the
technical details and the significance of both the architectures.
We discuss in the second chapter important characteristics of CISC
design with respect to its instuction set architecture, hardware architecture,
its advantages and disadvantages. The third chapter is devoted towards
RISC architecture and design, advantages and hazards. In chapter four
we elaborate on comparison of CISC and RISC architectures taking into
consideration different aspects such as ISA, speed, complexity, application,
OS support, support of software tools and marketability. Chapter five
talks about some of the latest trends in this field. Finally chapter
six gives a brief conclusion of this paper.
2 CISC
2.1 Characteristics of a CISC design
CISC, which stands for Complex Instruction Set Computer, is a philosophy
for designing chips that are easy to program and which make efficient
use of memory. Each instruction in a CISC instruction set might perform
a series of operations inside the processor. This reduces the number
of instructions required to implement a given program, and allows
the programmer to learn a small but flexible set of instructions.
While the chips that emerged from the 1970s and 1980s followed their
own unique design paths, most were bound by the "CISC Design Decisions"--
1)Use microcode 2) Build rich instruction sets 3) Build high-level
instruction sets
Taken together, these three decisions led to the CISC philosophy which
drove all computer designs until the late 1980s, and is still in major
use today. These chips all had similar instruction sets, and similar
hardware architectures. The Instruction Sets were designed for the
convenience of the assembly language programmer due to the fact that
most early machines were programmed in assembly language and memory
was slow and expensive and hence the CISC philosophy made sense. However
this makes hardware designs fairly complex. Most common microprocessor
designs including the Intel(80x86 and Motorola 68K series follow the
CISC philosophy.
However recent changes in software and hardware technology have forced
a re-examination of CISC. But first, let's take a closer look at some
of the important characteristics of the CISC Instruction Set Architecture
and Hardware Architecture.
2.2 Characteristics of CISC Instruction Sets
* Supports register to register, register to memory, and memory to
register commands.
* A 2-3 operand format, where instructions have a source and a destination.
* Multiple addressing modes for memory, including specialized modes
for indexing through arrays.
* Variable length instructions where the length often varies according
to the addressing mode.
* Instructions require multiple clock cycles to execute. If an instruction
requires additional information before it can run (for example,
if the processor needs to read in two memory locations before operating
on them), collecting the extra information will require extra clock
cycles. As a result, some CISC instructions will take longer than
others to execute.
2.3 Characteristics of CISC Hardware Architecture
* Complex instruction-decoding logic: Driven by the need for a single
instruction to support multiple addressing modes it incorporates
complex instruction-decoding logic.
* A small number of general purpose registers: This is the direct result
of having instructions which can operate directly on memory and
the limited amount of chip space not dedicated to instruction decoding,
execution, and microcode storage.
* Several special purpose registers: Many CISC designs set aside special
registers for the stack pointer, interrupt handling, and so on.
This can simplify the hardware design somewhat, at the expense of
making the instruction set more complex.
* A "Condition code" register which is set as a side-effect of most
 instructions. This register reflects whether the result of the last
operation is less than, equal to, or greater than zero, and records
if certain error conditions occur.
CISC processors were designed to execute each instruction completely
before beginning the next instruction. Even so, most processors break
the execution of an instruction into several definite stages; as soon
as one stage is finished, the processor passes the result to the next
stage. The steps involved are given below;
* An instruction is fetched from main memory.
* The instruction is decoded: The controlling code from the microprogram
identifies the type of operation to be performed, where to find
the data on which to perform the operation, and where to put the
result. If necessary, the processor reads in additional information
from memory.
* The instruction is executed: The controlling code from the microprogram
determines the circuitry/hardware that will perform the operation.
* The results are written to memory.
In an ideal CISC machine, each complete instruction would require only
one clock cycle (which means that each stage would complete in a fraction
of a cycle). In fact, this is the maximum possible speed for a machine
that executes 1 instruction at a time.
In reality, some instructions may require more than one clock per
stage. However, a CISC design can tolerate this slowdown since the
idea behind CISC is to keep the total number of cycles small by
having complicated things happen within each cycle.
2.4 CISC and the Classic Performance Equation
The usual equation for determining performance is,
ExecutionTime=N*CPI*CCT
Where N is the Instruction Count, CPI is the Clock Cycle Per Instruction
and CCT is the Clock Cycle Time.
This allows to speed up a processor in 3 different ways
1. Use fewer instructions for a given task
2. Reduce the number of cycles for some instructions
3. Speed up the clock (decrease the cycle time)
CISC tries to reduce the number of instructions for a program whereas
RISC tries to reduce the cycles per instruction.
2.5 Advantages of CISC
Some of the advantages of CISC architecture are listed below.
* Microprogramming is as easy as assembly language to implement, and
much less expensive than hardwiring a control unit. The ease of
microcoding new instructions allows designers to make CISC machines
 upwardly compatible.
* A new computer could run the same programs as earlier computers because
the new computer would contain a superset of the instructions of
the earlier computers.
* As each instruction became more capable, fewer instructions could
be used to implement a given task. This made more efficient use
of the relatively slow main memory.
* Because microprogram instruction sets can be written to match the
constructs of high-level languages, the compiler does not have to
be as complicated.
2.6 Disadvantages of CISC
The CISC philosophy had its own problems, including:
* Earlier generations of a processor family generally were contained
as a subset in every new version so, instruction set & chip hardware
become more complex with each generation of computers.
* So that as many instructions as possible could be stored in memory
with the least possible wasted space, individual instructions could
be of almost any length-this means that different instructions will
take different amounts of clock time to execute, slowing down the
overall performance of the machine.
* Many specialized instructions aren't used frequently enough to justify
their existence - approximately 20% of the available instructions
are used in a typical program.
* CISC instructions typically set the condition codes as a side effect
of the instruction. Not only does setting the condition codes take
time, but programmers have to remember to examine the condition
code bits before a subsequent instruction changes them.
3 RISC
3.1 INTRODUCTION
RISC is an acronym for Reduced Instruction Set Computer. Reduced Instruction
Set Computers have received much attention in the last few years.
The definition of "RISC design" has been obscured by manufacturers
but, it basically is a type of microprocessor that recognizes a relatively
limited number of instructions.
In the mid-1970's advances in semiconductor technology began to reduce
the difference in speed between main memory and processor chips. As
memory speed increased, and high-level languages displaced assembly
language, the major reasons for CISC began to disappear, and computer
designers began to look at ways computer performance could be optimized
beyond just making faster hardware.
3.2 Characteristics of RISC Architecture and Design
* Simple Instruction Set: In a RISC machine, the instruction set contains
simple, basic instructions, from which more complex instructions
can be composed. Each instruction is the same length, so that it
may be fetched in a single operation. Most instructions complete
 in one machine cycle, which allows the processor to handle several
instructions at the same time.
* Large Register Set: Most RISC processors normally do have a large
register set.
* Uniform Pipeline: A uniform pipeline is the most fundamental characteristic
of RISC hardware because it both increases cycle time and parallelism.
This pipelining is a key technique used to speed up RISC machines.
* Memory Speed: Memory speed issues are commonly solved using caches.
A cache is a section of fast memory placed between the processor
and slower memory. When the processor wants to read a location in
main memory, that location is also copied into the cache. Subsequent
references to that location can come from the cache, which will
return a result much more quickly than the main memory. RISC-based
systems typically contain large memory caches, usually on the chip
itself. This is known as a first-level cache.
* Load/Store Architecture: If all operands for arithmetic and logical
operations are located in registers, it is obvious that these registers
have to be loaded first with the necessary data. This is done in
RISC processors using a "load" instruction, which can access bytes,
halfwords or complete words. A "store" instruction transfers the
contents of registers to memory. Without special measures the processor
must wait after each load instruction for the memory to deliver
the wished data - the pipeline stalls. RISC processors avoid this
problem using a "delayed" load.
* Fixed Instruction Length: The simplest technique for avoiding a variable
fetch time as in CISC is to encode each instruction using a fixed
one word format. The fetch stage has in this way a fixed duration
and one instruction can be issued each cycle to the decoding stage
under normal pipeline flow. The decoding stage does not need to
request additional instruction bytes according to the encoding of
the instruction and there is no need for any additional control
lines between the fetch and decode stages.
* Delayed Branching: The branching decision is made very early in the
execution path of RISC processors - possibly already in the decode
stage. This can be done only if the branching condition tests are
very simple, like for example a register compare with zero or a
condition flag test. At the end of the decode phase the processor
can start fetching instructions from the new target. But in this
decode cycle the next instruction after the branch has already been
fetched. In order to avoid stall cycles this instruction can be
executed. In this case the branch is a delayed branch. From the
programmers point of view the branch is postponed until after the
next instruction is executed.
3.3 Advantages of RISC
Implementing a processor with a simplified instruction set design provides
several advantages over implementing a comparable CISC design:
* Speed: Since a simplified instruction set allows for a pipelined,
superscalar design, RISC processors often achieve 2 to 4 times the
performance of CISC processors using comparable semiconductor technology
and the same clock rates.
* Simpler Hardware: Because the instruction set of a RISC processor
is so simple, it uses up much less chip space; extra functions,
such as memory management units or floating point arithmetic units
can also be placed on the same chip. Smaller chips allow a semiconductor
manufacturer to place more parts on a single silicon wafer, which
can lower the per-chip cost dramatically.
* Shorter Design Cycle: Since RISC processors are simpler than corresponding
CISC processors, they can be designed more quickly, and can take
advantage of other technological developments sooner than corresponding
CISC designs, leading to greater leaps in performance between generations.
3.4 The hazards of RISC
The transition from a CISC design strategy to a RISC design strategy
isn't without its problems.
* Code Quality: The performance of a RISC processor depends greatly
on the code that it is executing. If the compiler does a poor job
of instruction scheduling, the processor can spend quite a bit of
time stalling: waiting for the result of one instruction before
it can proceed with a subsequent instruction. This makes the performance
of a RISC application depend critically on the quality of the code
generated by the compiler.
* Debugging: Unfortunately, instruction scheduling can make debugging
difficult. If scheduling (and other optimizations) are turned off,
the machine-language instructions show a clear connection with their
corresponding lines of source. However, once instruction scheduling
is turned on, the machine language instructions for one line of
source may appear in the middle of the instructions for another
line of source code. Such an intermingling of machine language instructions
not only makes the code hard to read, it can also defeat the purpose
of using a source-level compiler, since single lines of code can
no longer be executed by themselves.
* Code Expansion: Since CISC machines perform complex actions with
a single instruction, where RISC machines may require multiple instructions
for the same action, code expansion can be a problem. Code expansion
refers to the increase in size that you get when you take a program
that had been compiled for a CISC machine and re-compile it for
a RISC machine.
* System Design: Another problem that RISC machines face is that they
require very fast memory systems to feed them instructions. RISC-based
systems typically contain large memory caches, usually on the chip
itself. This is known as a first-level cache.
4 COMPARING RISC with CISC
In this section we compare the two architectures from different aspects.
4.1 Speed, ISA and Complexity
Any program, no matter how complex, ultimately translates into byte-size
series of instructions. Modern application programs often contain
hundreds of thousands of lines of code. Operating systems are even
more complex: Microsoft Windows 95 contains about 10 million lines,
most of it written in C, and Windows NT contains more than 5 million
lines written in C and C++. Translating a million lines of C code
into a set of instructions from 1 to perhaps 20 or 30 instructions
each, that's why software today is so complicated.
When a program runs, the microprocessor reads, or fetches, the instructions
one by one and executes them. It takes time to fetch an instruction
and more time to decode that instruction to determine what the 1s
and 0s represent. And once the instruction begins executing, it takes
a certain number of clock cycles to run to completion.
One way to make a microprocessor run software faster is to increase
the clock speed. Another way is to decrease the number of clocks required
to execute an instruction. Everything else being equal, a 100-MHz
microprocessor will deliver only half the performance of a 50-MHz
microprocessor if the former requires 4 clocks per instruction but
the latter requires just 1. Traditionally, CISC microprocessors like
the x86 have required anywhere from 1 to more than 100 clocks to complete
an instruction. For example, the mul (multiply) instruction on the
8088 that powered the original IBM PC required up to 133 clocks to
multiply two 16-bit integers. A register-to-register mov, by contrast,
required only 2 clocks. The same multiply on a 486 requires as few
as 13 clocks, and mov requires just 1. That's one reason why one can't
compare, say, a 25-MHz 386 with a 120-MHz Pentium based on clock speeds
alone. The instruction timings are different, and with each successive
generation of the x86, Intel has reduced the clock counts for individual
instructions.
Since the dawn of the microprocessor age, the holy grail for chip designers
has been to develop a CPU that requires 1 clock cycle per instruction--not
just certain instructions, but every instruction. Given an unlimited
number of transistors to work with, a microprocessor can be made into
a 1-clock-per-instruction device. But the transistors on a CPU have
to fit into a limited amount of real estate, so transistor counts
are limited. RISC's original goal was to limit the number of instructions
on the chip so that each could be allocated enough transistors to
make it execute in one clock cycle. Rather than provide a mul instruction,
for example, the microprocessor's designers might make sure that add
executes in one clock. Then a compiler could multiply a and b by adding
a to itself b times or b to itself a times.
A CISC CPU could multiply 5 by 10 like this:
mov ax,10
mov bx,5
mul bx
But a RISC chip might do it like this:
mov ax,0
mov bx,10
mov cx,5
Begin:
add ax, bx
loop Begin ; loop cx times
However now modern RISC chips do have multiply instructions. The RISC
version uses more instructions, but if the instruction timings are
low enough, the RISC chip might do in 20 clocks what the CISC chip
requires 100 clocks to do. Given a finite number of transistors to
work with, there is a trade-off between instruction-set complexity
and instruction timing. RISC seeks to strike a better balance between
the two to produce a faster microprocessor. The transistors a RISC
chip saves on large instructions can be used for cache, pipelines,
and more registers.
So what actually distinguishes a RISC chip from a CISC chip?
In reality, there's nothing RISC about a lot of RISC chips any more--that
is, their instruction sets aren't really reduced. Today's RISC chips
often have richer and more complex instruction sets than CISC chips.
The PowerPC 601, for example, supports more instructions than the
Pentium. Yet the 601 is considered a RISC chip, while the Pentium
is definitely CISC.
Since seventies the number of transistors that can pack onto a silicon
wafer has steadily increased. The sheer number of transistors, combined
with architectural improvements to the chip itself, allows a Pentium
to execute two instructions per clock cycle.The Pentium doesn't actually
perform an instruction in half a clock cycle; many instructions still
require multiple clocks. But pipelining allows instructions to be
overlapped, so that five instructions each requiring 5 clock cycles
can be completed in a total of 5 clocks--an average of one instruction
per clock. And the Pentium's two independent execution units, which
qualify the Pentium as a superscalar microprocessor, permit two pipelines
to run in parallel.
So much for cutting out instructions to make the remaining ones faster.
With today's transistor budgets it seems that all chips average 1
clock or less per instruction, no matter how complex their instruction
sets.
4.2 Architecture
The difference between RISC and CISC is no longer one of Instruction
Sets but what really distinguishes RISC from CISC these days is more
deeply rooted in the chip architectures.
RISC microprocessors have more general-purpose registers. The best
way to write fast code is to maximize the number of operations performed
"on-chip" and minimize the number of accesses to data stored in memory.
More registers make this goal more attainable. Register accesses are
nearly instantaneous; memory accesses take time. A Pentium has just
eight general-purpose registers, but a PowerPC chip has 32. RISC microprocessors
use load/store architectures. CPU instructions that operate on data
in memory--for example, integer add instructions that add x to y,
where y is a value stored in memory--are among the most expensive
in terms of clock cycles. In addition, the implementation of these
instructions tends to require a disproportionate number of transistors.
RISC designs minimize the number of instructions that access memory
in favor of load/store architectures that require y to be loaded into
a register before x is added, then "stored" back to memory. RISC microprocessors
use uniform instruction lengths. On a Pentium, the length of one instruction
can vary from as little as 1 byte to as many as 7 (more if 32-bit
code is executed in a 16-bit segment). RISC designers, on the other
hand, favor making all instructions the same length--usually 32 bits.
This simplifies the instruction-fetching and decoding logic and also
means an entire instruction can be retrieved with one 32-bit memory
access.
4.3 Support of Software Tools & Compiler
RISC processor makers are looking to take on the dominance of Intel
and its CISC architecture at the desktop level. To do that, RISC system
vendors will have to capture the hearts and minds of the software
developers who will create the applications.
The key to the success of this effort is the ability to deliver software
that solves user problems and takes full advantage of RISC architectures.
To create this software, developers need tools. The availability
of tools used to create applications for any given platform is a
requirement for a platform to prosper. For some RISC platforms such
as PA-RISC and SPARC, those tools are readily available. Newer processors
such as the PowerPC and the Alpha are not so well endowed at this
time but further development will enhance the chances for the successful
deployment of RISC-based systems on the desktop that Intel dominates.
RISC chips are generally faster than popular CISC processors, such
as the Pentium. For software developers, however, clock speed isn't
the only quality by which they judge a computer system. The performance
of any given processor is closely tied to compiler and, more precisely,
to optimization technology.
CISC-oriented compilers from companies such as Microsoft, Borland International,
Symantec, and others compete largely on the basis of ease of use and
slick development environments--the "front end" of the development
task. In the code-generating "back end," processor-independent optimizations
are the rule, owing to the complex nature of the instruction set and
(prior to the Pentium) the absence of superscalar, pipelined architectures.
In contrast, RISC compilers typically have so-so front ends and rely
heavily on processor-dependent optimizations in the back end to squeeze
maximum performance from the hardware. Issues such as instruction
scheduling, cache management, and register tracking are vital in light
of the memory-intensive and pipelined nature of RISC chips and become
even more important for superscalar architectures. Proper optimization
can improve RISC benchmark results by as much as 50 percent over nonoptimized
code
4.4 Operating System Support
The various operating systems some of the RISC processors support
+-----------------++----------------------------------------------------+
| CPU ||OS |
+-----------------++----------------------------------------------------+
+-----------------++----------------------------------------------------+
|PowerPC System 7 ||AIX,OS/2 (IBM), Solaris, Unix PA-RISC HP-UX, MPE/iX |
+-----------------++----------------------------------------------------+
+-----------------++----------------------------------------------------+
| SPARC Solaris ||SunOS |
+-----------------++----------------------------------------------------+
+-----------------++----------------------------------------------------+
| Mips R4x00 ||Windows NT, Unix |
+-----------------++----------------------------------------------------+
+-----------------++----------------------------------------------------+
| DEC Alpha ||Windows NT, OpenVMS, OSF/1 |
+-----------------++----------------------------------------------------+

The various operating systems some of the CISC processors support

+--------------------------++-----------------------------------+
| CPU ||OS |
+--------------------------++-----------------------------------+
+--------------------------++-----------------------------------+
|Intel Pentium, Cyrix, AMD ||Windows NT, Windows 98, Windows 95 |
+--------------------------++-----------------------------------+

4.5 Application
RISC microprocessors emphasize floating-point performance. Traditionally,
the stronghold of RISC machines has been the scientific community,
whose applications do more floating-point math than a typical work
processor or spreadsheet. Therefore, RISC microprocessors nearly always
have high-performance floating-point units built in. Only recently,
with the Pentium, has entire line of Intel chips included a math processor(remem
ber
the 486SX?), and integer operations are still considered the Pentium's
mainstay.
5 CONCLUSION
As we have seen, Reduced Instruction Set Computing (RISC) is an evolution
in computer architectures that emphasizes speed and cost-effectiveness
over ease of assembly-language programming and the conservation of
memory. In addition, RISC-based designs will continue to grow in speed
and ability much more rapidly than comparable CISC designs over the
next several years.
In general, RISC designers have been quick to adopt cutting-edge technologies
such as on-chip code and data caches, superscalar designs, instruction
pipelining, and branch prediction logic--anything to give their chips
a performance boost.
There is still considerable controversy among experts about the ultimate
value of RISC architectures. Its proponents argue that RISC machines
are both cheaper and faster, and are therefore the machines of the
future. Skeptics note that by making the hardware simpler, RISC architectures
put a greater burden on the software. They argue that this is not
worth the trouble because conventional microprocessors are becoming
increasingly fast and cheap anyway.
To some extent, the argument is becoming moot because CISC and RISC
implementations are becoming more and more alike. Many of today's
RISC chips support as many instructions as yesterday's CISC chips.
And today's CISC chips use many techniques formerly associated with
RISC chips.
The designations RISC and CISC are no longer meaningful in the original
sense; what counts is how fast a chip can execute the instructions
it is given and how well it runs existing software. The impact on
performance can be more than simply additive; synergism results from
good design. These days, both RISC and CISC manufacturers are pulling
out all the stops to get an edge on the competition.
6 References
1. Michael Slater [1992]. ``A Guide to RISC Microprocessors,'' Academic
Press, Inc.
2. John L. Hennessy and David A. Patterson [1996]. ``Computer Architecture:
A Quantitative Approach,'' Morgan Kauffman Publishers.
3. David A. Patterson and John L. Hennessy [1994]. ``Computer Organization
and Design: The Hardware/Software Interface,'' Morgan Kauffman Publishers.
4. URL link : (CPU Info Centre) http://www.infopad.eecs.berkeley.edu/CIC