8085 Interrupts

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 Interrupts
• Interrupt is a process where an external device
can get the attention of the microprocessor.
– The process starts from the I/O device
– The process is asynchronous.

• Classification of Interrupts
– Interrupts can be classified into two types:
• Maskable Interrupts (Can be delayed or Rejected)
• Non-Maskable Interrupts (Can not be delayed or
Rejected)

• Interrupts can also be classified into:

• Vectored (the address of the service routine is hard-wired)
• Non-vectored (the address of the service routine needs to
be supplied externally by the device)

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 Interrupts
• An interrupt is considered to be an emergency
signal that may be serviced.
– The Microprocessor may respond to it as soon as
possible.

• What happens when MP is interrupted ?

– When the Microprocessor receives an interrupt
signal, it suspends the currently executing
program and jumps to an Interrupt Service Routine
(ISR) to respond to the incoming interrupt.
– Each interrupt will most probably have its own
ISR.

3
 Responding to Interrupts
• Responding to an interrupt may be immediate or
delayed depending on whether the interrupt is
maskable or non-maskable and whether
interrupts are being masked or not.

• There are two ways of redirecting the execution

to the ISR depending on whether the interrupt is
vectored or non-vectored.
– Vectored: The address of the subroutine is already
known to the Microprocessor
– Non Vectored: The device will have to supply the
address of the subroutine to the Microprocessor
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 The 8085 Interrupts
• When a device interrupts, it actually wants the
MP to give a service which is equivalent to
asking the MP to call a subroutine. This
subroutine is called ISR (Interrupt Service
Routine)
• The ‘EI’ instruction is a one byte instruction and is
used to Enable the non-maskable interrupts.
• The ‘DI’ instruction is a one byte instruction and
is used to Disable the non-maskable interrupts.
• The 8085 has a single Non-Maskable interrupt.
– The non-maskable interrupt is not affected by the
value of the Interrupt Enable flip flop.
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 8085 Interrupts

TRAP
RST7.5
RST6.5
RST 5.5 8085
INTR
INTA

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 The 8085 Interrupts

Interrupt name Maskable Vectored

INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes

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 Interrupt Vectors and the Vector Table
• An interrupt vector is a pointer to where the ISR
is stored in memory.
• All interrupts (vectored or otherwise) are mapped
onto a memory area called the Interrupt Vector
Table (IVT).
– The IVT is usually located in memory page 00
(0000H - 00FFH).
– The purpose of the IVT is to hold the vectors that
redirect the microprocessor to the right place when
an interrupt arrives.

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• Example: Let , a device interrupts the
Microprocessor using the RST 7.5 interrupt line.
– Because the RST 7.5 interrupt is vectored,
Microprocessor knows , in which memory location
it has to go using a call instruction to get the ISR
address. RST7.5 is knows as Call 003Ch to
Microprocessor. Microprocessor goes to 003C
location and will get a JMP instruction to the actual
ISR address. The Microprocessor will then, jump
to the ISR location

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The 8085 Non-Vectored Interrupt Process
• The interrupt process should be enabled using the EI
instruction.
• The 8085 checks for an interrupt during the execution of
every instruction.
• If INTR is high, MP completes current instruction, disables
the interrupt and sends INTA (Interrupt acknowledge) signal
to the device that interrupted
• INTA allows the I/O device to send a RST instruction
through data bus.
• Upon receiving the INTA signal, MP saves the memory
location of the next instruction on the stack and the program
is transferred to ‘call’ location (ISR Call) specified by the
RST instruction

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The 8085 Non-Vectored Interrupt Process
• Microprocessor Performs the ISR.
• ISR must include the ‘EI’ instruction to enable the
further interrupt within the program.
• RET instruction at the end of the ISR allows the
MP to retrieve the return address from the stack
and the program is transferred back to where the
program was interrupted.

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The 8085 Non-Vectored Interrupt Process
• The 8085 recognizes 8 RESTART instructions:
RST0 - RST7.
– each of these would send the execution to a
predetermined hard-wired memory location:
Restart Equivalent
Instruction to
RST0 CALL 0000H
RST1 CALL 0008H
RST2 CALL 0010H
RST3 CALL 0018H
RST4 CALL 0020H
RST5 CALL 0028H
RST6 CALL 0030H
RST7 CALL 0038H

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 Restart Sequence
• The restart sequence is made up of three
machine cycles
– In the 1st machine cycle:
• The microprocessor sends the INTA signal.
• While INTA is active the microprocessor reads the data
lines expecting to receive, from the interrupting device,
the opcode for the specific RST instruction.
– In the 2nd and 3rd machine cycles:
• the 16-bit address of the next instruction is saved on the
stack.
• Then the microprocessor jumps to the address
associated with the specified RST instruction.

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 Issues in Implementing INTR Interrupts
• How long must INTR remain high?
– The microprocessor checks the INTR line one clock cycle
before the last T-state of each instruction.
– The INTR must remain active long enough to allow for the
longest instruction.
– The longest instruction for the 8085 is the conditional CALL
instruction which requires 18 T-states.
• Therefore, the INTR must remain active for 17.5 T-
states.
• If f= 3MHZ then T=1/f and so, INTR must remain active
for [ (1/3MHZ) * 17.5 ≈ 5.8 micro seconds].

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 Issues in Implementing INTR Interrupts
• How long can the INTR remain high?
– The INTR line must be deactivated before the EI is
executed. Otherwise, the microprocessor will be
interrupted again.
– Once the microprocessor starts to respond to an
INTR interrupt, INTA becomes active (=0).

Therefore, INTR should be turned off as soon as

the INTA signal is received.

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 Issues in Implementing INTR Interrupts
• Can the microprocessor be interrupted again
before the completion of the ISR?
– As soon as the 1st interrupt arrives, all maskable
interrupts are disabled.
– They will only be enabled after the execution of
the EI instruction.

Therefore, the answer is: “only if we allow it to”.

If the EI instruction is placed early in the ISR, other
interrupt may occur before the ISR is done.

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 Multiple Interrupts & Priorities
• How do we allow multiple devices to interrupt
using the INTR line?
– The microprocessor can only respond to one
signal on INTR at a time.
– Therefore, we must allow the signal from only one
of the devices to reach the microprocessor.
– We must assign some priority to the different
devices and allow their signals to reach the
microprocessor according to the priority.

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 The Priority Encoder
• The solution is to use a circuit called the priority
encoder (74LS148).
– This circuit has 8 inputs and 3 outputs.
– The inputs are assigned increasing priorities
according to the increasing index of the input.
• Input 7 has highest priority and input 0 has the lowest.
– The 3 outputs carry the index of the highest
priority active input.
– Figure 12.4 in the book shows how this circuit can
be used with a Tri-state buffer to implement an
interrupt priority scheme.

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 Multiple Interrupts & Priorities
• Note that the opcodes for the different RST
instructions follow a set pattern.
• Bit D5, D4 and D3 of the opcodes change in a binary
sequence from RST 7 down to RST 0.
• The other bits are always 1.
• This allows the code generated by the 74366 to be used
directly to choose the appropriate RST instruction.

• The one draw back to this scheme is that the

only way to change the priority of the devices
connected to the 74366 is to reconnect the
hardware.

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2
 The 8085 Maskable/Vectored Interrupts
• The 8085 has 4 Masked/Vectored interrupt
inputs.
– RST 5.5, RST 6.5, RST 7.5
• They are all maskable.
• They are automatically vectored according to the
following table:
Interrupt Vector
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

– The vectors for these interrupt fall in between the vectors

for the RST instructions. That’s why they have names like
RST 5.5 (RST 5 and a half).

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 Masking RST 5.5, RST 6.5 and RST 7.5
• These three interrupts are masked at two levels:
– Through the Interrupt Enable flip flop and the EI/DI
instructions.
• The Interrupt Enable flip flop controls the whole
maskable interrupt process.
– Through individual mask flip flops that control the
availability of the individual interrupts.
• These flip flops control the interrupts individually.

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The 8085 Maskable/Vectored Interrupt Process

• The interrupt process should be enabled using the

EI instruction.
• The 8085 checks for an interrupt during the
execution of every instruction.
• If there is an interrupt, and if the interrupt is
enabled using the interrupt mask, the
microprocessor will complete the executing
instruction, and reset the interrupt flip flop.
• The microprocessor then executes a call
instruction that sends the execution to the
appropriate location in the interrupt vector table.

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The 8085 Maskable/Vectored Interrupt Process

• When the microprocessor executes the call

instruction, it saves the address of the next
instruction on the stack.
• The microprocessor jumps to the specific service
routine.
• The service routine must include the instruction EI
to re-enable the interrupt process.
• At the end of the service routine, the RET
instruction returns the execution to where the
program was interrupted.

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 Manipulating the Masks
• The Interrupt Enable flip flop is manipulated
using the EI/DI instructions.

• The individual masks for RST 5.5, RST 6.5 and

RST 7.5 are manipulated using the SIM
instruction.
– This instruction takes the bit pattern in the
Accumulator and applies it to the interrupt mask
enabling and disabling the specific interrupts.

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 SIM and the Interrupt Mask
• Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST 6.5
and bit 2 is the mask for RST 7.5.
• If the mask bit is 0, the interrupt is available.
• If the mask bit is 1, the interrupt is masked.

• Bit 3 (Mask Set Enable - MSE) is an enable for setting the

mask.
• If it is set to 0 the mask is ignored and the old settings remain.
• If it is set to 1, the new setting are applied.
• The SIM instruction is used for multiple purposes and not only
for setting interrupt masks.
– It is also used to control functionality such as Serial Data
Transmission.
– Therefore, bit 3 is necessary to tell the microprocessor whether or
not the interrupt masks should be modified

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 SIM and the Interrupt Mask
• The RST 7.5 interrupt is the only 8085 interrupt that has
memory.
– If a signal on RST7.5 arrives while it is masked, a flip flop will
remember the signal.
– When RST7.5 is unmasked, the microprocessor will be
interrupted even if the device has removed the interrupt
signal.
– This flip flop will be automatically reset when the
microprocessor responds to an RST 7.5 interrupt.

• Bit 4 of the accumulator in the SIM instruction allows

explicitly resetting the RST 7.5 memory even if the
microprocessor did not respond to it.
• Bit 5 is not used by the SIM instruction

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Using the SIM Instruction to Modify the Interrupt Masks

• Example: Set the interrupt masks so that RST5.5

is enabled, RST6.5 is masked, and RST7.5 is
enabled.
– First, determine the contents of the accumulator
- Enable 5.5 bit 0 = 0

M7.5
M6.5
M5.5
SDO

MSE
R7.5
SDE
XXX
- Disable 6.5 bit 1 = 1
- Enable 7.5 bit 2 = 0
- Allow setting the masks bit 3 = 1 0 0 0 0 1 0 1 0
- Don’t reset the flip flop bit 4 = 0
- Bit 5 is not used bit 5 = 0
- Don’t use serial data bit 6 = 0 Contents of accumulator are: 0AH
- Serial data is ignored bit 7 = 0

EI ; Enable interrupts including INTR

MVI A, 0A ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
SIM ; Apply the settings RST masks

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 Triggering Levels
• RST 7.5 is positive edge sensitive.
• When a positive edge appears on the RST7.5 line, a
logic 1 is stored in the flip-flop as a “pending” interrupt.
• Since the value has been stored in the flip flop, the line
does not have to be high when the microprocessor
checks for the interrupt to be recognized.
• The line must go to zero and back to one before a new
interrupt is recognized.

• RST 6.5 and RST 5.5 are level sensitive.

• The interrupting signal must remain present until the
microprocessor checks for interrupts.

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 The RIM Instruction and the Masks
• Bits 0-2 show the current setting of the mask for
each of RST 7.5, RST 6.5 and RST 5.5
• They return the contents of the three mask flip flops.
• They can be used by a program to read the mask
settings in order to modify only the right mask.

• Bit 3 shows whether the maskable interrupt

process is enabled or not.
• It returns the contents of the Interrupt Enable Flip Flop.
• It can be used by a program to determine whether or not
interrupts are enabled.

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 The RIM Instruction and the Masks
• Bits 4-6 show whether or not there are pending
interrupts on RST 7.5, RST 6.5, and RST 5.5
• Bits 4 and 5 return the current value of the RST5.5 and
RST6.5 pins.
• Bit 6 returns the current value of the RST7.5 memory flip
flop.

• Bit 7 is used for Serial Data Input.

• The RIM instruction reads the value of the SID pin on the
microprocessor and returns it in this bit.

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 Pending Interrupts
• Since the 8085 has five interrupt lines, interrupts
may occur during an ISR and remain pending.
– Using the RIM instruction, it is possible to can read
the status of the interrupt lines and find if there are
any pending interrupts.

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 TRAP
• TRAP is the only non-maskable interrupt.
– It does not need to be enabled because it cannot
be disabled.
• It has the highest priority amongst interrupts.
• It is edge and level sensitive.
– It needs to be high and stay high to be recognized.
– Once it is recognized, it won’t be recognized again
until it goes low, then high again.

• TRAP is usually used for power failure and

emergency shutoff.

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 The 8085 Interrupts

Interrupt Masking Triggering

Maskable Vectored Memory
Name Method Method

Level
INTR Yes DI / EI No No
Sensitive

RST 5.5 / DI / EI Level

Yes Yes No
RST 6.5 SIM Sensitive

DI / EI Edge
RST 7.5 Yes Yes Yes
SIM Sensitive

Level &
TRAP No None Yes No Edge
Sensitive

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8259A PROGRAMMABLE INTERRUPT
CONTROLLER
 NEED FOR 8259A

• 8085 Processor has only 5 hardware interrupts.

• Consider an application where a number of I/O devices
connected with CPU desire to transfer data using
interrupt driven data transfer mode. In this process more
number of interrupt pins are required.
• In these multiple interrupt systems the processor will
have to take care of priorities.
 8259A PIC

• Able to handle a number of interrupts at a time.

• Takes care of a number of simultaneously appearing
interrupt requests along with their types and
priorities.
• Compatible with 8-bit as well as 16-bit processors.
 8259A PIC- FEATURES

• Manage 8 interrupts according to the instructions

written into the control registers.
• Vector an interrupt request anywhere in the
memory map. However all the 8 interrupts are
spaced at an interval of four to eight locations.
• Resolve 8 levels of interrupt priorities in variety
of modes.
• Mask each interrupt request individually.
• Read the status of pending interrupts, in-service
interrupts and masked interrupts.
 8259A PIC- FEATURES

• Be set up to accept either the level triggered or

the edge triggered interrupt request.
• Be expanded to 64 priority levels by cascading
additional 8259As.
• Compatible with 8-bit as well as 16-bit
processors.
 8259A PIC- BLOCK DIAGRAM

It includes 8 blocks.
• Control logic
• Read/Write logic
• Data bus buffer
• Three registers (IRR,ISR and IMR)
• Priority resolver
• Cascade Buffer
8259A PIC- PIN DIGRAM
8259A PIC- BLOCK DIAGRAM
 8259A PIC- INTERRUPTS AND CONTROL LOGIC SECTION

This section consists of

• IRR (Interrupt
IRR
Request Register) • 8 interrupt inputs set
corresponding bits of
• ISR (In-Service IRR
Register)
• Priority Resolver • Used to store the
information about the
• IMR (Interrupt Mask interrupt inputs
Register) requesting service.
• Control logic block
 8259A PIC- INTERRUPTS AND CONTROL LOGIC
SECTION

ISR PRIORITY RESOLVER

• Determines the priorities of

• Used to store information interrupts requesting services
(which set corresponding bits
about the interrupts of IRR)
currently being serviced. • It determines the priorities as
dictated by priority mode set by
OCWs.
• The bit corresponding to
* OCWs  Operation highest priority input is set in
Control Word. ISR during input.
• Examines three registers and
determines whether INT
should be sent to MPU.
 8259A PIC- INTERRUPTS AND CONTROL LOGIC
SECTION

IMR
• This register can be programmed by an OCW to
store the bits which mask specific interrupts.
• IMR operates on the IRR.
• An interrupt which is masked by software (By
programming the IMR) will not be recognized
and serviced even if it sets corresponding bits in
the IRR.
 8259A PIC- INTERRUPTS AND CONTROL LOGIC
SECTION

CONTROL LOGIC
• Has two pins:
INT (Interrupt) Output
( Interrupt Acknowledge) Input
• INT Connected to Interrupt pin of MPU.
 When interrupt occurs this pin goes high.
 8259A PIC- BLOCK DIAGRAM

DATA BUS BUFFER

• 8 bit
• Bidirectional
• Tri-state Buffer used to Interface the 8259 to the
system data bus.
• Control words, Status words and vectoring data
are all passed through the data bus buffer.
 8259A PIC- READ/WRITE CONTROL LOGIC
SECTION

• Contains ICW and OCW registers which are

programmed by the CPU to set up the 8259 and to
operate it in various modes.
• Also accepts read command from CPU to permit the
CPU to read status words.
•  Chip Select  Active Low input
 Used to select the Device.
•  Read  Active Low input
 Used by CPU to read the status of
ISR,IRR,IMR or the Interrupt level.
•  Write  Active Low input
 Used to write OCW and ICW onto the 8259.
*ICW Initialization Control Word
8259A PIC- CASCADE BUFFER/ COMPARATOR

• Generates control signals for cascade operation.

• Also generates buffer enable signals.
• 8259 cascaded with other 8259s
 Interrupt handling capacity to 64 levels
 Former is called master and latter is slave.
• 8259 can be set up as master or slave by
pin in non-buffered mode or by software if it is to
be operated in the buffered mode of operation.
8259A PIC- CASCADE BUFFER/ COMPARATOR

CAS 0-2
• For master 8259 these pins are outputs and for slaves these are
inputs.
• When 8259 is a master the CALL op-code is generated by master in
response to the first Interrupt acknowledge.
• The vectoring address must be released by slave 8259.

• The master puts out the identification code to select one of the slave
from 8 slaves through these pins.
• The slave accepts these three signals as inputs and compare the
code put out by the master with the codes assigned to them during
initialization.
• The slave thus selected puts out the address of ISR during second
and third interrupt acknowledge pulses from the CPU.
8259A PIC- CASCADE BUFFER/ COMPARATOR

Slave Program/ Enable Buffer:

• Used to specify whether 8259 is to act as a
master or a slave
High Master
Low  Slave
• In Non-Buffered Mode, this pin is used to specify
whether 8259 is to act as a master or a slave.
• In Buffered mode this pin is used as an output to
enable the data bus buffer of the system.
 8259A PIC- INTERRUPT OPERATION

• To implement interrupt, the interrupt Enable FF must be

enabled by writing EI instruction.
• 8259A should be initialized by writing control words in
the control register.
• 8259 requires two types of control words:
ICW Used to set up proper conditions
and specify RST vector address.
OCW Used to perform functions such as
masking interrupts, setting up status
read operations etc.
• After 8259A is initialized, the following sequence of
events occurs when one or more interrupt request lines
go high.
 8259A PIC- INTERRUPT OPERATION

• IRR stores the Interrupt requests.

• Priority Resolver Checks three registers:
IRR for interrupt requests.
IMR for Masking bits.
ISR for the interrupt request being serviced.
It resolves the priority and sets the INT high
when appropriate.
• MPU acknowledges the interrupt by sending
interrupt acknowledge.
 8259A PIC- INTERRUPT OPERATION

4. After is received, the appropriate priority

bit in the ISR is set to indicate which level is
being served and the corresponding bit in the
IRR is reset to that request is accepted. Then
op-code for CALL instruction is placed on the
Data Bus.
5. When MPU decodes the CALL instruction, it
places two more signals on the data
bus.
 8259A PIC- INTERRUPT OPERATION

6. When 8259 receives second , it places

lower order byte of CALL address on the data bus.
Third  High order byte.
The CALL address is the vector memory location for
the interrupt. This address is placed in control
register during initialization.
 8259A PIC- INTERRUPT OPERATION

7. During third pulse, the ISR bit is reset

either automatically (AEOI) or by a command
word that must be issued at the end of the
service routine (EOI). This option is determined
by the ICW.
8. The program sequence is transferred to the
memory location specified by the CALL
instruction.
AEOI  Automatic End of Interrupt Mode
EOI  End of Interrupt Mode
 8259A PIC- COMMAND WORDS

• Two types: ICW, OCW

ICW:
• Before start functioning, 8259 must be initialized
by writing two to four command words into their
respective command word registers.
• A0=0,D4=1: The control word is ICW1. ICW1
contains the control bits for edge/level triggered
mode, single/cascade mode, call address
interval and whether ICW4 is required or not etc.
• A0=1: ICW2Store details interrupt vector
addresses.
 8259A PIC- ICW1

The following initialization procedure Carried out internally

when ICW1 is loaded.
• The edge sense circuit is reset i.e. by default 8259A
interrupts are edge sensitive.
• IMR is cleared.
• IR7 input is assigned lowest priority.
• Slave mode address is set to 7.
• Special mask mode is cleared and status read is set to
IRR.
• If IC4=0, all functions of ICW4 are set to Zero.
Master/slave bit in ICW4 bit is used in buffered mode
only.
INITIALIZATION SEQUENCE OF 8259A

ICW1 & ICW2 are

Compulsory command
Words in the initialization
sequence.

ICW3 & ICW4 are

Optional.

ICW3 is read only when

More than one 8259 used in
the system ( SNGL bit in
ICW1 is 0).
 ADI=1 for 8086 based system

For 8086 Don’t Care

p
For 8085 system they are filled by A15-A11 of the interrupt vector address and
Least significant 3 bits are same as the respective bits of the vector address.
For 8086 system they are filled by most significant 5 bits of interrupt type and
the least significant 3 bits are 0, pointing to IR0.
If BUF=0,M/S is to be neglected.
 8259A- OPERATING MODES

FULLY NESTED MODE:

• General purpose mode.
• All IRs are arranged from highest to lowest.
• IR0 Highest IR7Lowest
AUTOMATIC ROTATION MODE:
• In this mode, a device after being serviced, receives the
lowest priority.

SPECIFIC ROTATION MODE:

• Similar to automatic rotation mode, except that the user
can select any IR for the lowest priority, thus fixing all
other priorities.
8259-INTERRUPT PROCESS IN FULLY NESTED MODE
 8259A- OPERATING MODES

END OF INTERRUPT (EOI):

• After the completion of an interrupt service, the
corresponding ISR bits needs to be reset to update the
information in the ISR. This is called EOI command.
It can be issued in three formats:
NON SPECIFIC EOI COMMAND:
• When this command is sent to 8259A, it resets the
highest priority ISR bit.
SPECIFIC EOI COMMAND:
• This command specifies which ISR bit is to reset.
 8259A- OPERATING MODES

AUTOMATIC EOI:
• In this mode, no command is necessary.
• During the third interrupt acknowledge cycle, the
ISR bit is reset.
• DRAWBACK: The ISR does not have information
about which ISR is being serviced. Thus, any IR can
interrupt the service routine, irrespective of its
priority, if the interrupt enable FF is set.
 8259A- OPERATING MODES

SPECIAL FULLY NESTED MODE:

• Used in case of larger system where cascading is used, and the has
to be programmed in the master using ICW4
• In this mode, when an interrupt request from a certain slave is in
service, this slave can further send requests to the master, if the
requesting device connected to the slave has higher priority than the
one being currently served.
• In this mode, the master interrupts the CPU only when the
interrupting device has the highest priority or the same priority than
the one currently being served.
• In normal mode, other requests than the one being served are
masked.

BUFFERED MODE

CASCADE MODE
 ADDITIONAL FEATURES OF THE 8259A
INTERRUPT TRIGGERING:
• 8259A can accept an interrupt request with either the
edge triggered or level triggered mode.
• Mode is determined by initialization instructions.
INTERRUPT STATUS:
• The status of the three interrupt registers (IRR, ISR and
IMR) can be read, and this status information can be
used to make the interrupt process versatile.

POLL METHOD:
• 8259A can be set up to function in polled environment.
• MPU polls the 8259A rather than each peripheral.