Lecture15 DiodeModelsSmalSignalZener PDF

Lecture 15
P-N Junction Diodes: Part 5

Large signal (complete model) and small signal
(limited use) models of a Diode
Reading:
Jaeger 3.4-3.14, 13.4, Notes
Georgia Tech ECE 3040 - Dr. Alan Doolittle

Diode Applications: 1/2 Wave Rectifier
id
+
vs RLoad VLoad
vd
-
vs-vLoad=vd
+
Id=-Io
vLoad = -Io RLoad
t
-
Diode Applications: Peak Detector
id
+
vs CLoad VLoad
vd
-
vs-vLoad=vd
+
-
Diode Applications: 1/2 Wave Rectifier with an RC Load
id
+
vs CLoad RLoad VLoad
-
-
Diode Applications: LED or a Laser Diode
I V1=IR Light Emission

R=1000 ohms
under forward Bias
VA
V=9V
Diode made from a direct

Quantum well made from bandgap semiconductor.
smaller bandgap material Note: These devices may not be a
simple p-n type diode, but behave
Electron Current electrically identical to a p-n
P-type junction diode.
Al0.5Ga0.5As
FN Majority Carriers that are injected to the oppposite
GaAs side of the diode under forward bias become minority
-qVA Light carriers and recombine. In a direct bandgap material,
this recombination can result in the creation of
FP photons. In a real device, special areas are used to trap
electrons and holes to increase the rate at which they
N-type recombine. These areas are called quantum wells.
Hole Current Al0.5Ga0.5As

Models used for analysis of Diode Circuits
Mathematical Model (previously developed)

Graphical Analysis
Ideal diode Model
•Treat the diode as an ideal switch
Constant Voltage Drop Model
•Treat as an ideal switch plus a battery
Large signal Model (model used by SPICE transient
analysis)
•multi-components
•generally applicable
Small Signal Model (model used by SPICE AC analysis)
•easier math
•valid only for limited conditions-ie small signals

Diode Circuits: Graphical Solution
To solve the problem graphically,
we need to find the IV curve for the
resistor:
Intersection of the
two curves gives
the DC operational
voltage and
VA=0V -> I=9V/1000 ohms currents
ID Load Line
I V1=IR
R=1000 ohms
VD
VA
I=0 -> VA=9V
V=9V

Diode Circuits: Other Models
Besides the direct mathematical solution and the graphical

solution, we can use 2 other models to approximate circuit
solutions:
1.) Ideal Diode Model:
a) The voltage across the diode is zero for forward bias.
b) The slope of the current voltage curve is infinite for
forward bias.
c) The current across the diode is zero for reverse bias.
I
Circuit Symbol

Diode Circuits: Other Models
2.) Constant Voltage Drop (CVD) Model:

a) The voltage across the diode is a non-zero value for
forward bias. Normally this is taken as 0.6 or 0.7 volts.
b) The slope of the current voltage curve is infinite for
forward bias.
c) The current across the diode is zero for reverse bias.
+
Von
0.6V V
-

Concept of the Small- Signal Model
•Superposition principle allows us to separate DC and AC
analysis of circuits containing active devices (like diodes,
transistors, amplifiers etc...).
•We assume the AC signals are small enough so that the circuit
behaves linearly and can be analyzed by replacing “non-linear”
components by “Linear Elements” such as resistors etc...
•DC analysis is first performed to determine the bias point which
will determine some of the parameters used in the “AC-small
signal analysis”.
•Consider a two terminal device (like a pn diode) at a given DC
operating point (or “Q- point”).
Let: VD = DC voltage applied to the diode
ID = DC current produced by the diode
Total current or voltage = DC part + AC part:
vD = VD + vd iD = ID + id
Note: (1) all caps = DC; (2) all lower case = AC; (3) lower case
symbol with upper case subscript = total voltage or current
Small Signal Analysis of Diodes
Diode Biased in
For small AC voltage Forward Bias: Tiny
“swings”, vd, about a fixed
DC voltage, VD the diode IV
small signal
curve can be approximated as resistance, rd.
a resistor (I.e. linear current-
voltage relationship). The
fixed DC operating point, iD=ID+id
(VD-ID), is called the bias ID 1 3
point or the quiescent or Q-
2
point. 2
2 vD=VD+vd
V1D

Diode Biased in
small signal
a resistor (I.e. linear current- 3
3
2
point. 2
2 vD=VD+vd
V1D

Diode Biased in
“small signal”
a resistor (I.e. linear current- 3
3
2
point. 2
2 vD=VD+vd
V1D

Small vs Large Signal Concept For Diodes
Consider the small signal case where

v D (t) = 0.6 + 0.025sin(wt) then,
iD=ID+id i D (t) = 1e - 12(e v D (t)/0.0259 - 1)
1 1
vD=VD+vd ⇒ i d (t) ≈ v d (t) but i D (t) ≠ v D (t)
rd rd
0.615 0.0184
Both Voltage and

Current are 0.61 0.0164
(approximately) a
sine wave. 0.605 0.0144
Voltage
Current
Some distortion is 0.6 0.0124
observed because in
this example we have 0.595 0.0104
exceeded the
mathematical limits 0.59 0.0084
valid for small signal
analysis (0.025 is not Voltage 0.6V+0.025sin(wt) I=f(V)
0.585 0.0064
<< kT/q). In most 0 10 20 30 40 50 60 70
cases, this is tolerable. Time

Small vs Large Signal Concept For Diodes
3 3 Consider the Large Signal case where

iD=ID+id v D (t) = 0.6sin(wt) then,
2
i D (t) = 1e - 12(e v D (t)/0.0259 - 1)
1
⇒ i D (t) ≠ v D (t)
vD=VD+vd rd
0.8 0.6sin(wt) I=f(V) 0.01
Voltage is a sine 0.008

0.6
wave but the 0.006
current is 0.4
0.004
“distorted” 0.2
0.002
Voltage
Current
0 0
0 10 20 30 40 50 60 70
-0.002
-0.2
-0.004
-0.4
-0.006
-0.6
-0.008
-0.8 -0.01
Time
The transition from valid small signal limits to Large Signal
conditions is a matter of what is acceptable for your requirements
0.6015
i D (t) = 1e - 12(e v D (t)/0.0259 - 1) 0.0122 0.01
v D (t) = 0.6 + 0.001sin(wt) 0.009
FFT
0.012
0.601
0.008
0.0118 0.007
Magnitude of Signal
0.6005
0.006
0.0116
“No”
Voltage
Current
0.005
0.6
0.0114 0.004
0.5995
0.0112
0.003 Distortion
0.002
0.599
0.011 0.001
Voltage 0.6V+0.025sin(wt) I=f(V) 0

0.5985 0.0108 0 10 20 30 40 50 60 70
0 10 20 30 40 50 60 70
Frequency
Time
0.12
v D (t) = 0.6 + 0.01sin(wt)

0.615 0.0184
0.61 0.0164 0.1
FFT
Magnitude of Signal
0.08
0.605 0.0144
Slight
Voltage
Current
0.06
0.6 0.0124
0.595 0.0104
0.04
Distortion
0.02
0.59 0.0084

0.585 0.0064 0 10 20 30 40 50 60 70
0 10 20 30 40 50 60 70
Frequency
Time
0.75
v D (t) = 0.6 + 0.1sin(wt) 0.6 5
4.5
FFT
0.7
0.4
4
0.65 3.5
Magnitude of Signal
0.2
3
Major
0.6
Voltage
Current
2.5
0
0.55
distortion
2
-0.2 1.5
0.5
1
-0.4
0.45 0.5

0.4 -0.6 0 10 20 30 40 50 60 70
0 10 20 30 40 50 60 70
Frequency
Time
g d ≡ small signal conduc tan ce of the diode
1
rd ≡ small signal resis tan ce of the diode, rd =
gd
∂i D
gd = Bias Po int or "Quiscient " or "Q − po int"
∂v D
  vD VT 
∂  I S  e − 1
 
=  Q − po int
∂v D
I S vD VT I S VD VT vd VT
= e Q − po int = e e
VT VT
vd
Assu min g small signals, v d 〈〈VT , e VT
→ 1 and
VD VD
I e VT
ISe VT
− IS + IS
= S =
VT VT
ID + IS
gd =
VT
 V A VT  kT
I D = I o  e − 1 where VT =
  q
iD = I D + g d vd
ID + IS
gd = in General
VT
VA
ID kT
VA >> 0 → I D ≈ I o e VT
where VT =
gd ≈ in Forward Bias q
VT
− IS + IS VA
gd ≈ ≈ 0 in Re verse Bias VA << 0 → e VT
→0
VT

Diode Biased in
Reverse Bias: Huge
“small signal”
resistance, rd=1/gd
VD
iD=ID+id
vD=VD+vd

Small Signal Analysis of Diodes:
Application: Diode as an AC variable attenuator
rd
R
C large
enough to be
vs an AC short
vout
IDC

Conversion to AC equivalent circuit
rd
R
C large enough R rd
to be an AC
short
vs
vout
vout
ID
C
Steps to Analyze a Diode Circuit

1.) Determine DC operating point and
calculate small signal parameters, rd and
others to come in later lectures)
2.) Convert to the AC only model.
•DC Voltage sources are shorts
•DC Current sources are open circuits
•Large capacitors are short circuits
•Large inductors are open circuits
Application: Diode as an AC variable attenuator
rd
R
vout
rd
vout = vin
rd + R
1 1
vout = vin = vin or at room temperature
1+
R (I DC + I S )R
1+
rd VT
1
vout ≈ vin
1 + 40(I DC + I S )R
Actual voltage drop
across the diode Completing the Large signal model of a diode
including resistive
losses from quasi-
neutral regions.
vD iD=IS(exp(v’D/(ηVT)) - 1) where η accounts
for previously neglected recombination-
v’D generation in the depletion region
iD=IS(exp[(vD- iDRSeries )/(ηVT)] - 1) accounts

for the series resistance drop in the quasi-
RSeries neutral regions.
Depletion-
CJunction region
ppo n no
p-region --+ -+ +- - n-region
+
-+--+ +- +-
+- +-
-+-+ +- +-
+ +
npo
CDiffusion pno
x=0 x=0
dQ
C= '
= Change in ch arg e resulting from a change in voltage
Georgia Tech
dv D ECE 3040 - Dr. Alan Doolittle
Completing the Large signal model of a diode
For an abrupt diode (uniform doping on both sides of the junction):
K sε o A
C junction =
W
but...
2K S ε o (N A + N D )
W = x p + xn = (Vbi − V A )
q NAND
qK S ε o N A N D 1
C junction =A
2 ( N A + N D ) (Vbi − V A )
Thus,
qK S ε o N A N D 1 C Jo
C Jo = C junction =A and CJ =
2 ( N A + N D ) (Vbi )
VA =0
VA
1−
Vbi
Junction capacitance is due to majority carrier charges displaced by the depletion

width (I.e. similar to a parallel plate capacitor).
More generally for a profile with a constant doping on the heavily doped side of
the junction and variable doping profile on the a low doped side that is described
by: N(x)=bxm for all x>0 Kε A
C junction = s o
W
but...
1
 (m + 2 )K S ε o  (m+ 2 )
W = x p + xn =  (Vbi − V A )
 qb 
AK S ε o
C junction = 1
 (m + 2 )K S ε o  (m+ 2 )
 (Vbi − V A )
 qb 
Thus,
AK S ε o C Jo
C Jo = C junction VA =0 = 1
and CJ = 1
 (m + 2 )K S ε o  (m+ 2 )
 V A  (m+ 2 )
 (Vbi ) 1 − 
 qb   Vbi 
Junction capacitance is due to majority carrier charges displaced by the depletion
width (I.e. similar to a parallel plate capacitor).
dQD
C Diffusion =
dv D'
dQD dt
=
dt dv D'
 vD VT  − x Lp  vD VT  − x Ln
' '
∞ ∞
QD = qA∫ p no  e 
− 1 e dx + qA∫ n po  e − 1e dx
0 0
   
 vD VT 
'

= e [ ]
− 1 p no L p + n po Ln qA
 
1  vD VT 
'
dQD
dt
=
VT 
e [ ]
 p no L p + n po Ln qA dt
dv D'

  vD' V 

 IS e T
− 1 + 1 
dQD
dt
=
1  
VT  IS
[ 
 ]
p no L p + n po Ln qA
dv D'
dt
 
 
 
Diffusion capacitance due to “excess injected” minority carrier charge at the depletion
region edges. Since this charge results from minority carriers, this capacitance is
negligible at zero or reverse biases.
1  iD + I S 
dQD
dt
= 
VT  I S 
[
 pno L p + n po Ln qA
dvD'
dt
]
[
dQD  iD + I S  pno L p + n po Ln qA dvD'
=
]

dt  VT  IS dt
iD=ID+id dQD
= gd
[ ]
pno L p + n po Ln qA dvD'
dt IS dt
iD~ID
C Diffusion =
dQD dt
= gd
[ 
]
pno L p + n po Ln qA  dvD' dt 

' 
dt dvD' IS  dt dv D 
  Unit
[ ]
pno L p + n po Ln qA  cm cm q cm 
−3 2
analysis
C Diffusion = g d = gd 
q  = g d [sec]
IS  
 sec 
C Diffusion = g dτ t where τ t =
[p no ]
L p + n po Ln qA
is the transit time or how quickly a carrier can respond
IS
to a change in voltage (physically the carriers have to move across the junction, requiring a finite time to do so)
∂i
or in SPICE , C Diffusion = D τ t
∂vD
Diffusion capacitance due to “excess injected” minority carrier charge at the depletion
region edges.
Summary of the Large signal model of a diode (SPICE Model)
( v D - i D R Series )
ηVT
i D = I S (e - 1)
RSeries
AK S ε o
 (m + 2)K S ε o  (m+ 2 )
 (V )
bi 
 qb 
CJunction
C Jo
and CJ = 1
⇒ f (V A )
 VA  (m+ 2 )
1 − 
 Vbi 
C Diffusion = g d τ t 1.) Mathematical model

2.) SPICE Model (this page)
3.) Ideal Diode Model
4.) Constant Voltage Drop (CVD) Model
5.) Graphical circuit model
Addition of Capacitance Components
Significant
minority
carrier
concentration
at the
depletion
region edges
No significant minority carrier in large-
concentration at the depletion forward bias
region edges in reverse or small- => CD>>CJ
forward bias => CD<<CJ

Summary of the Small signal model of a diode
ID + IS
iD = I D + g d vd where gd =
VT
rd = 1/g d ⇒ f (I D )
RSeries
AK S ε o
 (m + 2)K S ε o  (m+ 2 )
 (V )
bi 
CJunction  qb 
C Jo
and CJ = 1
⇒ f (V A )
 VA  (m+ 2 )
1 − 
 Vbi 
C Diffusion = g d τ t ⇒ f (I D )
Things we have added to account for “Non-ideal” behavior
•Series resistance to account for finite resistance of the quasi-neutral
regions and metal contact resistance's.
•Diode “ideality factor”, η, to account for thermal recombination-
generation in the depletion region.
•Junction capacitance due to majority carrier charges displaced by
the depletion width (I.e. similar to a parallel plate capacitor).
•Diffusion capacitance due to “excess injected” minority carrier
charge at the depletion region edges. Since this charge results from
minority carriers, this capacitance is negligible at zero or reverse
biases.
Things we still need to add to account for “Non-ideal” behavior

• Reverse “Breakdown” characteristics
•“Breakdown” is a deceptive term because no damage typically
occurs to the device. Often diodes are designed to operate in the
breakdown mode.
Breakdown Mechanisms
Avalanche Breakdown:
Excess current flows due to
electron-hole pair
multiplication due to impact
ionization. This current
rapidly increases with
increasing reverse bias.

Breakdown Mechanisms
Zener Breakdown:
Excess current flows due to bonding electrons “tunneling” into empty
conduction band states. The “tunneling barrier” must be sufficiently thin.
This current rapidly increases with increasing reverse bias.

“Zener” Diodes
Zener diodes may actually operate based on either avalanche or

zener breakdown mechanisms.
Rule of thumb: |VBR|>6EG/q is typically Avalanche Breakdown
Slightly different symbol
I
VBR almost
R constant can act
V>VBR as a high
voltage (~1V -
100 V) DC
reference

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Lecture 15

P-N Junction Diodes: Part 5

Georgia Tech ECE 3040 - Dr. Alan Doolittle

I V1=IR Light Emission

Diode made from a direct

Hole Current Al0.5Ga0.5As

Mathematical Model (previously developed)

Georgia Tech ECE 3040 - Dr. Alan Doolittle

Georgia Tech ECE 3040 - Dr. Alan Doolittle

Besides the direct mathematical solution and the graphical

Georgia Tech ECE 3040 - Dr. Alan Doolittle

2.) Constant Voltage Drop (CVD) Model:

Georgia Tech ECE 3040 - Dr. Alan Doolittle

Georgia Tech ECE 3040 - Dr. Alan Doolittle

Georgia Tech ECE 3040 - Dr. Alan Doolittle

Georgia Tech ECE 3040 - Dr. Alan Doolittle

Consider the small signal case where

Both Voltage and

cases, this is tolerable. Time

Georgia Tech ECE 3040 - Dr. Alan Doolittle

3 3 Consider the Large Signal case where

Voltage is a sine 0.008

v D (t) = 0.6 + 0.001sin(wt) 0.009

Voltage 0.6V+0.025sin(wt) I=f(V) 0

v D (t) = 0.6 + 0.01sin(wt)

0.61 0.0164 0.1

Voltage 0.6V+0.025sin(wt) I=f(V) 0

Voltage 0.6V+0.025sin(wt) I=f(V) 0

Georgia Tech ECE 3040 - Dr. Alan Doolittle

Georgia Tech ECE 3040 - Dr. Alan Doolittle

Georgia Tech ECE 3040 - Dr. Alan Doolittle

Steps to Analyze a Diode Circuit

iD=IS(exp[(vD- iDRSeries )/(ηVT)] - 1) accounts

For an abrupt diode (uniform doping on both sides of the junction):

Junction capacitance is due to majority carrier charges displaced by the depletion

C Diffusion = g d τ t 1.) Mathematical model

Georgia Tech ECE 3040 - Dr. Alan Doolittle

Things we still need to add to account for “Non-ideal” behavior

Georgia Tech ECE 3040 - Dr. Alan Doolittle

Georgia Tech ECE 3040 - Dr. Alan Doolittle

Zener diodes may actually operate based on either avalanche or

Slightly different symbol

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