MSP 430 PDF

MSP430 Design Workshop
Outline
 MSP430 Family
 MSP430 CPU
 Memory
 MSP430 Peripherals
 Ultra Low-Power (ULP)
 Community / Resources
 Launchpads
 Lab Exercise
Chapter 1: Introduction
TI’s Embedded
Microcontrollers (MCU)Processor Portfolio
Application (MPU)
MSP430 C2000 Tiva C Hercules Sitara DSP Keystone
16-bit 32-bit 32-bit 32-bit 32-bit 16/32-bit 32-bit
Ultra Low Real-time All-around Safety Linux All-around Massive
Power & Cost MCU Android DSP Performance
• Real-time ARM ARM • C66 + C66
MSP430 DSP
C28x MCU ARM • A15 + C66
ULP RISC Cortex-M3 Cortex-A8 C5000
• A8 + C64
MCU • ARM M3+C28 Cortex-M4F Cortex-R4 Cortex-A9 C6000
• ARM9 + C674
• Low Pwr Mode • Motor Control • 32-bit Float • Lock step • $5 Linux CPU • C5000 Low • Fix or Float
 250nA (RTC)
 770nA (LCD)
• Digital Power • Nested Vector Dual-core R4
IntCtrl (NVIC) • ECC Memory • 3D Graphics
Power DSP • Up to 12 cores
4 A15 + 8 C66x
• Analog I/F • Precision • PRU-ICSS • 32-bit fix/float
Timers/PWM • Ethernet industrial subsys C6000 DSP • DSP MMAC’s:
• USB and RF (MAC+PHY) • SIL3 Certified 352,000
3rd Party Linux, Android, C5x: DSP/BIOS Linux
TI-RTOS TI-RTOS (k) TI-RTOS
(only) TI-RTOS Kernel C6x: TI-RTOS (k) TI-RTOS (k)
Flash: 512K 512K 1MB 256K to 3M L1: 32K x 2 L1: 32K x 2 L1: 32K x 2
FRAM: 128K Flash Flash Flash L2: 256K L2: 256K L2: 1M + 4M
25 MHz 300 MHz 120 MHz 220 MHz 1.35 GHz 800 MHz 1.4 GHz
$0.25 to $1.85 to $1.00 to $5.00 to $5.00 to $2.00 to $30.00 to

$9.00 $20.00 $8.00 $30.00 $25.00 $25.00 $225.00
F5xx Key Features
Ultra-Low Power
MSP430F5xx Block Diagram
 160 μA/MIPS
Unified Clock 16-bit
 2.5 μA standby mode System RISC CPU
DMA
Flash
Controller
 Integrated LDO, BOR, WDT+, RTC Enhanced
Power Management Embedded
Module Emulation System
 12 MHz @ 1.8V Control/
Supply Supervisors JTAG Watchdog RAM
 Wake up from standby in <5 μs Supply Monitors Spy Bi-Wire
Interface
Brownout
Increased Performance Computation Timing and Control Signal Chain Communication I/O & Display
 Up to 25 MHz Hardware General Purpose Universal Serial General

Timers Capture/ Communication Purpose I/O,
32x32 Comparators
Compare PWM Interfaces Pull-Up/Down,
 1.8V ISP Flash erase and write Multiplier Outputs (SPI, UART, I2C) High Drive
 Fail-safe, flexible clocking system CRC

Basic Timer
+ ADC
USB 2.0
(Full Speed)
Segmented
LCD, Static,
RTC Engine + PHY Muxed
 User-defined Bootstrap Loader
 Up to 1MB linear memory addressing AEC DAC RF Transceivers
Innovative Features
Operational
 Multi-channel DMA supports data Amplifiers
movement in standby mode

 Industry leading code density
 More design options including USB,
RF, encryption, LCD interface
Looking at the 'FR59xx...
MSP430FR58xx/59xx
MSP430FR58/59xx Memory
Ultra Low Power • FRAM (32/48 / 64 KB)
16-bit MCU • RAM (1 or 2 KB)
• MPU
16MHz
Debug
• Real Time JTAG
• Embedded emulation
• Bootstrap Loader
Accelerators Timers
• 32x32 Multiplier • Watch Dog Timer (WDT_A)
• DMA (3 Ch) • Real Time Clock (RTC_B)
• CRC16 • Two 16-bit w/3 CCR (TA0, TA1)
• AES256 Encryption (FR59xx) • Two 16-bit w/2 CCR (TA2, TA3)
• One 16-bit w/7 CCR (TB0)
Serial Interfaces
• 3 Serial Interfaces (eUSCI) Connectivity
• 2 UART + IrDA or SPI • Up to 40 GPIO (Interrupt/Wake)
• 2 I2C or SPI • Cap touch IO
Analog Power & Clocking

• 12-bit SAR ADC (up to 16 ch) • Brownout Reset
o Differential inputs • Supply Voltage Supervisor (SVS)
o Window comparators • Low Power Vreg (1.5V LDO)
• Comparator (Comp_E) • External Oscillators: LFXT, HFXT
• Vref (REF_A) • Internal Oscillators: VLO, DCO (±2%)
MSP430 CPU
 Efficient, ultra-low power CPU
 C-compiler friendly
 RISC architecture
 51 instructions
 7 addressing modes
 Constant generator
 Single-cycle register operations

 Bit, byte and word processing
 1MB unified memory map
 No paging
 Extended addressing modes
 Page-free 20-bit reach
 Improved code density
 Faster execution
 100% code compatible with
earlier versions
MSP430 details
CPU Registers Program counter
The CPU incorporates 16 registers The 20-bit Program Counter (PC,

(R0 through R15). Registers R0,
also called R0) points to the next
R1, R2, and R3 have dedicated
functions.
instruction to be executed.
Registers R4 through R15 are Each instruction uses an even

working registers for general use. number of bytes (2, 4, 6, or 8
bytes), and the PC is incremented
accordingly.
Outline
 TI Products
 TI's Embedded Processors
 MSP430 Family
 MSP430 CPU
 Memory
 Memory Map
 FRAM
 Launchpads
 Lab Exercise
Unified Memory Map
In-System Prog (ISP) ‘F5529 Memory Map
 Write using: User
program, JTAG, BSL
Bytes MSP430 Memory
 Unified memory map
 Byte, word, long-word (program or data)
 Erase one (or all)  Absolutely no paging
segments at a time
Flash 128K
Main Flash
 512 byte segments
 Start address moves
according to RAM 0xFFFF RAM
0xFF80 INT Vectors 80  Always a contig. block
Info Memory  If enabled, USB port
 Use for your own uses first 2K
calibration data, etc.  RAM segments can be
 4 segments (A-D) RAM 8K powered down
0x2400
 128 byte segments
0x01C0 USB RAM 2K
Boot Loader (BSL) Info Memory 512 Device Descriptors (TLV)
 Program Flash/RAM Boot Loader 2K  Factory calibration
with serial (slau319) data, periph support,…
 Password protected Peripherals 4K  Found in peripherals
 512 byte segments 0x0000 (at 0x1A00)
0x243FF
‘F5529
‘F5529 vs ‘FR5969 Mem Maps
Main 81K ‘FR5969  Most MSP430 devices have
Flash similar Memory Maps
0xFFFF Main FRAM 17K
0xFF80 INT Vectors INT Vectors 80  ‘F5529
 128K of Flash non-volatile
memory
Main Main 47K  10K of SRAM (2K can be
Flash FRAM dedicated to USB usage)
0x4400
 ‘FR5969
RAM Vacant 8K
 64K of non-volatile FRAM
0x2400
USB RAM RAM 2K memory
0x1C00
0x1A00 TLV TLV  2K of SRAM
Info A Info A 128  Though you can use FRAM
Info B Info B 128 like SRAM which gives you
Info C Info C 128 up to 64K more read/write
0x1800 Info D Info D 128 storage)
Boot Loader Boot Loader 2K
Peripherals Peripherals 4K
0x0000 Bytes Let's look closer at FRAM...
‘F5529 ‘FR6989
0x243FF
Memory Maps
Main Main 81K ‘FR5969
Flash FRAM
0xFFFF Main FRAM 17K ‘FR4133
0xFF80 INT Vectors INT Vectors INT Vectors 80 INT Vectors 80
Main 15.5K
Main Main Main FRAM
47K
Flash FRAM FRAM
0x4400 Vacant
RAM Vacant Vacant 8K
0x2400
0x1C00 USB RAM RAM RAM 2K RAM 2K
0x1A00 TLV TLV TLV TLV
Info A Info A Info A 128
Info B Info B Info B 128
Info A 512
Info C Info C Info C 128
0x1800 Info D Info D Info D 128
Vacant
Boot Loader Boot Loader Boot Loader 2K Boot Loader 1K
Peripherals Backup RAM 20B
Peripherals Peripherals 4K
0x0000 Tiny RAM (26B) Let's
Byteslook closer at FRAM...4K
Peripherals
Outline
 TI Products
 MSP430 Family
 MSP430 CPU
 Memory
 Memory Map
 FRAM
 Launchpads
 Lab Exercise
FRAM: The Future of MCU Memory
 Non-volatile, Reliable Storage

 Over 100 Trillion write/read
cycles
 Write Guarantee in case of
power loss
 Fast write times like SRAM
 ~50ns per byte or word
 1,000x faster than
Flash/EEPROM
 Low Power
 Only 1.5v to write & erase
 >10-14v for Flash/EEPROM
 Universal Memory
Photo: Ramtron Corporation
Memory Comparison
FRAM MCU Delivers Max Benefits
FRAM SRAM EEPROM Flash
Non-volatile
Retains data without power
Yes No Yes Yes
Write speeds 10 ms <10 ms 2 secs 1 sec
Average active Power

( µA/MHz )
110 <60 50mA+ 230
Write endurance 1015 Unlimited 100,000 10,000
Dynamic
Bit-wise programmable
Yes Yes No No
Unified memory
Flexible code/data Yes No No No
partitioning
Outline
 TI Products
 MSP430 Family
 MSP430 CPU
 Memory
 UltraLow-Power (ULP)
 Launchpads
 Lab Exercise
MSP430 GPIO (Chapter 3)
GPIO
CH 3
GPIO (Chapter 3)
 Independently programmable
 Any combination of input, output,
interrupt and peripheral is possible
 Each I/O has an individually
programmable pull-up/pull-down
resistor
 Many devices can lock pin values
‘F5529 block diagram during low-power modes
 Some devices support touch-sense
capability built into the pins
MSP430 Timers (Chapters 3, 5, 6, 8)
Watchdog GPIO
CH 3 & 5 CH 3
Timers (Chapters 3, 5, 6, 8)
 Timer_A: 16-bit timer/counter
 Multiple capture/compare registers
 Generates PWM and other complex
waveforms & interrupts
 Directly trigger GPIO, DMA, ADC, etc.
 Timer_B: Same as A; improved PWM
 Timer_D: Same as B; with hi-res timing
‘F5529 block diagram  RTC: Real-time clock with calendar &
CH 6 CH 8 alarms – runs in LPM3 low power mode
Timer A & B RTC  Watch: Watchdog or interval functions
MSP430 Clocking & Power Mgmt (Ch 4)
Clocks Power
CH 4 CH 4
Clocking (Chapter 4)
 Three Internal Clocks provide for
CPU, fast and slow peripherals
 Many clock sources (internal and
external) provide cheap and accurate
clks with quick wake-up
 Clock defaults and failsafe’s improve
system robustness
Power Mgmt
 Brown-out reset on all devices
 Many provide LDO’s and power
‘F5529 block diagram supervisors
 On-chip power gating drives ULP
MSP430 Analog
Clocks Power Watchdog GPIO
CH 4 CH 4 CH 3 & 5 CH 3
Analog
 Families ADC converter options:
10 or 12-bit SAR (ADC10, ADC12)

16 or 24-bit Sigma-Delta (SD16, SD24)

Slope converters

 DAC converters: 12-bit DAC12
 Comparators
 Voltage REFerences
 Features in common:
 Analog mux supporting multiple input chan’s
 DMA can read/write samples without CPU
‘F5529 block diagram
 Precise timing when using timer to trigger
CH 6
 Generate interrupts to CPU
Timers
 Low power dissipation
Sampling of MSP430 Analog
MSP430i2040
 4 Sigma-Delta AFE
1% accuracy for precise measurements
with a 2000:1 dynamic range ΣΔ
convertors
 Low Cost SoC – Targets low-end meters
with minimal communications (memory)
requirements
 Internal DCO – eliminates need for
external crystal
 Small packages minimize pin count and
cost
 Temperature - -40C to 105C
MSP430F67791
 7 Independent Sigma-Delta ADC’s
with Differential Inputs and Variable Gain
 7 Channel 10-bit SAR ADC (200-ksps)
Six Channels Plus Supply and
Temperature Sensor Measurement
 LCD Driver With Contrast Control for up
to 320 segments
 Six Enhanced Communications Ports
 512 KB of Flash
 32 KB of SRAM
 MPY and CRC Accelerators
MSP430 Communication
Clocks Power Watchdog GPIO USB
CH 4 CH 4 CH 3 & 5 CH 3 CH 10
Communications
 USB (Chapter 10)
 USB 2.0 at Full speed (12Mbps)
 Includes PHY, LDO, PLL, PUR
 Serial ports
 USI: SPI, I2C
 USCI: SPI, I2C, IrDA, UART
 eUSCI: enhanced USCI
 Radio Frequency
 CC430 and RF430 devices include
Sub-1GHz or NFC radios CH 6
 WiFi, BLE, ANT, BluetoothTimers
& Sub1GHz
communications via TI SimpleLink
MSP430 Accelerators
CH 4 CH 4 Accelerators
CH 3 & 5 CH 3 CH 10
 DMA (“hardware memcpy”)

 Copy from memory to memory
 Faster copies than with CPU
 Supports periph’s (ADC, UART)
 MPY32 (8/16/32 Multiplier)
 MAC, fractional, saturation support
 CRC: Single-cycle CRC generation
 AES: 128, 192, 256 bit encryption
 LCD: Automatic with up-to 160-bit

MSP430 Peripherals (and In-Depth Chapters)
CH 4 CH 4 CH 3 & 5 CH 3 CH 10

CH 6 CH 8
Timer A & B RTC
Outline
 TI Products
 MSP430 Family
 MSP430 CPU
 Memory
 Launchpads
 Lab Exercise
Why does Ultra Low Power Matter?
2.9 Billion
$50 Billion
Thrown Away
Spent Every Year
Each Year in
On Batteries
the U.S.
50 Billion
Additional
Connected
Devices Expected
by 2020
Distributed
Sensor Networks
Mean More
Batteries in
Remote Locations
Why does Ultra Low Power Matter?
How does this impact you?
2.9 Billion
$50 Billion
Thrown Away
Spent Every Year
Each Year in
On Batteries
the U.S.
50 Billion
Additional
Connected
Devices Expected
by 2020
Distributed
Sensor Networks
Mean More
Batteries in
Remote Locations
Low Power Modes (LPM's)

Ultra-low Power Activity Profile
Active Active
170 A
Standby (LPM3)
0.4 A
32768 MSP430 Leave On the Slow Clock

ACLK  Low power clock and peripherals
low-power peripherals interrupt CPU only for processing
On-Demand CPU Clock
MCLK
DCO  DCO starts immediately
CPU and peripherals
 CPU processes data and quickly
returns to Low Power Mode
Low-Power Modes
Self Wakeup
CPU (MCLK)
Retention
SMCLK
Operating
ACLK
RAM
BOR
Mode Interrupt Sources
Active     
LPM0     
Timers, ADC, DMA, WDT, I/0,
LPM1      External Interrupt, COMP,
Serial, RTC, other
LPM2    
LPM3    
LPM3.5   External Interrupt, RTC
LPM4   External Interrupt
LPM4.5  External Interrupt
LPM is great, but waking up...

Outline
 TI Products
 MSP430 Family
 MSP430 CPU
 Memory
 References
 Launchpads
 Lab Exercise
TTO Workshops: processors.wiki.ti.com
This Workshop
Engineer-2-Engineer Forums
http://e2e.ti.com
Outline
 TI Products
 MSP430 Family
 MSP430 CPU
 Memory
 References
 Launchpads
 Lab Exercise
Further Reading…
MSP430 Microcontroller Basics by John H. Davies,
(ISBN-10 0750682760) Link
Microcontroller Programming and Interfacing:

Texas Instruments MSP430 (Synthesis Lectures on
Digital Circuits and Systems)
by Steven Barrett and Daniel Pack ,
(ISBN-10 0750682760) Link
Outline
 TI Products
 MSP430 Family
 MSP430 CPU
 Memory
 Launchpads
 Lab Exercise
MSP-EXP430F5529LP Launchpad
MSP-EXP430F5529LP Overview
Outline
 TI Products
 MSP430 Family
 MSP430 CPU
 Memory
 Launchpads
 Lab Exercise
Lab 1 – Run Out-of-Box Demo
 Verify tool installation

 Review Launchpad kit
contents
 Connect hardware
Agenda …
http://www.ti.com/training

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MSP430 Design Workshop

$0.25 to $1.85 to $1.00 to $5.00 to $5.00 to $2.00 to $30.00 to

 Up to 25 MHz Hardware General Purpose Universal Serial General

 Fail-safe, flexible clocking system CRC

movement in standby mode

Analog Power & Clocking

 Single-cycle register operations

CPU Registers Program counter

The CPU incorporates 16 registers The 20-bit Program Counter (PC,

Registers R4 through R15 are Each instruction uses an even

 Non-volatile, Reliable Storage

Write speeds 10 ms <10 ms 2 secs 1 sec

Average active Power

Write endurance 1015 Unlimited 100,000 10,000

 DMA (“hardware memcpy”)

‘F5529 block diagram

‘F5529 block diagram

Low Power Modes (LPM's)

32768 MSP430 Leave On the Slow Clock

LPM is great, but waking up...

Microcontroller Programming and Interfacing:

 Verify tool installation

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