SONY: ICX038BLA | 1/2 inch CCD Image Sensor for EIA B/W Camera Description ICXO38BLA is an interline transfer CCD solid-state imager sultable for EIA 1/2 inch BW video cameras. High sensitiveness is achieved through the adoption of HAD (Hole-Accumulation Diode) sensors, This chip features a field integration read out system, an electronic shutter with variable charge-storage time and 20 pin Cer-DIP package. Features 20 pin DIP (Cer-DIP) ‘* High image, high sensitivity and low dark current (+648 compare with ICXO38ALA) © Consecutive various speed shutter 1160s. (Typ.), 1/100s. to 1/10000s, ‘+ Low smear ‘© High antiblooming ‘¢ Horizontal register 8V drive ¢ Reset gate 5V drive Device Structure ‘© Optical size 1/2 inch format Number of effective pixels 768 (H) x494(V) Approx. 380k pixels Number of total pixels —_-811(H) X50B (V) Approx. 410k pixels * Interline transfer CCD image sensor © Chip size 7.95mm (H) x6,45mm (V) © Unit cell size 8.4 um (H) X9.8 um (V) Optical black Horizontal (H) direction Front 3 pixels Rear 40 pixels Vertical (V) direction Front 12 pixels Rear 2 pixels ‘* Number of dummy bits Horizontal 22 Vertical 1 {even field only) © Substrate material Silicon Sony ragarves the righ 0 change products and speciizaions without prior alice, This information does nat convey ary license by hi, Application cts shown, any. are lypeal exemple esvatog RG ‘poration of he devices. Sony cannol assume responsiny or any prblams asing avi of to use cl hase arcots ‘any implicalon or othorwisa uncer any patents or other ties —< Ontieal bieck position (Top View) Eeteszc6y—Ps,SONY oxog88uA Block Diagram Pin Configuration (Top View) re Phat ig! to iG fe a Holt “8 al Bh C ~O wanes ° 23 ‘ccs LET 22¢ se Pin Description No. | Symbol Description No. | Symbol Description 1 Voe Vertical register transfer clock 114 | Vea Output amplifier gate bias 2 | Vos Vertical register transfer clock 12 | NC 3 | Vo2 Vertical register transfer clock 13 | Vss Output amplifier source 4 | SUB Substrate (Overflow drain) 14 | GND GND 5 | GND GND 15 | GND GND 6 | Ver Vertical register transfer clock 16 | RO Reset drain bias. 7 IM Protective transistor bias 17 | RG Reset gate clock 8 | GND GND 18 | LHe: Horizontal register final stage transfer clock 9 | Voo Output amplifier drain supply 19 | Hos Horizontal register transter clock 10 | Vour Signal output 20 | Hoe Horizontal register transfer clock Absolute Maximum Ratings Item Ratings Unit | Remarks Substrate voltage SUB-GND 0.3 to +55 v Supply voltage Voo, Vao, Vout, Vss — GND 0.310 +18 v Voo, Vao, Vout, Vss — SUB -55 to +10 v Vo1, V2, Vos, V4 — GND. -15 to +20 Vv Cleckinnstvetege Tyg, vba Voa,Voe=SUB | to x10 Vv Voltage difference between vertical clock input pins to+i5 v * (Max,) Voltage difference between horizontal clock input pins to+17 v Ho1,Ho2-Voe 17 to +17, v LH), RG. Vac ~ GND aos |v LH@ 1, AG, Veo - SUB ~sSiovi0 | Vv Vu - SUB 65 to +0.3 Vv Beside GND, SUB-Vi_ 0.3 to +30. v Storage temperature -30 to +80 c Operating temperature =10 to +60 c * +27V (Max.) when clock width < 10 us, duty factor <0.1%. -2-SONY exO3BBLA Bias Conditions i item [symbol | Min. | Typ. | Max. | Unit | Remarks | ‘Output ampitier drain voltage Vo | 1455 | 150 | 1545] V i Reset drain voltage ‘Vao 1455 | 150 | 15.45 | V_ | Vao=Voo j Output ampitier gate votage Ves__| 175 | 20 [225 | Vv | Output amplifier source Ves | Ssound through + 5% | Substrate voltage adjustment range sus. 9.0 15 | v [*2 | Fluctuation range after substrate voage adjustment | A Veue | _-3 3 | % - Reset gate clock voltage adjustment range vans |_10 40 |v [#2 +6 ututon ang afer eet at cock votage alee eee eee Protective transistor bias We 3 DC Characteristics item ‘Symbol | Min. | Typ. | Max. | Unit | Remarks ‘Output amplifier drain current | loo 5 mA Input current Toa 1 | wa [ra Input current ina 10 [wa [#5 *2- Substrate voltage (Vsus) - reset gate clock voitage (Vat) setting value display. es Setting values of substrate voltage and reset gate clock voltage are displayed at the back of the device through a code address. Adjust substrate voltage (Vsus) and reset gate clock voltage (Vaai) to the displayed voltage. Fluctuation range after adjustment is + 3%, Veue code address—t digit display q. Vact code address-1 digit display sup address code ' ack address code Code addresses and actual numerical values correspond to each other as follows. Vaat address code [1] 2/3 [4[5]6]7 Numerical value |1.0[1.5|2.0|2.5]3.0[3.5]40) Veue address JE} f/G)hjJ/ K/L] miniPlalrisjtjiulviwixly}z code Numerical value {90/95} 10.0|10.5)11.0|11,5/12.0] 12.5) 13.0/13.5]14.0|14.5|15.0|15.5]16.0|16.5|17.0117.5|18.0/18.5| “SL" > Vrat=3.0V are Vsue=12.0V *3_ Vi setting is the Vu. voltage of the vertical transfer clock waveform.