Professional Documents
Culture Documents
VGG
28
40
24
38
20
Pout (dBm)
Gain (dB)
36
16
34
12
8
32
4
30
0
8 8.25 8.5 8.75 9 9.25 9.5 9.75 10 10.25 10.5 10.75 11
8 8.25 8.5 8.75 9 9.25 9.5 9.75 10 10.25 10.5 10.75 11
Frequency (GHz)
Frequency (GHz)
45 0
40
-5
35
30
Return Loss(dB)
-10
PAE (%)
25
20
-15
15
10
-20
5
0
-25
8 8.25 8.5 8.75 9 9.25 9.5 9.75 10 10.25 10.5 10.75 11
8 8.25 8.5 8.75 9 9.25 9.5 9.75 10 10.25 10.5 10.75 11
Frequency (GHz)
Frequency (GHz)
Figure 3. Power Added Efficiency vs. Frequency Figure 4. Input Return Loss vs. Frequency
APPLICATION INFORMATION
Assembly:
5000 pF
0.1 µF
Chip dimensions: 4.6 mm x 4.6 mm, .003”
thickness.
VGG VDD VDD Die attach: Use AuSn (80/20) 1-2 mil.
preform solder. Limit time @ 300 °C to less
5000 pF
5000 pF
0.1 µF
0.1 µF
100 pF
than 5 minutes.
Wirebonding: Bond @ 160 °C using
standard ball or thermal compression wedge
bond techniques. For DC pad connections,
RF IN RF OUT use either ball or wedge bonds. For best RF
50 Ω 50 Ω performance, use wedge bonds of shortest
length, although ball bonds are also
acceptable.
100 pF
VGG Biasing:
1. User must apply negative bias to VGG before
5000 pF
0.1 µF
5000 pF
0.1 µF
VDD VDD
applying positive bias to VDD to prevent
5000 pF
0.1 µF
damage to amplifier.
www.DatasheetCatalog.com