RGM COLLEGE OF ENGINEERING & TECHNOLOGY, NANDYAL-518 501.

AUTONOMOUS
RGMCET/ECE/HR/F-03
ACADEMIC YEAR: 2010-11 TEACHING PLAN RGMCET/ECE/TP/F-01

NAME OF THE FACULTY: Mr.N.Nagaraja Kumar

SUBJECT: DIGITAL SYSTEM DESIGN
Branch & Year: M.Tech, I-Sem DSCE Total Hours: 47 Hours
Estimated
S.No Unit Topics to be covered
Periods

DESIGN OF DIGITAL SYSTEMS: ASM charts, Hardware description language

1 I 6
and control sequence method, Reduction of state tables, state assignments

SEQUENTIAL CIRCUIT DESIGN: design of Iterative circuits, design of sequential

2 II 6
circuits using ROMs and PLAs, sequential circuit design using CPLD, FPGAs

FAULT MODELING: Fault classes and models, stuck at faults, bridging faults, transition
and intermittent faults.
3 III 8
TEST GENERATION: Fault diagnosis of Combinational circuits by conventional
methods – Path Sensitization technique, Boolean difference method, Kohavi algorithm

TEST PATTERN GENERATION: D–algorithm, PODEM, Random testing, transition count

4 IV 5
testing, Signature analysis and testing for bridging faults

FAULT DIAGNOSIS IN SEQUENTIAL CIRCUITS: State identification and fault

5 V 6
detection experiment. Machine identification, Design of fault detection experiment

PROGRAMMING LOGIC ARRAYS: Design using PLA’s, PLA minimization and PLA
6 VI 5
folding

7 VII PLA TESTING: Fault models, Test generation and Testable PLA design 5

ASYNCHRONOUS SEQUE NTI A L MA CHI NE : Fundamental m od e m od el , f lo w

8 VIII 6
tabl e , state red uc ti o n , mi nim al closed covers, races, cycles and hazards

FACULTY HOD PRINCIPAL

 RGM COLLEGE OF ENGINEERING & TECHNOLOGY, NANDYAL-518 501.
AUTONOMOUS
RGMCET/ECE/HR/F-03
ACADEMIC YEAR: 2010-11 TEACHING PLAN RGMCET/ECE/TP/F-01

NAME OF THE FACULTY: Mr.M.Chennakesavulu

SUBJECT: EMBEDDED SYSTEM CONCEPTS
Branch & Year: M.Tech, I-Sem DSCE Total Hours: 49 Hours
Estimated
S.No Unit Topics to be covered
Periods
INTRODUCTION: Embedded system overview, embedded hardware units, embedded
1 I software in a system, embedded system on chip (SOC), design process, classification of 7
embedded systems.
EMBEDDED COMPUTING PLATFORM: CPU Bus, memory devices, component
2 II interfacing, networks for embedded systems, communication interfacings: RS232/UART, 7
RS422/RS485, IEEE 488 bus.

SURVEY OF SOFTWARE ARCHITECTURE: Round robin, round robin with interrupts,

3 III 6
function queue scheduling architecture, selecting an architecture saving memory space.

EMBEDDED SOFTWARE DEVELOPMENT TOOLS: Host and target machines, linkers,

4 IV locations for embedded software, getting embedded software into target system, 6
debugging technique.

RTOS CONCEPTS: Architecture of the kernel, interrupt service routines, semaphores,

5 V 6
message queues, pipes.

6 VI INSTRUCTION SETS: Introduction, preliminaries, ARM processor, SHARC processor. 5

SYSTEM DESIGN TECHNIQUES: Design methodologies, requirement analysis,

7 VII 5
specifications, system analysis and architecture design.

DESIGN EXAMPLES: Telephone PBX, ink jet printer, water tank monitoring system,
8 VIII 7
GPRS, Personal Digital Assistants, Set Top boxes.

FACULTY HOD PRINCIPAL

 RGM COLLEGE OF ENGINEERING & TECHNOLOGY, NANDYAL-518 501.
AUTONOMOUS
RGMCET/ECE/HR/F-03
ACADEMIC YEAR: 2010-11 TEACHING PLAN RGMCET/ECE/TP/F-01

NAME OF THE FACULTY: Mr.C.Venkataiah

SUBJECT: ADVANCED COMPUTER ARCHITECTURE
Branch & Year: M.Tech, I-Sem DSCE Total Hours: 49 Hours
Estimated
S.No Unit Topics to be covered
Periods

FUNDAMENTALS OF COMPUTER DESIGN: Technology trends, cost- measuring

1 I 6
and reporting performance quantitative principles of computer design.

INSTRUCTION SET PRINCIPLES AND EXAMPLES: classifying instruction set,

memory addressing, type and size of operands, addressing modes for signal
2 II 7
processing, operations in the instruction set- instructions for control flow- encoding
an instruction set.-the role of compiler.
INSTRUCTION LEVEL PARALLELISM (ILP): overcoming data hazards, reducing
3 III branch costs, high performance instruction delivery, hardware based speculation, 7
limitation of ILP.

ILP SOFTWARE APPROACH: Compiler Techniques, Static Branch Protection, VLIW

4 IV 6
Approach, H.W support for more ILP at compile time- H.W verses S.W solutions.

MEMORY HIERARCHY DESIGN: cache performance, reducing cache misses

5 V 6
penalty and miss rate, virtual memory, protection and examples of VM

MULTIPROCESSORS AND THREAD LEVEL PARALLELISM: symmetric shared

6 VI 6
memory architectures, distributed shared memory, Synchronization, multi threading.

STORAGE SYSTEMS: Types, Buses, RAID, errors and failures, bench marking a storage
7 VII 6
device, designing a I/O system

INTER CONNECTION NETWORKS AND CLUSTERS: Interconnection network media,

8 VIII 5
practical issues in interconnecting networks, examples, clusters, designing a cluster.

FACULTY HOD PRINCIPAL

 RGM COLLEGE OF ENGINEERING & TECHNOLOGY, NANDYAL-518 501.
AUTONOMOUS
RGMCET/ECE/HR/F-03
ACADEMIC YEAR: 2010-11 TEACHING PLAN RGMCET/ECE/TP/F-01

NAME OF THE FACULTY: Mr.S.Govindarajulu

SUBJECT: ADVANCED DATA COMMUNICATIONS
Branch & Year: M.Tech, I-Sem DSCE Total Hours: 52 Hours
Estimated
S.No Unit Topics to be covered
Periods
DIGITAL MODULATION: Introduction, Information Capacity Bits, Bit Rate, Baud, and
1 I M-ARY Coding, ASK, FSK, PSK, QAM, BPSK, QPSK, 8PSK, 16PSK, 8QAM, 16QAM, DPSK, 7
Methods, Band Width Efficiency, Carrier Recovery, Clock Recovery
BASIC CONCEPTS OF DATA COMMUNICATIONS, INTERFACES AND MODEMS:
2 II Data Communication, Components, Networks, Distributed Processing, Network Criteria- 6
Applications, Protocols and Standards, Standards Organizations, Regulatory Agencies
Line Configuration- Point-to-point- Multipoint, Topology, Mesh, Star, Tree, Bus, Ring,
Hybrid Topologies, Transmission Modes, Simplex, Half duplex- Full Duplex, Categories of
Networks- LAN, MAN, WAN and Internetworking, Digital Data Transmission- Parallel and
3 III 6
Serial, DTE-DCE Interface-Data Terminal Equipment, Data Circuit-Terminating
Equipment, Standards EIA 232 Interface, Other Interface Standards, Modems-
Transmission Rates.
ERROR DETECTION AND CORRECTION: Types of Errors- Single- Bit Error, CRC
4 IV (Cyclic Redundancy Check), Performance, Checksum, Error Correction- Single-Bit Error 6
Correction, Hamming Code.
DATA LINK CONTROL: Stop and Wait, Sliding Window Protocols.
DATA LINK PROTOCOLS: Asynchronous Protocols, Synchronous Protocols, Character
5 V 6
Oriented Protocol- Binary Synchronous Communication (BSC) - BSC Frames- Data
Transparency, Bit Oriented Protocols, HDLC, Link Access Protocols.
SWITCHING: Circuit Switching- Space Division Switches- Time Division Switches, TDM
Bus, Space and Time Division Switching Combinations, Public Switched Telephone
Network, Packet Switching- Datagram Approach- Virtual Circuit Approach, Circuit
6 VI 7
Switched Connection Versus Virtual Circuit Connection, Message Switching.
MULTIPLEXING: Time Division Multiplexing (TDM), Synchronous Time Division
Multiplexing, Digital Hierarchy, Statistical Time Division Multiplexing.
MULTIPLE ACCESS: Random Access, Aloha- Carrier Sense Multiple Access (CSMA)-
Carrier Sense Multiple Access with Collision Detection (CSMA)- Carrier Sense Multiple
7 VII 7
Access with Collision Avoidance (CSMA/CA), Controlled Access- Reservation- Polling-
Token Passing, Channelization.
Frequency- Division Multiple Access (FDMA), Time - Division Multiple Access (TDMA), -
8 VIII 7
Code - Division Multiple Access (CDMA).

FACULTY HOD PRINCIPAL

 RGM COLLEGE OF ENGINEERING & TECHNOLOGY, NANDYAL-518 501.
AUTONOMOUS
RGMCET/ECE/HR/F-03
ACADEMIC YEAR: 2010-11 TEACHING PLAN RGMCET/ECE/TP/F-01

NAME OF THE FACULTY: Mr.M.Ramana Reddy

SUBJECT: DIGITAL DESIGN THROUGH VERILOG
Branch & Year: M.Tech, I-Sem DSCE Total Hours: 54 Hours
Estimated
S.No Unit Topics to be covered
Periods
INTRODUCTION TO VERILOG: Verilog as HDL, Levels of Design Description,
Concurrency, Simulation and Synthesis, Functional Verification, System Tasks,
Programming Language Interface (PLI), Module, Simulation and Synthesis Tools, Test
1 I Benches. 7
LANGUAGE CONSTRUCTS AND CONVENTIONS: Introduction, Keywords, Identifiers,
White Space Characters, Comments, Numbers, Strings, Logic Values, Strengths, Data
Types, Scalars and Vectors, Parameters, Memory, Operators, System Tasks, Exercises
GATE LEVEL MODELING: Introduction, AND Gate Primitive, Module Structure, Other
Gate Primitives, Illustrative Examples, Tri-State Gates, Array of Instances of Primitives,
2 II 8
Additional Examples, Design of Flip-flops with Gate Primitives, Delays, Strengths and
Contention Resolution, Net Types, Design of Basic Circuits, Exercises.
BEHAVIORAL MODELING: Introduction, Operations and Assignments, Functional
Bifurcation, Initial Construct, Always Construct, Examples, Assignments with Delays, Wait
construct, Multiple Always Blocks, Designs at Behavioral Level, Blocking and Non blocking
3 III 8
Assignments, The case statement, Simulation Flow. iƒ and iƒ-else constructs, assign-
deassign construct, repeat construct, for loop, the disable construct, while loop, forever
loop, parallel blocks, force-release construct, Event
MODELING AT DATA FLOW LEVEL: Introduction, Continuous Assignment Structures,
Delays and Continuous Assignments, Assignment to Vectors, Operators.
SWITCH LEVEL MODELING.
4 IV 7
Introduction, Basic Transistor Switches, CMOS Switch, Bi-directional Gates, Time Delays
with Switch Primitives, Instantiations with Strengths and Delays, Strength Contention
with Trireg Nets, Exercises
SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES: Introduction,
Parameters, Path Delays, Module Parameters, System Tasks and Functions, File-Based
Tasks and Functions, Compiler Directives, Hierarchical Access, General Observations,
5 V 8
Exercises,
FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES: Introduction, Function,
Tasks, User- Defined Primitives (UDP), FSM Design (Moore and Mealy Machines)
DIGITAL DESIGN WITH SM CHARTS : State Machine Charts, Derivation of SM
6 VI Charts, Realization of SM Charts, Implementation of the Dice Game, Alternative 5
realizations for SM Charts using Microprogramming, Linked State Machines
DESIGNING WITH PROGRAMMABLE GATE ARRAYS AND COMPLEX
PROGRAMMABLE LOGIC DEVICES: Xilinx 3000 Series FPGAs, Designing with FPGAs,
7 VII 6
Using a One-Hot State Assignment, Altera Complex Programmable Logic Devices
(CPLDs), Altera FLEX 10K Series CPLDs
VERILOG MODELS: Static RAM Memory, A simplified 486 Bus Model, Interfacing
8 VIII 5
Memory to a Microprocessor Bus, UART Design, Design of Microcontroller CPU

FACULTY HOD PRINCIPAL

 RGM COLLEGE OF ENGINEERING & TECHNOLOGY, NANDYAL-518 501.
AUTONOMOUS
RGMCET/ECE/HR/F-03
ACADEMIC YEAR: 2010-11 TEACHING PLAN RGMCET/ECE/TP/F-01

NAME OF THE FACULTY: Dr.D.Satyanarayana

SUBJECT: DSP PROCESSORS AND ARCHITECTURES
Branch & Year: M.Tech, I-Sem DSCE Total Hours: 51 Hours
Estimated
S.No Unit Topics to be covered
Periods
INTORODUCTION TO DIGITAL SIGNAL PROCESING: Introduction, A Digital signal-
processing system, The sampling process, Discrete time sequences. Discrete Fourier
1 I Transform (DFT) and Fast Fourier Transform (FFT), Linear time-invariant systems, Digital 6
filters, Decimation and interpolation, Analysis and Design tool for DSP Systems MATLAB,
DSP using MATLAB
COMPUTATIONAL ACCURACY IN DSP IMPLEMENTATIONS: Number formats for
signals and coefficients in DSP systems, Dynamic Range and Precision, Sources of error
2 II 7
in DSP implementations, A/D Conversion errors, DSP Computational errors, D/A
Conversion Errors, Compensating filter.
ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES: Basic Architectural
features, DSP Computational Building Blocks, Bus Architecture and Memory, Data
3 III 8
Addressing Capabilities, Address Generation Unit, Programmability and Program
Execution, Speed Issues, Features for External interfacing.
EXECUTION CONTROL AND PIPELINING: Hardware looping, Interrupts, Stacks,
4 IV Relative Branch support, Pipelining and Performance, Pipeline Depth, Interlocking, 5
Branching effects, Interrupt effects, Pipeline Programming models
PROGRAMMABLE DIGITAL SIGNAL PROCESSORS: Commercial Digital signal-
processing Devices, Data Addressing modes of TMS320C54XX DSPs, Data Addressing
5 V modes of TMS320C54XX Processors, Memory space of TMS320C54XX Processors, 8
Program Control, TMS320C54XX instructions and Programming, On-Chip Peripherals,
Interrupts of TMS320C54XX processors, Pipeline Operation of TMS320C54XX Processors
IMPLEMENTATIONS OF BASIC DSP ALGORITHMS: The Q-notation, FIR Filters, IIR
6 VI Filters, Interpolation Filters, Decimation Filters, PID Controller, Adaptive Filters, 2-D 5
Signal Processing
IMPLEMENTATION OF FFT ALGORITHMS: An FFT Algorithm for DFT Computation, A
7 VII Butterfly Computation, Overflow and scaling, Bit-Reversed index generation, An 8-Point 6
FFT implementation on the TMS320C54XX, Computation of the signal spectrum
INTERFACING MEMORY AND I/O PERIPHERALS TO PROGRAMMABLE DSP
DEVICES: Memory space organization, External bus interfacing signals, Memory
8 VIII interface, Parallel I/O interface, Programmed I/O, Interrupts and I/O, Direct memory 6
access(DMA). A Multichannel buffered serial port (McBSP), McBSP Programming, a
CODEC interface circuit, CODEC programming, A CODEC-DSP interface example.

FACULTY HOD PRINCIPAL