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Tap cell, Decap cell and

end cap cells
Placing the Well Tap
Cells These library cells
connect the power and
ground connections to
the substrate and
n-wells, respectively. ...

max transition violations

When a signal takes too
long transiting from one
logic level to another, a
transition violation is
reported. The violation is
a functi...

MCMM: Multi-Corner
Multi-Mode
What's MCMM MCMM
stands for: Multi-Corner
Multi-Mode (static timing
analysis used in the
design of digital ICs)
What's a Mode A...

Physical design sanity

checks
Sanity Checks in
Physical Design Flow
Learn more
check_library
check_timing
• Litho based Routing
report_constraint
 report_timing report_qor • MMMC
check_design check_l...
• MUX
What is temperature • Mantra VLSI
Inversion? • Max trans
High-Vt cells respond to
• NDR
the temperature
inversion effect more • Nand based design
effectively compared to • PCB Package Die
Std-Vt and Low-Vt cells. Chip
Not only that...
• PCB-Package-Die
IR Drop Chip
1. Power The power • PVT
spent in Complementary • Power Gating
metal oxide
semiconductor (CMOS) • Power analysis
can be classified as • Power trends
dynamic power
• QRC & Cap table
consumption and
leakag... • Recovery and
Removel Checks
Library Exchange Format • Report global timing
(LEF)
• Resistor color coding
Library Exchange Format
(LEF) is a specification • Routing
for representing the • SDC
physical layout of an
integrate circuit in an • SPEF
ASCII format. It includ... • Semiconductor
Lithography
Physical Design • Switch
Interview Question
Filler cells are added • TLU+
___. a. Before • Terminology in VLSI
Placement of std cells b.
• Transistor
After Placement of Std
Cells c. Before Floor • Transmission gate
planning d. Before ... • Unconstrainted points
• VI-characteristics
Clock Uncertainty
You can model the • VLSI CELLS
expected uncertainty • VLSI design flow
(skew) for a prelayout
design with setup or hold • WLM
and rise or fall • Wafer
uncertainty values.
• Wire bonding
PrimeTime s...
• atomic model
Physical Design Routing • cadence help
Process : VLSI chip command
metal routing
• clock gating
It involves generating
metal wires to connect • clock skew
the pins of same signal • crosstalk noise and
while obeying crosstalk delay
manufacturing design
rules. Before routing is • device-fabrication
perfor... • different-vt-cells
• doping-p-n-junction
• electrostatic-
Blog Archive discharge
2018 (1) • fanout
• fix setup-hold
2017 (1)
• half-adder
2016 (22)
• hold violation
2015 (11)
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2014 (124) • low power
November (3) • max cap
October (7) • min pulse width
violation
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August (30)
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July (23)
• photolithography
June (55) • physical-design-
Antennas and Wave interview
Propagation • physical-design-
All VLSI ppt questions-placement
• placement -
Verilog Codes
manufacturing grid
Hot Carrier Effect • power switch
(HCE)
• prime time flow
Why NAND Based
• redhawk inputs static-
Design is better
dynamic IR
than NOR Based
Des... • report_constraints

what is setup and hold • reset

violations • sanity checks analysis
coverage
Latchup – Cause,
Effect and • semiconductors
Prevention • series-parallel
Jitter on PLL Clocks capacitance
or clock jitter • setup hold violation
Delay in vlsi • static timing reports

Linux Commands • tap - decap-end_cap

cells
VLSI interview
• temperature-inversion
Questions
• tie-cells
Physical Design
Interview Question
 NETWORK • time borrowing-
ANALYSIS AND stealing
SYNTHESIS
• timing models etm-
QUESTION1
qtm-ilm
NETWORK • verilog codes
ANALYSIS AND
SYNTHESIS
QUESTION2
NETWORK
ANALYSIS AND
SYNTHESIS
QUESTION3
NETWORK
ANALYSIS AND
SYNTHESIS
QUESTION4
Tap cell, Decap cell
and end cap cells
set_input_delay ;
set_output_delay
set_timing_derate:
Derating
Clock Reconvergence
Pessimism
Removal : CRPR
Antenna Effects
What are different VT
cells ? How they
are differe...
What is temperature
Inversion?
NMOS PMOS
fanout of a standard
cell in vlsi physical
design
Synchronous vs
Asynchronous
resets
Transmission gate
and other logic
Posted by Mantra VLSI at 23:26 using Tx gate
Basic gates using
NAND and NOR
gate
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Crosstalk Modelling
and Analysis
Interconnect
Technology File (.itf
file)
MCMM: Multi-Corner
Multi-Mode
DeCap: Decoupling
Capacitors
Different File Formats
(file extensions)
max transition
violations
Capacitor and Cap
Violations
NON Default Rule:
NDR Rules
difference between clk
buffer and normal
buffer
Electrostatic
discharge
C4B controlled
collapse chip
connection
verilog code for
interview
 Physical design
questions :
Placement
High-Vt and Low-Vt
cells
Low Power
Techniques
clock gating and latch
based clock gating
Tie Cells & Spare
cells

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