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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO.

4, APRIL 2014 943

Power Efficient Class AB Op-Amps With High and operates as a push–pull amplifier and provides dynamic class-AB
Symmetrical Slew Rate operation with large positive and negative output currents. This does
not increase power dissipation or supply requirements but operates
only for dynamic changes with frequencies f > 1/(2π Rlarge Cbat ).
Jesus Aguado-Ruiz, Antonio Lopez-Martin, Javier Lopez-Lemus,
and Jaime Ramirez-Angulo In this brief, two-stage op-amps with mostly symmetrical slew
rate are presented. They achieve class AB operation also for static
input signals and have been fabricated in a prototype test chip. The
Abstract— Various class AB two-stage op-amps with high and approxi- proposed topologies are described in Section II. Sections III and IV
mately symmetrical slew rate and very simple architecture are introduced deal with simulation and experimental results, respectively. Finally,
in this brief. A current replicating branch with scaled-down transistors in
combination with adaptive loads is used to implement a push–pull output some conclusions are drawn. An Appendix is included describing in
stage with maximum output current several times higher than the bias detail the ac performance of the proposed approach.
current. Postlayout simulation and measurement results are presented
and verify a 400%–500% slew rate and 80%–100% GB enhancement II. C LASS AB T WO -S TAGE O P -A MPS P ROPOSED
with only 5% additional quiescent power dissipation and 20% silicon
area increase. A. Op-Amp With Current Replication Branch
Index Terms— Class AB operation, CMOS analog integrated circuits, As a first step to achieve class AB operation, the output transistor
operational amplifiers, symmetrical slew rate. MoN can be transformed into an active amplifying device by simply
adding a (scaled down) current replicating branch formed by M2R
and MoNR as shown in Fig. 1(c) (square). This transfers current
I. I NTRODUCTION
variations Ia in M1 -M2 to the output transistor MoN and increases
Very efficient schemes have been reported to achieve high sym- the maximum positive output current by 2I B (achieved when MoN
metrical slew rate in single-stage op-amps [1]–[3]. A drawback turns off).
of single-stage op-amps based on this technique is that only rel- The maximum negative current is still limited to a value 2I B
atively low open-loop gain A ol is possible since the inclusion of (when MoP turns off). The current replicating branch does not require
output cascoding transistors to increase the output resistance Rout additional compensation since the only node with gain in the current
(and thus A ol ) would seriously limit the maximum output current replicating branch is from the gate to the drain of MoN , and at high
and the slew rate enhancement factor. The conventional class-A frequencies Miller compensation (with Cc and Rc ) causes MoP to
two-stage Miller-compensated op-amp [Fig. 1(a)] is characterized by behave as low-impedance diode-connected load. This reduces the gain
a highly asymmetrical slew rate with large positive slew rate and (and Miller effect) between the gate of MoN (node Vx ) and the op-
much lower negative slew rate given by S R− = 2I B /C L , where I B amp’s output terminal to approximately a unity value and prevents
is the bias current. This low negative-slew rate is due to the fact Miller multiplication by a large factor on node Vx (which is a low-
that the output nMOS transistor (MoN ) acts as a dc current source impedance node) at high frequencies. The current replicating branch
with value 2I B . Slew rate can only be increased in class A op-amps has negligible dimensions (transistors downscaled by a factor 5)
by increasing I B (and consequently the static power dissipation). reducing area and static power consumption.
Many class AB two-stage op-amps have been reported [4]–[6] In order to achieve large negative-output currents (and correspond-
to avoid this limitation. Most of them feature relatively modest ingly large negative slew rate), nonlinear adaptive loads can be used
effective slew rate improvement and require additional complex similarly to the technique introduced in [8] and also reported in [2]
circuitry, and/or nonnegligible additional static power dissipation, and [10]. This modification is discussed next.
or increased supply requirements. This decreases their current effi-
ciency, defined here as the ratio of the maximum output current to
B. Class AB Two-Stage Op-Amp Using Adaptive Loads
the total op-amp static current (including that of circuitry added
to achieve class AB operation), i.e., CE = Ioutmax /IQtotal . One Starting from the circuit of Fig. 1(a), class AB operation can
scheme reported in [7] and illustrated in Fig. 1(b) achieves class be achieved by including an adaptive load at the input stage. Two
AB operation with very small additional hardware. It includes a large different alternatives are shown in Fig. 1(d) and (c), which will
resistive element Rlarge (implemented with a minimum size diode- be named adaptive load types I and II, respectively. In both cases,
connected transistor) and a small capacitor Cbat . This combination the adaptive loads exploit the large variation of output resistance of
operates as a floating battery that transfers ac variations taking transistors M2triode -M2Ptriode between triode and saturation regions.
place at the gate of MoP to the gate of MoN . The output stage Bias voltage VbR sets these transistors at the boundary between triode
and saturation regions in quiescent conditions. With both schemes, a
Manuscript received September 10, 2012; revised January 24, 2013; current increase in Ia or Ib causes transistors M2triode or M2Ptriode
accepted March 30, 2013. Date of publication May 6, 2013; date of current to go in triode mode and to develop large drain-source voltages.
version March 18, 2014. This work was supported by the Spanish Ministerio These changes cause large variations at nodes a and b, which lead to
de Economía y Competitividad under Grant TEC2010-21563-C02-01.
large currents in the output transistors MoP and, thanks to the current
J. Aguado-Ruiz and A. Lopez-Martin are with the Department of Electrical
and Electronic Engineering, Public University of Navarra, Pamplona replicating branch, MoN .
E-31006, Spain (e-mail: jesus.aguado@unavarra.es; antonio.lopez@ The performance of these circuits is similar to that of the circuit
unavarra.es). of Fig. 2(b). In this case, the adaptive load has been included directly
J. Lopez-Lemus and J. Ramirez-Angulo are with the Klipsch School in the current replicating branch, leading to extremely large negative-
of Electrical Engineering, New Mexico State University, Las Cruces, output currents. The circuit is based on a modification of the diode-
NM 88003-0001 USA (e-mail: jlemus@inaoep.mx; jramirez@nmsu.edu).
Color versions of one or more of the figures in this paper are available
connected load in the current replicating branch by adding a transistor
online at http://ieeexplore.ieee.org. MoNtriode between the gate of MoNR and the lower supply rail. A bias
Digital Object Identifier 10.1109/TVLSI.2013.2256946 voltage with value Vbtriode = VSS + VGS + VDSsat = VTH + 2VDSsat
1063-8210 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
944 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 4, APRIL 2014

Vy
M2 M2P MoP M2 M2P MoP M2R M2 M2P MoP
x1 x1 x2 x1 x1 x2 x1 x1 x2
Cc Cc x0.2 Cc
Rc Rc Rc
0.2Ia Ia Ib Vout
Vout Vout

M1 M1P M1 M1P M1 M1P


x1 x1 Vin- x1 x1 Vin+ Vin- x1 x1 Vin+
Vin- Vin+

2IB
Cbat 2Ia
2IB 2IB 2IB
V’y
MB MoN MB MoN MoNR MB MoN
x2 x2 x2 x2 x2
x2 Rlarge x0.2
Vx
Vbn Vbn Vbn

(a) (b) (c)

M2Ptriode
M2R M2triode VbR MoP M2R M2triode M2Ptriode MoP
x0.2 x1 x1 X1.8 x0.2 x1 x1 X1.8
M2P
M2 M2P M2 VbR
x1 x1 x1 x1
b Cc b Cc
0.2Ia a Ia Ib 0.2Ia a Ia Ib
Rc Rc
Vout Vout
M1 M1P M1 M1P
Vin- x1 x1 Vin+ Vin- x1 x1 Vin+

2IB 2IB
MoNR MB MoN MoNR MB MoN
x2 X1.8 x0.2 x2 X1.8
x0.2
Vbn Vbn

(d) (e)

Fig. 1. (a) Conventional two-stage Miller op-amp. (b) Free-class AB op-amp. (c) Push pull op-amp with current replication branch M2R, MoNR. (d) Class
AB two-stage op-amp with current replicating branch using adaptive load II at the input stage. (e) Class AB two-stage op-amp with current replicating branch
using adaptive load I at the input stage.

-3 -3
x 10 x 10
1.5 1.5

1 1
Output Current (A)

Output Current (A)


M2R M2 M2P MoP
x0.2 x1 x1 Cc x2 0.5 0.5
Rc
0.2Ia 0 0
Ia Ib
Vout
-0.5 -0.5
M1 M1P
0.2IB Vin- x1 x1 Vin+ -1 -1
MoNR
x0.2
MBtriode Vbtriode 2IB -1.5 -1.5
1.5 2 2.5 3 3.5 1.5 2 2.5 3 3.5
Vbtriode Time (s) -6 Time (s) -6
x0.25 MoNtriode MB MoN x 10 x 10
x2 x2
x0.2 Vx (a) (b)
Vbn -3 -3
x 10 x 10
1.5 1.5

1 1
Output Current (A)

Output Current (A)

(a) (b) 0.5 0.5

0 0

Fig. 2. (a) Vbtriode circuit generator and (b) class AB two-stage op-amp -0.5 -0.5

with current replicating branch using an adaptive load. -1 -1

-1.5 -1.5
1.5 2 2.5 3 3.5 1.5 2 2.5 3 3.5
Time (s) x 10
-6 Time (s) x 10
-6

is required at the gate of MoNR , where VDSsat = VGS − VTH is (c) (d)

the minimum VDS voltage to operate in saturation. To generate it, Fig. 3. Output current transient responses for (a) conventional operational
the circuit of Fig. 2(a) is used. It is a diode-connected transistor amplifier, (b) operational amplifier with current replicating branch and adap-
MBtriode with W/L equal to 1/4 that of MoNtriode and MoNR so that tive load, (c) operational amplifier with adaptive load type I at the input stage
it achieves twice the VDS,sat and thus its VGS is the required Vbtriode. and current replicating branch, and (d) operational amplifier with adaptive
load type II at the input stage and current replicating branch.
This Vbtriode leaves a quiescent drain-source voltage for MoNtriode
with value VDSsat , which causes MoNtriode to operate (under static
conditions) at the boundary between the triode and saturation regions, helps compensating the current through the Miller capacitor just as
as M2triode -M2Ptriode in Fig. 1(d) and (e). An increase in current in other multipath Miller zero-cancellation schemes.
Ia leads to an increase in the gate source voltage of MoNR , and
a decrease in the drain-source voltage of MoNtriode, which brings III. S IMULATION R ESULTS
this transistor into triode region, generating, consequently, a large Transient postlayout simulations have been made with the oper-
voltage increase at node Vx and correspondingly large output currents ational amplifiers configured in unity-gain closed loop as voltage
in transistor MoN . Then, the negative slew rate is improved and followers, and results are shown in Fig. 3. The figure compares sim-
approximately equal to positive slew rate. ulations of the current in the load capacitor of the conventional class
The circuit of Fig. 2 is denoted as “operational amplifier with A op-amp of Fig. 1(a) with the class AB op-amp of Fig. 2, and both
current replicating branch and adaptive load” here. Note from the class AB op-amps with adaptive loads at the input stage of Fig. 1(d)
analysis in the Appendix that the use of two gain branches in the and (e). The unitary transistor dimensions are (W/L) N = 50/1
proposed topologies is not harmful in terms of stability of the ac and (W/L) P = 140/1. I B = 100 μA, C L = 30 pF, VDD =
response, but in fact it is beneficial. The current replicating branch 1.65 V, VSS = −1.65 V, Rc = 2 k, Cc = 10 pF, and
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 4, APRIL 2014 945

80
(a)
(b)
(c)
60
(d)

40
Magnitude (dB)

20
0dB

-20 Fig. 6. Prototype test chip microscopic photograph.


10MHz

0.8 0.8
-40 2 3 4 5 6 7 8
10 10 10 10 10 10 10 0.6 0.6
Frequency (Hz)
0.4 0.4

0.2 0.2

V
Fig. 4. Open-loop magnitude frequency response for the four circuits under
0 0
test and detail of the interest zone centered at 10 MHz. (a) Conventional
-0.2 -0.2
operational amplifier. (b) Operational amplifier with current replicating branch
-0.4 -0.4
and adaptive load. (c) Operational amplifier with adaptive load type I at the 0 1 2 3 4 0 1 2 3 4
Time (s) -6
x 10 Time (s) -6
x 10
input stage and current replicating branch. (d) Operational amplifier with
(a) (b)
adaptive load type II at the input stage and current replicating branch. 0.8 0.8

0.6 0.6
0
(a) 0.4 0.4

-20 (b) 0.2 0.2

V
(c)
(d) 0 0
-40
-0.2 -0.2
-60
Phase Margin (º)

90º -0.4 -0.4


0 1 2 3 4 0 1 2 3 4
-80 Time (s) -6
x 10 Time (s) x 10
-6

(c) (d)
-100

-120 Fig. 7. Experimental transient response for (a) conventional operational


amplifier, (b) operational amplifier with current replicating branch and adap-
-140
tive load, (c) operational amplifier with adaptive load type I at the input stage
-160 and current replicating branch, and (d) operational amplifier with adaptive
load type II at the input stage and current replicating branch.
-180 10MHz

-200 0 1 2 3 4 5 6 7 8
10 10 10 10 10 10 10 10 10
Frequency (Hz) class AB two-stage op-amps: the one with adaptive load in the current
replicating branch (Fig. 2 and square C in Fig. 6, 122 × 275 μm),
Fig. 5. Open-loop phase-frequency response for the four circuits under and the two schemes with adaptive load at the input stage
test and detail of the interest zone centered at 10 MHz. (a) Conventional [Fig. 1(d) and (e) and squares B and A in Fig. 6, 115 × 297 μm]. The
operational amplifier. (b) Operational amplifier with current replicating branch
and adaptive load. (c) Operational amplifier with adaptive load type I at the circuits have been biased with ±1.65 V power supplies and 100 μA
input stage and current replicating branch. (d) Operational amplifier with of bias unitary current.
adaptive load type II at the input stage and current replicating branch. Fig. 7 shows the measured transient pulse response of the four
fabricated circuits working as voltage followers with unity gain. The
input is a pulse between 600 and −200 mV and the frequency is
Vbiastriode = VSS + 1.25 V. The Miller compensation net is the same 200 kHz (so, the pulse width is 2.5 μs). Load capacitance was 30 pF.
in all of the four circuits.
It can be seen that the class AB operation of the three proposed
It can be seen that, while the conventional op-amp works in circuits improves significantly the negative slew rate behavior, as the
class A, class AB performance is achieved in the three proposed simulations predicted.
topologies getting negative output currents much larger than I B and
Table I summarizes the main measurement results of the four
approximately of the same order than the positive output current. This circuits under test. Note the improvement in terms of negative slew
result confirms the improvement in negative slew rate achieved with rate of the proposed circuits, which is between four and five times
these topologies.
larger than the conventional class A op-amp. Consequently, almost
Figs. 4 and 5 compare the open-loop magnitude and phase symmetrical performance is achieved, specially with the topology
responses of the circuits of Figs. 1(a), (d), (e), and 2. It can be with adaptive load in the current replicating branch, which has
seen that the four schemes have similar dc open-loop gains of
22 V/μs of positive slew rate and 24 V/μs of negative slew rate.
approximately 70 dB; note that the proposed circuits improve the GB Table I also shows the improvement in terms of GB and PM (see
and phase margin as compared to the conventional class A op-amp. Appendix). Adaptive loads at the input stage improve the performance
This is due to a negative zero introduced in the frequency response by
in terms of CMRR and PSRR but slightly degrade offset. This is
the additional gain path to the output provided by the extra current- due to the inclusion of additional circuitry in the first stage of the
replicating branch. This behavior will be justified in Appendix at the operational amplifier, which may harm the symmetry of the circuit
end of the document.
introducing some mismatch. Comparison with other techniques is also
provided in Table I. Although comparison is difficult since different
IV. M EASUREMENT R ESULTS loads are employed in each work, note that our approach presents
The following experimental results have been obtained by testing a good SR and GB and improved phase margin.
prototype chip (Fig. 6) containing the conventional class A two-stage The common mode input range (CMIR) is almost the same for
op-amp (square D in Fig. 6, 110 × 250 μm) and the three proposed all the topologies in this brief. It could be extended to rail-to-rail
946 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 4, APRIL 2014

TABLE I
S UMMARY OF M EASUREMENT R ESULTS AND C OMPARISON W ITH O THER W ORKS

Parameter Conventional CRB&Adaptive Adaptive Load Adaptive Load [6] [14] [15]
Fig. 1(a) Load–Fig. 2 Input I–Fig. 1(d) Input II–Fig. 1(e)
Supply (V) 3.3 3.3 3.3 3.3 4.75 10 3
Power (mW) 1.32 1.38 1.36 1.36 1.6 12.5 2.1
SR− (V/us) 4 22 16 19 2.1 30 74
SR+ (V/us) 22 24 24 24 1.45 11.1 90
Offset (mV) 1.5 0.2 4.3 2.4 1 4.8 0.1
A0 (dB) 68 68 75 70 72 66 94
GB (MHz) 10.9 21.8 17.3 21.2 1.5 10 54
PM (◦ ) 70 73 78 77 N/A 47 61
CMRR (dB) 78 75 88 89 85 67 43-58
PSRR+ (dB) 72 78 80 78 85 78 81-106
PSRR− (dB) 70 75 81 77 95 74 77-97
THD @ 1 V, 100 KHz (dB) −56 −54 −55 −53 −80 N/A −46
CMIR (V) −1 to Vdd −1 to Vdd −0.95 to Vdd −0.95 to Vdd −0.3 to 3.1 −4.6 to 3.1 rail to rail

operation using floating gate (FG) techniques [11]. A FGMOS input V1 Vout
version of a previous class AB op-amp with current replicating branch C1 R1 C2 R2 gmfVin
Rc Cc
design was fabricated in a previous prototype chip and rail-to-rail
operation was verified experimentally. gm1Vin gm2V1

V. C ONCLUSION
Fig. 8. Small-signal model of class AB op-amps with replica bias branch.
Various schemes of power-efficient class AB two-stage op-amps
using a current replication branch and adaptive loads have been
Pole p1 is the dominant pole at node V1 generated by Miller
introduced and experimentally tested. They achieve approximately
capacitance CMiller = Cc A I I , where A I I = gm2 R2 is the gain of
symmetrical and high slew rate with very small additional static
the second stage, and by output resistance of first-stage R1 . Pole p2
power dissipation and small additional circuitry. Measurement results
is a high-frequency pole, which by design (properly choosing Cc )
show that the inclusion of adaptive loads in the current replicating
is usually set at 2 GB, approximately. Pole p3 is at very high
branch instead of the input stage is advantageous in terms of
frequency and its effect is negligible.
offset.
The additional path to the output in our proposal modifies the
location of the LHP created by Rc -Cc , which becomes
A PPENDIX A  
 
−1 Rc 1
AC A NALYSIS z 1 = gmf C1 + Cc 1 + + C c Rc −
gm2 R1 gm2
Fig. 8 shows the small signal model for the class AB op-amps gm1
with current replicating branch. Node labeled by V1 is the output of −1
≈  . (3)
the first stage. C1 and R1 are the parasitic capacitance and resistance 1 + gmf g
Cc Rc − gm2 gm1 m2
of this node, respectively. They are C1 = CgsoP + Cdb1P + Cdb2P
and R1 = rds1P rds2P . Node-labeled Vout corresponds to the output The approximation is made assuming C1 Cc and Rc R1 .
node. C2 and R2 are the capacitance and resistance associated with Note that if gmf = 0, the conventional zero location results, as
this node, respectively. They are C2 = CdboP + CdboN + C L and expected. In our case, from (1), gmf = gm1 , and (3) results in
R2 = rdsoP rdsoN R L . Note that they include the load capacitance −1
and resistance if any, respectively. The path through the replica bias z1 = (4)
Rc C c
branch has been represented by the voltage-controlled current source
becoming a high-frequency zero with negligible influence. Note that
gmf v in , where
in theory, Rc is not required, as with Rc = 0, z 1 goes to −∞. In fact,
g gmoN gm1 0.2 · 10 · g m1 Rc is not used in multipath Miller zero cancellation methods [12] as
gmf ≈ m2R ≈ ≈ gm1 . (1)
gm2 gm2oN T riode 2 2 the extra path allows cancelling the RHP zero created by Cc . The
additional path to the output also creates a new zero
The proposed schemes, besides providing power-efficient class  
gm1 g m2
AB operation, implement a multipath Miller zero cancellation 1+ C Rc
C c + R1 + gmf
1 1
Rc − gm2
scheme [12], [13]. Straightforward analysis leads to a transfer func- z2 = −
Rc C 1
tion with two negative real zeros (z 1 and z 2 ) and three negative real  
gm1 g m2 1
poles ( p1 , p2 , and p3 ). The poles are the same as the conventional 1 + gmf Rc − gm2
Miller amplifier with lead compensation resistance Rc . They are ≈− (5)
Rc C 1
−1 −gm2 −1 where again the approximation is made with the same assumptions
p1 = , p2 = , p3 = . (2)
R1 R2 gm2 Cc C1 + C2 Rc C 1 as in (3). Note again that if gmf = 0, the zero vanishes as expected.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 4, APRIL 2014 947

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in gmf have little effect. With On-Chip Comparison
2) Effect in the location of poles and zeros: Note from (2) that
Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes,
poles are not influenced by gmf . However, from (3), and (5),
and Bruno Rouzeyre
a small deviation in gmf could slightly modify the location of
the zeros. Zero z 1 would still be at high frequency (assuming
Abstract— Hardware implementation of cryptographic algorithms is
small or zero Rc ), but to control the influence of z 2 in the phase subject to various attacks. It has been previously demonstrated that scan
margin, proper layout techniques should be used to minimize chains introduced for hardware testability open a back door to potential
such mismatch. attacks. Here, we propose a scan-protection scheme that provides testing
facilities both at production time and over the course of the circuit’s life.
The underlying principles to scan-in both input vectors and expected
R EFERENCES responses and to compare expected and actual responses within the
circuit. Compared to regular scan tests, this technique has no impact
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1063-8210 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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