Philips Semiconductors Product specification

Phase-locked loop NE/SE564

DESCRIPTION PIN CONFIGURATIONS

The NE/SE564 is a versatile, high guaranteed frequency
phase-locked loop designed for operation up to 50MHz. As shown D, N Packages
in the Block Diagram, the NE/SE564 consists of a VCO, limiter,
phase comparator, and post detection processor. V+ 1 16 TTL OUTPUT

LOOP GAIN CONTROL 2 15 HYSTERESIS SET

FEATURES
• Operation with single 5V supply INPUT TO PHASE COMP
FROM VCO
3 14 ANALOG OUT

• TTL-compatible inputs and outputs LOOP FILTER 4 13 FREQ. SET CAP

• Guaranteed operation to 50MHz LOOP FILTER 5 12 FREQ. SET CAP

• External loop gain control FM/RF INPUT 6 11 VCO OUT 2

• Reduced carrier feedthrough BIAS FILTER 7 10 V+

• No elaborate filtering needed in FSK applications GND 8 9 VCO OUT TTL

• Can be used as a modulator

• Variable loop gain (externally controlled) TOP VIEW
SR01025

APPLICATIONS Figure 1. Pin Configuration

• High speed modems
• Signal generators
• FSK receivers and transmitters
• Various satcom/TV systems
• Frequency Synthesizers
• pin configuration

ORDERING INFORMATION
DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #
16-Pin Plastic Small Outline (SO) Package 0 to +70°C NE564D SOT109-1
16-Pin Plastic Dual In-Line Package (DIP) 0 to +70°C NE564N SOT38-4
16-Pin Plastic Dual In-Line Package (DIP) -55 to +125°C SE564N SOT38-4

BLOCK DIAGRAM
V+

4 5 1 14

PHASE 2
LIMITER
6 COMPARATOR
DC
3 RETRIEVER
7
11 AMPLIFIER SCHMITT
TRIGGER
16
9
VCO POST DETECTION
PROCESSOR
10 15

12 13 8

SR01026

Figure 2. Block Diagram

1994 Aug 31 1 853-0908 13720

Philips Semiconductors Product specification

Phase-locked loop NE/SE564

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNITS
V+ Supply voltage
Pin 1 14 V
Pin 10 6 V
IOUT Sink Max (Pin 9) and sourcing (Pin 11) 11 mA
IBIAS Bias current adjust pin (sinking) 1 mA
PD Power dissipation 600 mW
Operating ambient temperature
TA NE 0 to +70 °C
SE -55 to +125 °C
TSTG Storage temperature range -65 to +150 °C
NOTE:
Operation above 5V will require heatsinking of the case.

DC AND AC ELECTRICAL CHARACTERISTICS

VCC = 5V; TA = 0 to 25°C; fO = 5MHz, I2 = 400µA; unless otherwise specified.
LIMITS LIMITS
SYMBOL PARAMETER TEST CONDITIONS SE564 NE564 UNITS
MIN TYP MAX MIN TYP MAX
Maximum VCO frequency C1 = 0 (stray) 50 65 45 60 MHz
Input > 200mVRMS
TA = 25°C 40 70 40 70
TA = 125°C 20 30
Lock range % of fO
TA = -55°C 50 80
TA = 0oC 70
TA = 70°C 40
Capture range Input > 200mVRMS, R2 = 27Ω 20 30 20 30 % of fO
fO = 5MHz,
TA = -55°C to +125°C 500 1500
TA = 0 to +70°C
VCO frequency drift with = 0 to +70°C 600 PPM/oC
temperature
fO = 5MHz, 300 800
TA = -55°C to +125°C 500
TA = 0 to +70°C
C1 = 91pF
VCO free-running frequency 4 5 6 3.5 5 6.5 MHz
RC = 100Ω “Internal”
VCO frequency change with
VCC = 4.5V to 5.5V 3 8 3 8 % of fO
supply voltage
Modulation frequency: 1kHz
fO = 5MHz, input deviation:
2%T = 25°C 16 28 mVRMS
28
1%T = 25°C 8 14 mVRMS
Demodulated output voltage 14
1%T = 0°C 16 mVRMS
13
1%T = -55°C 6 10 8 mVRMS
1%T = 70°C mVRMS
15
1%T = 125°C 12 16 mVRMS
Distortion Deviation: 1% to 8% 1 1 %
S/N Signal-to-noise ratio Std. condition, 1% to 10% dev. 40 40 dB
AM rejection Std. condition, 30% AM 35 35 dB
Modulation frequency: 1kHz
Demodulated output at oper- fO = 5MHz, input deviation: 1% mVRMS
ating voltage VCC = 4.5V 7 12 7 12 mVRMS
VCC = 5.5V 8 14 8 14
ICC Supply current VCC = 5V I1, I10 45 60 45 60 mA

Output
VOUT = 5V, Pins 16, 9 1 20 1 20 µA
“1” output leakage current
IOUT = 2mA, Pins 16, 9 0.3 0.6 0.3 0.6 V
“0” output voltage
IOUT = 6mA, Pins 16, 9 0.4 0.8 0.4 0.8 V

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Philips Semiconductors Product specification

Phase-locked loop NE/SE564

TYPICAL PERFORMANCE CHARACTERISTICS

Lock Range vs Signal Input

1000
8

6 IPIN = 400µA
2 VCO Capacitor vs Frequency
4 106
IPIN = 0µA
2
105
INPUT SIGNAL LEVEL – mV

CAPACITANCE pF
104

100 103
8

6 102

4 10

1
VCC 5V .1 1 10 102 103 104 105
2
fo = 5MHz FREQUENCY kHz

10
0.7 0.8 0.9 1.0 1.1 1.2 1.3

NORMALIZED LOCK RANGE

Typical Noirmalized VCO Typical Noirmalized VCO Typical Noirmalized VCO

Frequency as a Function of Frequency as a Function of Frequency as a Function of
Pin 2 Bias Current Pin 2 Bias Current Temperature
NORMALIZED VCO FREQUENCY
NORMALIZED VCO FREQUENCY

NORMALIZED VCO FREQUENCY

1.10
VCO FREQUENCY: 50MHz

1.05
1.01 FREQUENCY: 50MHz 1.10
BIAS CURRENT: — 200µA
FREQUENCY: 5MHz
1.00 1.00 1.05
0.99
1.00
0.95
0.98
0.95 FREQUENCY: 500MHz
0.97 BIAS CURRENT: — 200µA
0.90
0.96 0.90

–600µA –400 –200 0 +200 –600µA –400 –200 0 +200 +400 –50 –25 25 0 25 50 75 100 125

BIAS CURENT (µA), PIN 2 BIAS CURENT (µA), PIN 2 TEMPERATURE (INoC)

SR01027

Figure 3. Typical Performance Characteristics

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Philips Semiconductors Product specification

Phase-locked loop NE/SE564

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

VD – PHASE COMPARATOR’S
OUTPUT VOLTAGE IN mV

800

VCO FREQUENCY
IBIAS = 200µA IN MHz
600 IBIAS = 400µA
IBIAS = 0µA 1.6 IBIAS = 800µA
IBIAS = 800µA
IBIAS = 00µA
400
1.4
fo = 1.0MHz

200 1.2

0
40 60 100 120 140 160 –400 –200 200 400 600 800
VDIN mV
0 – PHASE
–200 ERROR IN .8
DEGREES

.6
–400

–600

–800

Variation of the Comparator’s Output Voltage VCO Output Frequency as a Function of

vs Phase Error and Bias Current (KD) Input Voltage and Bias Current (KO)
SR01028

Figure 4. Typical Performance Characteristics (cont.)

TEST CIRCUIT
+5V

R3 1K

R1
VCO
15 OUYPUT
C3 pF 390
INPUT 1 10 16 9
2
6 3 DEMODULATED
0.1µF 1K
7 14 OUTPUT

R2 564 0.1µF
C2
4 13
430pF C1
C2 R2
5 12
430pF 8

SR01029

Figure 5. Test Circuit

1994 Aug 31 4
Philips Semiconductors Product specification

Phase-locked loop NE/SE564

FUNCTIONAL DESCRIPTION Phase Comparator Section

The phase detection processor consists of a doubled-balanced
(Figure 6) modulator with a limiter amplifier to improve AM rejection.
The NE564 is a monolithic phase-locked loop with a post detection Schottky-clamped vertical PNPs are used to obtain TTL level inputs.
processor. The use of Schottky clamped transistors and optimized The loop gain can be varied by changing the current in Q4 and Q15
device geometries extends the frequency of operation to greater which effectively changes the gain of the differential amplifiers. This
than 50MHz. can be accomplished by introducing a current at Pin 2.
In addition to the classical PLL applications, the NE564 can be used
Post Detection Processor Section
as a modulator with a controllable frequency deviation.
The post detection processor consists of a unity gain
The output of the PLL can be written as shown in the following transconductance amplifier and comparator. The amplifier can be
equation: used as a DC retriever for demodulation of FSK signals, and as a
post detection filter for linear FM demodulation. The comparator has
(fIN - fO)
VO = (1) adjustable hysteresis so that phase jitter in the output signal can be
KVCO
eliminated.
KVCO = conversion gain of the VCO As shown in the equivalent schematic, the DC retriever is formed by
fIN = frequency of the input signal the transconductance amplifier Q42 - Q43 together with an external
capacitor which is connected at the amplifier output (Pin 14). This
fO = free-running frequency of the VCO forms an integrator whose output voltage is shown in the following
The process of recovering FSK signals involves the conversion of equation:
the PLL output into logic compatible signals. For high data rates, a gM
considerable amount of carrier will be present at the output of the VO = VINdt (3)
C2
PLL due to the wideband nature of the loop filter. To avoid the use
of complicated filters, a comparator with hysteresis or Schmitt trigger gM = transconductance of the amplifier
is required. With the conversion gain of the VCO fixed, the output
C2 = capacitor at the output (Pin 14)
voltage as given by Equation 1 varies according to the frequency
deviation of fIN from fO. Since this differs from system to system, it VIN = signal voltage at amplifier input
is necessary that the hysteresis of the Schmitt trigger be capable of
With proper selection of C2, the integrator time constant can be
being changed, so that it can be optimized for a particular system.
varied so that the output voltage is the DC or average value of the
This is accomplished in the 564 by varying the voltage at Pin 15
input signal for use in FSK, or as a post detection filter in linear
which results in a change of the hysteresis of the Schmitt trigger.
demodulation.
For FSK signals, an important factor to be considered is the drift in
The comparator with hysteresis is made up of Q49 - Q50 with
the free-running frequency of the VCO itself. If this changes due to
positive feedback being provided by Q47 - Q48. The hysteresis is
temperature, according to Equation 1 it will lead to a change in the
varied by changing the current in Q52 with a resulting variation in the
DC levels of the PLL output, and consequently to errors in the digital
loop gain of the comparator. This method of hysteresis control,
output signal. This is especially true for narrowband signals where
which is a DC control, provides symmetric variation around the
the deviation in fIN itself may be less than the change in fO due to
nominal value.
temperature. This effect can be eliminated if the DC or average
value of the signal is retrieved and used as the reference to the Design Formula
comparator. In this manner, variations in the DC levels of the PLL The free-running frequency of the VCO is shown by the following
output do not affect the FSK output. equation:
VCO Section fO ≅
1
(4)
Due to its inherent high-frequency performance, an emitter-coupled 22 RC (C1 + CS)
oscillator is used in the VCO. In the circuit, shown in the equivalent
schematic, transistors Q21 and Q23 with current sources Q25 - Q26 RC = 100Ω
form the basic oscillator. The approximate free-running frequency of C1 = external cap in farads
the oscillator is shown in the following equation:
CS = stray capacitance
1
fO ≅ (2) The loop filter diagram shown is explained by the following equation:
22 RC (C1 + CS)
1
RC = R19 = R20 = 100Ω (INTERNAL) fS = (First Order) (5)
1 + sRC3
C1 = external frequency setting capacitor
R = R12 = R13 = 1.3kΩ (Internal)*
CS = stray capacitance
By adding capacitors to Pins 4 and 5, a pole is added to the loop
Variation of VD (phase detector output voltage) changes the transfer at
frequency of the oscillator. As indicated by Equation 2, the
1 NOTE:
frequency of the oscillator has a negative temperature coefficient ω= RC3 *Refer to Figure 6.
due to the monolithic resistor. To compensate for this, a current IR
with negative temperature coefficient is introduced to achieve a low
frequency drift with temperature.

1994 Aug 31 5
Philips Semiconductors Product specification

Phase-locked loop NE/SE564

EQUIVALENT SCHEMATIC



 
  
  




















 







  


  
 

  

 

   







    
 


 
  

 

 



 

 



 


 
  











 
 

    
 


     



   

 




 
 







 

  



 

   

 










 

  
SR01030

Figure 6. Equivalent Schematic

LOCK RANGE ADJUSTMENT

I2
0.01µF

LOOP FILTER
0.01µF
0.47µF 16 2 11 4
FM INPUT
6 5
fO = 5MHz
1k
fM = 1kHz 7 15 ANALOG OUT
564 1kHz
.01µF
BIAS FILTER 3 14 POST DETECTION FILTER
0.1µF
1
13
8 10 9 12
80pF

fO = 5MHz
FREQUENCY SET CAP

1k

5V 5V
SR01031

Figure 7. FM Demodulator at 5V

1994 Aug 31 6
Philips Semiconductors Product specification

Phase-locked loop NE/SE564

APPLICATIONS 5V

FM Demodulator I2 FINE FREQUENCY

ADJUSTMENT
The NE564 can be used as an FM demodulator. The connections
2k
for operation at 5V and 12V are shown in Figures 7 and 8, MODULATING
respectively. The input signal is AC coupled with the output signal INPUT
1kHz
being extracted at Pin 14. Loop filtering is provided by the 16 2 11 4
0.47µF
capacitors at Pins 4 and 5 with additional filtering being provided by
1kHz 6 5
the capacitor at Pin 14. Since the conversion gain of the VCO is not 1k
very high, to obtain sufficient demodulated output signal the 7 15
564
frequency deviation in the input signal should be 1% or higher. .01µF
3 14

Modulation Techniques 1
13
The NE564 phase-locked loop can be modulated at either the loop 8 10 9 12
filter ports (Pins 4 and 5) or the input port (Pin 6) as shown in Figure 80pF
9. The approximate modulation frequency can be determined from
the frequency conversion gain curve shown in Figure 10. This curve fO = 5MHz
will be appropriate for signals injected into Pins 4 and 5 as shown in FREQUENCY SET CAP

Figure 9. 5V
1k

MODULATED OUTPUT
I2 LOCK RANGE ADJUSTMENT 5V (TTL) SR01033
0.01µF
Figure 9. Modulator
LOOP FILTER The lock range graph indicates that the +1.0MHz frequency
0.01µF
deviations will be within the lock range for input signal levels greater
0.47µF 16 2 11 4
FM INPUT than approximately 50mV with zero Pin 2 bias current. (While
fO = 5MHz 6 5
1k
strictly this figure is appropriate only for 50MHz, it can be used as a
fM = 1kHz ANALOG OUT
7 15 1kHz guide for lock range estimates at other fO’ frequencies).
BIAS .01µF 564
FILTER 3 14 POST The hysteresis was adjusted experimentally via the 10kΩ
DETECTION
0.1µF FILTER potentiometer and 2kΩ bias arrangement to give the waveshape
1
13 shown in Figure 12 for 20k, 500k, 2M baud rates with square wave
8 10 9 12
FSK modulation. Note the magnitude and phase relationships of the
80pF
phase comparators’ output voltages with respect to each other and
to the FSK output. The high-frequency sum components of the input
fO = 5MHz
.01µF FREQUENCY SET CAP and VCO frequency also are viable as noise on the phase
comparator’s outputs.
200 1k

12V SR01032
OUTLINE OF SETUP PROCEDURE
Figure 8. FM Demodulator at 12V 1. Determine operating frequency of the VCO: IF÷ N in feedback
loop, then
FSK Demodulation fO = N x fIN.
The 564 PLL is particularly attractive for FSK demodulation since it 2. Calculate value of the VCO frequency set capacitor:
contains an internal voltage comparator and VCO which have TTL
1
compatible inputs and outputs, and it can operate from a single 5V CO ≅
power supply. Demodulated DC voltages associated with the mark 2200 fO
and space frequencies are recovered with a single external 3. Set I2 (current sinking into Pin 2) for ≅ 100µA. After operation is
capacitor in a DC retriever without utilizing extensive filtering obtained, this value may be adjusted for best dynamic behavior,
networks. An internal comparator, acting as a Schmitt trigger with V
1.3V
an adjustable hysteresis, shapes the demodulated voltages into and replace with fixed resistor value of R2 = CC .
IB
compatible TTL output levels. The high-frequency design of the 564 2
enables it to demodulate FSK at high data rates in excess of 1.0M 4. Check VCO output frequency with digital counter at Pin 9 of
baud. device (loop open, VCO to φ det.). Adjust CO trim or frequency
adj. Pins 4 - 5 for exact center frequency, if needed.
Figure 10 shows a high-frequency FSK decoder designed for input
frequency deviations of +1.0MHz centered around a free-running 5. Close loop and inject input signal to Pin 6. Monitor Pins 3 and 6
frequency of 10.8MHz. the value of the timing capacitance required with two-channel scope. Lock should occur with ∆φ3 - 6 equal to
was estimated from Figure 8 to be approximately 40pF. A trimmer 90o (phase error).
capacitor was added to fine tune fO’ 10.8MHz.

1994 Aug 31 7
Philips Semiconductors Product specification

Phase-locked loop NE/SE564

6. If pulsed burst or ramp frequency is used for input signal, special
loop filter design may be required in place of simple single
capacitor filter on Pins 4 and 5. (See PLL application section)
7. The input signal to Pin 6 and the VCO feedback signal to Pin 3
must have a duty cycle of 50% for proper operation of the phase
detector. Due to the nature of a balanced mixer if signals are not
50% in duty cycle, DC offsets will occur in the loop which tend to
create an artificial or biased VCO.
8. For multiplier circuits where phase jitter is a problem, loop filter
capacitors may be increased to a value of 10 - 50µF on Pins 4,
5. Also, careful supply decoupling may be necessary. This
includes the counter chain VCC lines.

BIAS 0.22µF 0.22µF

ADJ
+5V
10k 10k
2k 1.2k
HYSTERESIS FSK
ADJUST OUTPUT
2k

1 10 15 16
2
0.1µF
FSK
INPUT 6
0.1µF 1k
14
7 10µF/8V
1k NE564
3
510Ω 0–20pF
*NOTE:
+5V 9 12
Use R9-11 only if rise time is critical.
*510Ω 33pF
11 13
300pF
4 8
5
300pF
SR01034

Figure 10. 10.8MHz FSK Decoder Using the 564

1994 Aug 31 8
Philips Semiconductors Product specification

Phase-locked loop NE/SE564

SR01035

Figure 11. Phase Comparator (Pins 4 and 5) and FSK (Pin 16) Outputs

+5V
BIAS ADJUST
.47µF
10k
CER.

I2
.47µF CER. 2k

.33µF
INPUT SIGNAL 2 1 10 4 LOOP 510Ω
5 FILTER
6 11 .33µF
fT 1kΩ NE564
DET. *510Ω
.47µF VCO
7 9 OUTPUT
VCO
3 8 12 13
NxfT

CO
*NOTE:
Use R9-11 only if rise time is critical.

f = NxfT

÷N

Figure 12. NE564 Phase-Locked Frequency Multiplier

1994 Aug 31 9