KRISHNASAI MANDA

krishnasaimanda@gmail.com
+91-8608704396 www.siliconsys.in
OBJECTIVE:

To pursue a challenging carrier and be a part of progressive organization that gives a scope to enhance my
knowledge and utilizing my skills towards the growth of the organization.

PROFESSIONAL TRAINING:

An Industry Oriented Trainee in VLSI PHYSICAL DESIGN from Institute of Silicon

Systems Pvt Ltd., Hyderabad since August 2018 to January 2019.

COURSE OUTLINE:

VLSI Fundamentals, CMOS Basics, Digital Design, Floor Planning, Power Planning,
Placement and Routing, Clock Tree Synthesis, Static Timing Analysis, Timing optimization,
Cross talk analysis, IR Drop Analysis and Physical Verification.

TOOLS:

Experience in physical design of 130nm and 90nm technologies using Cadence tool
  Cadence Innovus–Floor Planning, Place & Route, and Clock tree synthesis
 Tempus –Static Timing Analysis and Crosstalk Analysis
 Genus- Logic Synthesis
 Assura- Physical Verification

ACADEMIC EDUCATION:

Year of
S.No Course Institution Board/University CGPA/Percentage
Passing

B.Tech
1 SRM University SRM University 2017 9.011
(E.C.E)
Board of Intermediate
2 Intermediate Narayana Jr.College 2013 93
Education, A.P.
Board of Secondary
3 SSC Sama Public School 2011 84
Education, A.P.

SOFTWARE EXPOSURE:

Operating system : Windows, Linux, Unix

Languages : C, Verilog.
Scripting Languages : TCL(Basics)
PROJECTS:

Project 1: ISS_Wrapper
Objective : To optimize for timing as well as power.
Layout Tools : Innovus.
Aspect ratio : 1.8906
Core Utilization : 87.2%
Gate count/Area : 2,96,296/ 1508801.9 um^2
Macros : 12
Standard Cells : 25207
No. of Clocks : 17
Frequency : 200MHz
Technology/Layers : TSMC 130nm/5 Metal Layers
Role : Performing sanity check, Design import, Floor Plan, Power Plan,
Placement, Trail Route, RC Extract, Timing Analysis, CTS, Adding
Filler cells.

Project 2: BLOCK 1
Objective : To meet 0.03% congestion and timing clean
Layout Tools : Innovus.
Aspect ratio : 0.538
Core Utilization : 85.4%
Gate count/Area : 2, 96,296/ 1508801.9 um^2
Macros : 12
Standard Cells : 25207
No. of Clocks : 17
Frequency : 200MHz
Technology/Layers : TSMC 130nm/5 Metal Layers
Role : Performing sanity check, Design import, Floor Plan, Power Plan,
Placement, Trail Route, RC Extract, Timing Analysis, CTS, Adding
Filler cells.

Project 3: BLOCK 2
Objective : To optimize for timing as well as power.
Layout Tools : Innovus.
Gate count : 1, 18,676/1447471.3um^2
Macros : 12
Standard Cells : 23124
No. of Clocks :4
Frequency : 150 MHz
Technology : TSMC 180nm/6 Metal Layers
Role : Performing sanity check, Design import, Floor Plan, Power Plan ,
Placement , Trail Route, RC Extract , Timing analysis , CTS , Adding
Filler Cells.
 LOGIC SYNTHESIS

Project 1:
Name: 16 Bit Counter
Objective : Running Zero and Force Wire Load Model Synthesis by meeting
Timing, optimizing Area and power.
Tools : Genus
No. of Clocks :2
Frequency : 200MHz
Technology : TSMC 90nm
Role : Writing SDC, TCL Scripts, Extracting Timing, Optimizing Area,
Timing and Power.

Project 2:
Name: 256 Bit Counter
Objective : Running Zero Wire Load Model Synthesis and to achieve Maximum
Possible frequency for different VTs.
Tools : Genus
No. of Clocks :1
Frequency : 555MHz(RVT),270MHz(HVT),476MHz(MVT)
Technology : TSMC 90nm
Role : Writing SDC, TCL Scripts, Extracting Timing, Optimizing Area,
Timing and Power.

ACHIEVEMENTS:

 Awarded Merit scholarship for four years by SRM University.

PERSONAL STRENGTHS:

 Self-Motivate.
 Able to adapt any type of environment

EXTRA CURRICULAR:

  Certificate of Appreciation for rendering services as a Committee Head as part of ‘AARUSH’.

  Attended In-plant training at “ECIL”.
  Participated in BLOOD DONATION camp organized by SRM University.
 Participated in Workshop conducted as a part of SHAASTRA at ‘IIT MADRAS”.
PERSONAL DETAILS:

Name : M PVMNP KrishnaSai

Fathers Name : M MaheswaraRao
Date of Birth : 04/01/1996
Sex : Male
Language : English, Telugu.
Marital Status : Single
Nationality : Indian
Address : 2-6,Pillanka,East Godavari District,
Andhra Pradesh-533464.
DECLARATION:

I hereby declare that above mentioned information is true to the best of my knowledge and
belief.

Place : Hyderabad
Date :
(M KrishnaSai)