11.

Discrete time analog circuits

Kanazawa University
Microelectronics Research Lab.
Akio Kitagawa
11.1 Switched capacitor

2
 CMOS Switch (CMOS
Transmission Gate)
Clock

Input Output
n = p

Clock  　RON  C H
Time Constant　
CH

＝

g dsn  g dsp

gdsn, gdsp: Channel conductance of

n-ch MOSFET and p-ch MOSFET
3
 Conductance of CMOS switch
There is a minimum conductance at the middle of VDD and VSS.
n-ch MOSFET
Conductance [S]
Vin - Vout = 0 (Linear region)
gdsn + gdsp
Vgsn  VDD  Vin
Low
Vgsp  VSS  Vin conductance

1
I dsn   n {(Vgsn  VTn )  Vdsn  Vdsn }
2

2 gdsn gdsp
1 2 Large
  n {(VDD  Vin  VTn ) Vin  Vin } conductance is
2
1 I better.
g dsn   dsn   n {(VDD  VTn )  3Vin }
rdsn Vin Vtp Vin
Vtn
VSS VDD
p-ch MOSFET
1 I dsp Minimum conductance is degraded
g dsp     p {(VTp  VSS )  3Vin } by the low power supply voltage
rdsp Vin
and high VTn and VTp. 4
Estimation of ON-resistance of
Quiz: CMOS Switch
Find a ON-resistance of CMOS Switch, assuming that |VTp| = VTn =
0.3(VDD - VSS)、pCOX = 100 (mA/V2) , and VDD - VSS = 0.5 (V).

Answer：
Minimum conductance of CMOS switch is observed at Vin = 0 (V), the
conductance is minimum, assuming that n = p.
g dsn  g dsp   n {(VDD  VTn )  3Vin }   p {(VTp  VSS )  3Vin }
  p {(VDD  VSS )   p  0.3(VDD  VSS )}
 0.7  p (VDD  VSS )
Set Wn and Wp to make Vin dependence
Wp of the conductance a symmetry for
 0.35 p  35 ( S )
Lp positive and negative voltage.
1 Lp
RON   29 (k) NOTE: Normally, RON = ~10k*(L/W)
g dsn  g dsp Wp 5
 Clock Feedthrough error
The error is raised by the charge transfer from the sampling
capacitor to the parasitic capacitance of MOSFET ∝ L.

VG
VG
Cgd slow
Cgs fast
+ V2
Vin Charge transfer time
V2 Vin slow
Channel current CH error
fast
If VG is fallen suddenly (ON→OFF), the charge
of CH is partially transferred to Cgd and V2 is time
decreased.
6
 Charge injection error
The error is raised by the charge transfer from the sampling
capacitor to the channel of MOSFET ∝ LW.

VG

Charge transfer
Vin V2 V2 Vin
Cgb error
CH

When the carrier in the channel of time

MOSFET recombine, the charge is injected
from CH and V2 is decreased.

7
 Cancellation of errors
Common-mode error

error
 
+
Vin M1 CH -
Vout
W/L
Vin Vout +
M1 M2 Vout
CH -
W /L W /(2L) Vin M2 CH error
W/L

1. Withdraw from a dummy switch 2. Set-off of the common-mode error

with the differential amplifier

8
Non-overlapping clock generation
Q
Non-overlapping Clock Generator




Delay

Delay
1: Vin = Q/C (Sampling od input voltage)
2: Vout = -Q/C (Inversion and output) 


Even if only slightly 'H' level of 1
1
and 2 is overlapped, the sampled
charge Q is leaked to VCM line. 2
The non-overlapped clock signals
is employed for the 1 and 2. 9
 Application example of Non-
overlapping Clock
VCM
CF
2D 
1D CC 
+ +
Vin -+ Vout
SC DAI - -
Vin +- Vout
1D CC 
2D 
CF
VCM
1 
 1
1D
1D

2D 2

2 2D
The delay time is adjusted by the number of stages. 10
Complementary clock generation

The size of MOSFET is adjusted to

bring the clock edges in line.




11
11.2 Clocked comparator

12
 Function of a comparator
(Analog comparator)
• If (Vin+ > Vin- ), then Vout = VDD (Logic level = 'H')
• If (Vin+ < Vin- ) , then Vout = VSS (Logic level = 'L')

The same symbol as a single-end OPA is Vout Ideal characteristic

used, but the circuit configuration and
function is different. VDD（'H'）
+
Vin
+ Vout
-
Vin - Real
Vin+ - Vin-
VSS（'L'）
Vin+
Vout Offset voltage
Vin- VOS (comparison error)

13
Symbol
 Specification of a comparator
Parameter Design constraint Description
VDD/VSS max/typ/min
IBIAS max
IACTIVE max dependent on the clock frequency
fS typ Clock frequency
Common-mode input min/max
range
Input-referred offset max VOS << VLSB/2
VOS
Gain min Gain >> (VDD - VSS)/VLSB
Settling time max >> fS
Load capacitance typ
14
Block diagram of a comparator

+
+ out
in + + + + +
- out
in - - -
- - -
out

15
 Clocked Comparator (Sens. amp.)
VDD

Compare
Reset pull-up
Reset Reset transistor
clk

Differential amplifier
Decision circuit in
+
in
-

(n = p) VSS

Latch while Clock = 'L'

+ -
out out
16
 Wide Swing Comparator
VDD
VSS 30/2 30/2 30/2 30/2
120/4

10/2 10/2
+ -
in in
30/2 clk
10/2

VDD 40/4
10/2 10/2
VSS
Rail-to-Rail differential amplifier
Point: Wide gate length L of the tail MOSFET.

- +
out out

17
11.3 Dynamic comparator

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 Dynamic comparator
• Small area
• High precision
• Wide input range
• Cancelling noise and drift in lower frequency than the clock frequency

Non-Overlapping Clock 2 1
Gain = -AV
c
in1

1 out
e
in2
2 1
Voltage gain of a inverter
Clock Slope = －AV
State
phase Vout Vout = Ve
1 Sample Vin-
VM
2 Compare with Vin+
V VDD Ve
VM: Threshold of gate M 19
 Operation of the dynamic
comparator －C C
Vout

VM

VM V2
Ve  Vin1  VC
 Vin1  VM  Vin 2
   VM
Vout   AV (Ve  VM )  VM
If the threshold voltage VM of the inverter is fluctuated, the   AV    VM
fluctuation of the offset voltage is negligible. Because only a
comparison result  is amplified. The voltage gain of inverter
AV is normally low (~20dB). The gain od the comparator can 20
be increased by using additional inverter stage.
Practical implementation of the
dynamic comparator
2 Gain Gain
1 2 1
in1

out
in2
1
The speed is depends on the size of MOSFET and
C, but the small capacitance suffers the kT/C noise
c2 M2 – 2 and charge injection error of CMOS switch.
2 M2 V2   AV    VM 1
Vc 2  VM 2  V2  VM 2  AV    VM 1
Ve 2  VM 1  Vc 2  VM 1  VM 2  AV    VM 1
 AV    VM 2
Vout   AV (Ve 2  VM 2 )
  AV ( AV    VM 2  VM 2 )  VM 2
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  AV2    VM 2
Full-differential dynamic comparator
1
+
in2 VC
+ 1 -
in1 + out
- - 1
in1 + - +
out
- 1
in2
VC

1 Differential
inverter
Clock
State
phase
1 Sample Vin
2 Compare with V1

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