ASSIGNMENT 1, E3 238 ANALOG VLSI CIRCUITS, JAN-APR 2017, ELECTRICAL COMMUNICATION ENGINEERING DEPARTMENT,

INDIAN INSTITUTE OF SCIENCE, BANGALORE (560012), KARNATAKA, INDIA

Assignment 1
Computer-Aided Design of Analog Circuits
E3 238: Analog VLSI Circuits
January 25, 2017

INSTRUCTIONS
 Use the links given in this document to get supplementary material stored on the cloud.
 Follow the instructions in p. 4 to launch design environment on your PC.
 Write a concise report (IEEE transaction format is preferable) following the guidelines
provided in pp. 2-3.
 The last date of report submission is February 8, 2017 (23:59 HRS). To submit your
report, click here.
 Late submissions will be penalized by a 5%-mark reduction per day.
 This assignment is intended to be individual work. Acts of plagiarism will be taken very
seriously.

OBJECTIVE
This assignment serves the following learning goals:
 Getting familiar with commercial EDA tools for analog/RF design.
 Selecting an appropriate device from the design kit for an application based on the
technology information provided by the foundry.
 Simulating various characteristics of a MOSFET described by a complex compact
model and interpreting its operating point details.
 Handling a design problem systematically to reduce design iterations.

DESIGN ENVIRONMENT
Tool Purpose
Cadence® Library Manager To create and edit design libraries
and cells with a given technology
Virtuoso® Schematic Editor L For graphical entry of circuit
(IC617) schematics
Analog Design To setup design variables, analyses,
Environment (ADE) L and probes
Visualization and For post simulation data visualization
Analysis (ViVA) L and analysis
Spectre® (MMSIM151) For simulating analog circuits

Process UMC L130E FSG (Mixed-Mode/RFCMOS)

Technology
Low-𝑉𝑡 Core N-MOSFET:
𝐿𝑚𝑖𝑛 = 0.12 𝜇𝑚
𝑉𝑑𝑑 = 1.2 𝑉
𝑓𝑇 = 110 𝐺𝐻𝑧 @ [(𝐼𝑑 /𝑊 = 463 𝜇𝐴/𝜇𝑚) & (𝑉𝑔𝑠 /𝑉𝑑𝑠 = 0.8 𝑉/1.2 𝑉)]
Design kit UM130FDKMFC0000OA_A02_PB

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ASSIGNMENT 1, E3 238 ANALOG VLSI CIRCUITS, JAN-APR 2017, ELECTRICAL COMMUNICATION ENGINEERING DEPARTMENT,
INDIAN INSTITUTE OF SCIENCE, BANGALORE (560012), KARNATAKA, INDIA

PROBLEM STATEMENT
Design a voltage amplifier with the topology shown in Figure 1, complying with the following
set of specifications (assume zero PVT variation1):
 𝑀𝑎𝑥𝑖𝑚𝑢𝑚 𝑂𝑢𝑡𝑝𝑢𝑡 𝑆𝑤𝑖𝑛𝑔
 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝐺𝑎𝑖𝑛 ≥ 26 𝑑𝐵
 𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ(−3 𝑑𝐵) ≥ 90 𝑀𝐻𝑧
 𝑃𝑜𝑤𝑒𝑟 𝐶𝑜𝑛𝑠𝑢𝑚𝑝𝑡𝑖𝑜𝑛 ≤ 30 𝜇𝑊

Figure 1: CS amplifier followed by a source follower.

GENERAL GUIDELINE
For the given amplifier design problem, consider using N_12_HSL130E (N-MOSFET) and
P_12_HSL130E (P-MOSFET) cells in umc13mmrf library.
As a first step in circuit design, the devices’ characteristics of interest are obtained, which, in
turn, relate to the circuit performance parameters. Based on the performance required,
appropriate dimensions and operating points are chosen for the circuit topology.

Device characterization
The BSIM (version 3.3) model is used in the design kit. The model uses many more
parameters 2 compared to the familiar square-law model to describe a MOSFET. It is
instructive to obtain parameters like 𝑘𝑛,𝑝 ( = 𝜇𝑛,𝑝 𝐶𝑜𝑥 ) by investigating the BSIM model
parameters file of the MOSFETs for hand calculation. Report the values of 𝑘𝑛,𝑝 obtained.

Large-signal dc characteristics
To begin with, consider 𝑊/𝐿 = 50𝜇𝑚/1𝜇𝑚 for the MOSFET characterization.
Simulate 𝐼𝐷 (𝑉𝐺𝑆 , 𝑉𝐷𝑆 , 𝑉𝑆𝐵 ) for the MOSFETs using DC sweep analysis in Spectre®. Include
the following plots in the report:
P1 Transfer characteristics 𝐼𝐷 vs. 𝑉𝐺𝑆 𝑉𝐷𝑆 = 0 𝑉: 200 𝑚𝑉: 𝑉𝐷𝐷
𝑉𝑆𝐵 =0𝑉
P2 Output characteristics 𝐼𝐷 vs. 𝑉𝐷𝑆 𝑉𝐺𝑆 = 0 𝑉: 200 𝑚𝑉: 𝑉𝐷𝐷
𝑉𝑆𝐵 =0𝑉

1 Zero PVT variation implies constant process parameters, supply voltage, and operating temperature.
2 Click here to download BSIM3v3 manual.

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ASSIGNMENT 1, E3 238 ANALOG VLSI CIRCUITS, JAN-APR 2017, ELECTRICAL COMMUNICATION ENGINEERING DEPARTMENT,
INDIAN INSTITUTE OF SCIENCE, BANGALORE (560012), KARNATAKA, INDIA

Small-signal ac characteristics
Simulate low-frequency 𝑔𝑚 and 𝑟0 , and 𝑓𝑇 of the MOSFETs, and obtain the following plots:
P3 (a,b) Low-frequency transconductance 𝑔𝑚 vs. 𝑉𝐺𝑆 𝑉𝐷𝑆 = 0 𝑉: 200 𝑚𝑉: 𝑉𝐷𝐷
𝑔𝑚 vs. 𝐼𝐷 𝑉𝑆𝐵 = 0 𝑉
P4 (a,b) Low-frequency output resistance 𝑟0 vs. 𝑉𝐷𝑆 𝑉𝐺𝑆 = 0 𝑉: 200 𝑚𝑉: 𝑉𝐷𝐷
𝑉𝑆𝐵 = 0 𝑉
P5 (a,b) Transition frequency 𝑓𝑇 vs. 𝑉𝐺𝑆 𝑉𝐷𝑆 = 0 𝑉: 200 𝑚𝑉: 𝑉𝐷𝐷
𝑓𝑇 vs. 𝐼𝐷 𝑉𝑆𝐵 = 0 𝑉

The quantities like 𝑔𝑚 , 𝑟0 , and 𝑓𝑇 can be obtained from operating point information, namely,
gm, gds, and fug of the transistor in the post-simulation data.

Gain-speed versus power tradeoff

For the given application, 𝑔𝑚 𝑟0 , 𝑓𝑇 , and 𝐼𝐷 are chosen as metrics to characterize gain, speed,
and power in the MOSFET. Using the square-law model, setup trade-off relationships among
these metrics (also mention in the report).
Simulate 𝑔𝑚 𝑟0 and 𝑓𝑇 and obtain the following plots (also include these plots in the report):
P5 Gain and speed versus power 𝑔𝑚 𝑟0 vs. 𝐼𝐷 𝑉𝐷𝑆 = 0 𝑉: 200 𝑚𝑉: 𝑉𝐷𝐷
𝑓𝑇 vs. 𝐼𝐷 𝑉𝑆𝐵 =0𝑉
P6 Gain-speed product versus power 𝑔𝑚 𝑟0 𝑓𝑇 vs. 𝐼𝐷 𝑉𝐷𝑆 = 0 𝑉: 200 𝑚𝑉: 𝑉𝐷𝐷
𝑉𝑆𝐵 =0𝑉

Double (or half) the width and the length (one at a time) and re-simulate Plot P5 and P6.
Observe the effect of the scaling on the metrics; write the inference in the report.

Circuit design
Divide the amplifier circuit into two stages: a common-source stage with current source load
and a source follower. Using small-signal model (hybrid-π and/or T model), develop and report
the relationship between the circuit performance parameters (gain and bandwidth)3 and small-
signal model parameters (𝑔𝑚 and 𝑟0 ).
Considering maximum swing constraint, determine voltage level at each node for proper
operation of the circuit.
Identify the critical stage and node and device in the circuit which limits the bandwidth and the
gain. Considering power budget and using 𝑔𝑚 𝑟0 𝑓𝑇 as a figure of merit (FOM) for the device,
obtain an optimum dimension and operating condition for the device. Iterate the steps in Plot
P6 if necessary.
Loosely speaking, connecting any device to the critical node will further degrade the overall
performance. Keeping this in mind, obtain an optimum dimension for the connecting devices
that degrade the FOM of the core device the least. This may take some iterations of steps in
Plot P4.
Having obtained optimal dimensions and operating conditions for all the MOSFETs in the
circuit, verify the overall design via simulations. Include the final design obtained and its
simulated parameters such as, gain, bandwidth, power, swing, and input/output impedances,
in the report.

3Here, the gain refers to the small-signal, low-frequency, unloaded voltage gain between input and
output node, and the bandwidth assumes −3 𝑑𝐵 threshold.

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ASSIGNMENT 1, E3 238 ANALOG VLSI CIRCUITS, JAN-APR 2017, ELECTRICAL COMMUNICATION ENGINEERING DEPARTMENT,
INDIAN INSTITUTE OF SCIENCE, BANGALORE (560012), KARNATAKA, INDIA

INSTRUCTIONS FOR LAUNCHING DESIGN ENVIRONMENT ON

YOUR PC
Login details
 Server address: 10.32.40.203
 Username: Last five digits of your SR number
 Password: avlsiwinter17 (at first login, you will be asked to change the password)
Windows user
o Click here to download MobaXterm (zip file).
o Extract the downloaded zip file and copy the extracted exe file on your desktop.
 Run ‘MobaXterm.exe’.
 Enter the server address in ‘Quick connect’ (top-left) field.
 Choose ‘SSH’ session type, click OK, and enter the username and password on the
terminal.
Linux user
 Run following command in terminal:

$ssh -X <username>@10.32.40.203

To launch Cadence® Virtuoso® (IC617) design environment, run following command on the
terminal:

$virtuoso