SiHB15N60E

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Vishay Siliconix
E Series Power MOSFET
FEATURES
PRODUCT SUMMARY
• Low Figure-of-Merit (FOM) Ron x Qg
VDS (V) at TJ max. 650
• Low Input Capacitance (Ciss)
RDS(on) max. at 25 °C () VGS = 10 V 0.28
• Reduced Switching and Conduction Losses
Qg max. (nC) 76
• Ultra Low Gate Charge (Qg)
Qgs (nC) 11
Qgd (nC) 17
• Avalanche Energy Rated (UIS)
Configuration Single • Material categorization: For definitions please see
www.vishay.com/doc?99912
D
D2PAK (TO-263) APPLICATIONS
• Server and Telecom Power Supplies
• Switch Mode Power Supplies (SMPS)
G • Power Factor Correction Power Supplies (PFC)
• Lighting
G D - High-Intensity Discharge (HID)
S - Fluorescent Ballast Lighting
S

N-Channel MOSFET • Industrial

- Welding
- Induction Heating
- Motor Drives
- Battery Chargers
- Renewable Energy
- Solar (PV Inverters)

ORDERING INFORMATION
Package D2PAK (TO-263)
Lead (Pb)-free and Halogen-free SiHB15N60E-GE3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 600
Gate-Source Voltage ± 20 V
VGS
Gate-Source Voltage AC (f > 1 Hz) 30
TC = 25 °C 15
Continuous Drain Current (TJ = 150 °C) VGS at 10 V ID
TC = 100 °C 9.6 A
Pulsed Drain Currenta IDM 39
Linear Derating Factor 1.4 W/°C
Single Pulse Avalanche Energyb EAS 102 mJ
Maximum Power Dissipation PD 180 W
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C
Drain-Source Voltage Slope TJ = 125 °C 37
dV/dt V/ns
Reverse Diode dV/dtd 7.7
Soldering Recommendations (Peak Temperature) for 10 s 300c °C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 11.6 mH, Rg = 25 , IAS = 4.2 A.
c. 1.6 mm from case.
d. ISD  ID, dI/dt = 100 A/μs, starting TJ = 25 °C.

S12-0647-Rev. B, 26-Mar-12 1 Document Number: 91485

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - 62
°C/W
Maximum Junction-to-Case (Drain) RthJC - 0.7

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 600 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.71 - V/°C
Gate-Source Threshold Voltage (N) VGS(th) VDS = VGS, ID = 250 μA 2 - 4 V
Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA
VDS = 600 V, VGS = 0 V - - 1
Zero Gate Voltage Drain Current IDSS μA
VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 10
Drain-Source On-State Resistance RDS(on) VGS = 10 V ID = 8 A - 0.23 0.28 
Forward Transconductance gfs VDS = 30 V, ID = 8 A - 4.6 - S
Dynamic
Input Capacitance Ciss VGS = 0 V, - 1350 -
Output Capacitance Coss VDS = 100 V, - 70 -
Reverse Transfer Capacitance Crss f = 1 MHz - 5 -
Effective Output Capacitance, Energy pF
Co(er) - 53 -
Relateda
VDS = 0 V to 480 V, VGS = 0 V
Effective Output Capacitance, Time
Co(tr) - 177 -
Relatedb
Total Gate Charge Qg - 38 76
Gate-Source Charge Qgs VGS = 10 V ID = 8 A, VDS = 480 V - 11 - nC
Gate-Drain Charge Qgd - 17 -
Turn-On Delay Time td(on) - 17 34
Rise Time tr - 51 77
VDD = 480 V, ID = 8 A, ns
Turn-Off Delay Time td(off) VGS = 10 V, Rg = 9.1  - 35 70
Fall Time tf - 33 66
Gate Input Resistance Rg f = 1 MHz, open drain - 0.86 - 
Drain-Source Body Diode Characteristics
MOSFET symbol
Continuous Source-Drain Diode Current IS D
- - 15
showing the
A
integral reverse G

Pulsed Diode Forward Current ISM p - n junction diode S - - 60

Diode Forward Voltage VSD TJ = 25 °C, IS = 8 A, VGS = 0 V - - 1.2 V

Reverse Recovery Time trr - 410 - ns
TJ = 25 °C, IF = IS = 8 A,
Reverse Recovery Charge Qrr - 5.4 - μC
dI/dt = 100 A/μs, VR = 20 V
Reverse Recovery Current IRRM - 21 - A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.

S12-0647-Rev. B, 26-Mar-12 2 Document Number: 91485

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

50 TOP 15 V
3
14 V
TJ = 25 °C ID = 8 A
ID, Drain-to-Source Current (A)

13 V

On Resistance (Normalized)
12 V
11 V
2.5
40

RDS(on), Drain-to-Source
10 V
9V
8V
7V
2
30 6V
BOTTOM 5 V
1.5 VGS = 10 V
20
1

10
0.5

0 0
0 5 10 15 20 25 30 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature (°C)

Fig. 1 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature

30 10 000
TOP 15 V
14 V TJ = 150 °C
ID, Drain-to-Source Current (A)

13 V
25 12 V Ciss
11 V
10 V 1000
Capacitance (pF)

9V
20 8V VGS = 0 V, f = 1 MHz
7V Ciss = Cgs + Cgd, Cds Shorted
BOTTOM 6 V
Crss = Cgd
15 100 Coss Coss = Cds + Cgd

10
10 Crss

5
5V
0 1
0 5 10 15 20 25 30 0 100 200 300 400 500 600
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)

Fig. 2 - Typical Output Characteristics Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

50 24
VDS = 480 V
VGS, Gate-to-Source Voltage (V)
ID, Drain-to-Source Current (A)

TJ = 25 °C VDS = 300 V
20 VDS = 120 V
40

16
30
12
TJ = 150 °C
20
8

10
4

0 0
0 5 10 15 20 25 0 20 40 60 80
VGS, Gate-to-Source Voltage (V) Qg, Total Gate Charge (nC)

Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

S12-0647-Rev. B, 26-Mar-12 3 Document Number: 91485

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 SiHB15N60E
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Vishay Siliconix

100 20
ISD, Reverse Drain Current (A)

TJ = 150 °C

ID, Drain Current (A)

15
TJ = 25 °C
10

10

1
5

VGS = 0 V
0.1 0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25 50 75 100 125 150
VSD, Source-Drain Voltage (V) TJ, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature

1000 750
Operation in this Area 725
Limited by RDS(on)
100 IDM = Limited
Brakdown Voltage (V) 700
VDS, Drain-to-Source
ID, Drain Current (A)

675
10
100 μs 650
Limited by RDS(on)*
625
1
1 ms 600

0.1 TC = 25 °C 10 ms 575
TJ = 150 °C 550
Single Pulse BVDSS Limited
0.01 525
1 10 100 1000 10 000 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature (°C)
* VGS > minimum VGS at which RDS(on) is specified

Fig. 8 - Maximum Safe Operating Area Fig. 10 - Temperature vs. Drain-to-Source Voltage

1
Normalized Effective Transient

Duty Cycle = 0.5

Thermal Impedance

0.2

0.1
0.05 0.02
0.1
Single Pulse

0.01
0.0001 0.001 0.01 0.1 1
Pulse Time (s)

Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case

S12-0647-Rev. B, 26-Mar-12 4 Document Number: 91485

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix

RD
VDS QG
10 V
VGS
D.U.T.
RG QGS QGD
+
- VDD

10 V VG
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Charge
Fig. 12 - Switching Time Test Circuit Fig. 16 - Basic Gate Charge Waveform

Current regulator
Same type as D.U.T.
VDS
90 %
50 kΩ

12 V 0.2 µF
0.3 µF

+
10 % VDS
D.U.T. -
VGS
td(on) tr td(off) tf VGS

3 mA

Fig. 13 - Switching Time Waveforms

IG ID
Current sampling resistors

Fig. 17 - Gate Charge Test Circuit

L
VDS
Vary tp to obtain
required IAS

RG D.U.T +
V DD
-
IAS
10 V
tp 0.01 Ω

Fig. 14 - Unclamped Inductive Test Circuit

VDS
tp
VDD

VDS

IAS

Fig. 15 - Unclamped Inductive Waveforms

S12-0647-Rev. B, 26-Mar-12 5 Document Number: 91485

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 SiHB15N60E
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Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage
Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

Note
a. VGS = 5 V for logic level devices

Fig. 18 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91485.

S12-0647-Rev. B, 26-Mar-12 6 Document Number: 91485

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Package Information
Vishay Siliconix

TO-263AB (HIGH VOLTAGE)

A
(Datum A)
3 4 A A B
E c2
H
4 L1 4 Gauge
plane
0° to 8° B
D 5 Detail A Seating plane
H
C C L A1
1 L3 L4
2 3
Detail “A”
L2
Rotated 90° CW
B B
scale 8:1

A
2 x b2
2xb c
E
0.010 M A M B
± 0.004 M B
2xe
Base
5 metal D1
Plating 4
b1, b3

(c) c1 5

(b, b2)
Lead tip Section B - B and C - C E1 4
Scale: none View A - A

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -
A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420
b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -
b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC
b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625
b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110
c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066
c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070
c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC
D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.

Document Number: 91364 www.vishay.com

Revision: 15-Sep-08 1
 AN826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

0.420
(10.668)

(9.017)
0.355
(16.129)
0.635

0.145
(3.683)

0.135
(3.429)

0.200 0.050
(5.080) (1.257)

Recommended Minimum Pads

Dimensions in Inches/(mm)

Return to Index

Document Number: 73397 www.vishay.com

11-Apr-05 1
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Revision: 12-Mar-12 1 Document Number: 91000