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Digital

System
Design
Laboratory Report I

Mehzin Baker
Roll No: 8441
3/4 B.Tech - E.C.E – ‘A’
Digital
System
Design
Laboratory Report I

Sonal Pinto
Roll No: 8449
3/4 B.Tech - E.C.E – ‘A’
Digital
System
Design
Laboratory Report I

Sachin Kurian Suresh


Roll No: 8455
3/4 B.Tech - E.C.E – ‘A’
TABLE OF CONTENTS

1. 4 Bit Ripple Carry Adder (s) using Full Adder (d,s)


2. 16:1 Mux (s,b) using 4:1 Mux(d,s)
3. 4:16 Decoder (s,b) using 2:4 Decoder
4. 8:3 Priority Encoder (s,b) using 4:2 Priority Encoder
5. 4 Bit Carry Look-Ahead Adder
6. 8 Bit Comparator (s,b) using 2 Bit Comparator
7. 4 Bit Adder/Subtractor (s) using 1 Bit Full Adder
8. 2 Digit Decimal Adder (s)
9. 4 Bit Binary-Gray & Gray-Binary Converter (s,b)
4 BIT RIPPLE CARRY ADDER
USING FULL ADDER

ABSTRACT

A device for addition of two n-bit binary numbers, formed by connecting n full adders in cascade,
with the carry output of each full adder feeding the carry input of the following full adder.

The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple
carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from
the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit.
Each full adder requires three levels of logic. In a 4-bit [ripple carry] adder, there are 4 full adders, so
the critical path (worst case) delay is 3 * 2(for carry propagation) + 3(for sum) = 9 gate delays.

RTL
VHDL CODE

HALF ADDER (dataflow)

library ieee;
use ieee.std_logic_1164.all;

entity Half_Adder is
port(a,b:in std_logic;sum,cout:out std_logic);
end Half_Adder;

architecture dataflow of Half_Adder is


begin
sum <= a xor b;
cout <= a and b;
end dataflow;

FULL ADDER (structural)

library ieee;
use ieee.std_logic_1164.all;

entity Full_Adder is
port(A,B,Cin :in std_logic;SUM, COUT:out std_logic);
end Full_Adder;
architecture struct of Full_Adder is

signal c1,c2,c3 : std_logic;


component Half_Adder is
port(a,b: in std_logic;sum,cout:out std_logic);
end component;
begin
x1: Half_Adder port map(A,B,c1,c2);
x2: Half_Adder port map(c1,Cin,SUM,c3);
COUT<= c2 or c3;

end struct;

FULL ADDER(Behavioral)

library ieee;
use ieee.std_logic_1164.all;

ENTITY Adder_1b is
port( a,b,ci: IN std_logic;
s,co: OUT std_logic);
END Adder_1b;

ARCHITECTURE Dataflow of Adder_1b is


BEGIN
s<= a xor b xor ci;
co<= (a and b) or ( ci and (a xor b));
END Dataflow;
4-BIT RIPPLE CARRY ADDER (structural)

library ieee;
use ieee.std_logic_1164.all;
Entity Adder_4_Bit is
port( A,B:IN std_logic_vector(3 downto 0);
Cin:IN std_logic;
SUM:OUT std_logic_vector(3 downto 0);
Cout:OUT std_logic);
end Adder_4_Bit;
Architecture Structure of Adder_4_Bit is
signal c1,c2,c3:std_logic;
component Full_Adder is
port(A,B,Cin:IN std_logic; SUM,COUT:OUT std_logic);
end component;
BEGIN
x1: Full_Adder port map(A(0),B(0),Cin,SUM(0),c1);
x2: Full_Adder port map(A(1),B(1),c1,SUM(1),c2);
x3: Full_Adder port map(A(2),B(2),c2,SUM(2),c3);
x4: Full_Adder port map(A(3),B(3),c3,SUM(3),Cout);
END Structure;

TIMING ANALYSIS
SYNTHESIS REPORT
+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Wed Sep 01 22:15:37 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Adder_4_Bit ;
; Top-level Entity Name ; Adder_4_Bit ;
; Family ; Stratix III ;
; Met timing requirements ; N/A ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 6 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 14 / 296 ( 5 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Sep 01 22:15:04 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Adder_4_Bit ;
; Top-level Entity Name ; Adder_4_Bit ;
; Family ; Stratix III ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 6 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 14 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Wed Sep 01 22:15:23 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Adder_4_Bit ;
; Top-level Entity Name ; Adder_4_Bit ;
; Family ; Stratix III ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 6 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 14 / 296 ( 5 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
-----------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 11.378 ns
From : B[0]
To : SUM[1]
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0

-----------------------------------------------------------------------------------

CONCLUSION

The functional analysis of the logic design follows the truth table of the 4-bit Full adder model.
16:1 MUX
USING 4:1 MUX

ABSTRACT

A multiplexer or mux is a device that performs multiplexing; it selects one of many analog or digital
input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select
lines, which are used to select which input line to send to the output.

RTL
16:1 MUX (behavioural)
16:1 MUX (structural)

VHDL CODE

2:1 MUX (behavioral)

library ieee;
use ieee.std_logic_1164.all;

ENTITY Mux_2to1 is
port (x1,x2,sel:IN std_logic; y:OUT std_logic);
end Mux_2to1;

Architecture behaviour of Mux_2to1 is


begin
process(x1,x2,sel)
begin
if sel='1' then
y<=x2;
else
y<=x1;
end if;
end process;
end behaviour;

4:1 MUX (dataflow)

library ieee;
use ieee.std_logic_1164.all;

ENTITY Mux_4to1_df is
port( x:IN std_logic_vector(3 downto 0);
c:IN std_logic_vector(1 downto 0);
y:OUT std_logic);
end Mux_4to1_df;
Architecture DataFlow of Mux_4to1_df is
begin
y<= (not c(1) and not c(0) and x(0)) OR
(not c(1) and c(0) and x(1)) OR
(c(1) and not c(0) and x(2)) OR
(c(1) and c(0) and x(3));
end DataFlow;

4:1MUX (structural)

library ieee;
use ieee.std_logic_1164.all;

ENTITY Mux_4to1 is
port( x:IN std_logic_vector(3 downto 0);
c:IN std_logic_vector(1 downto 0);
y:OUT std_logic);
end Mux_4to1;

Architecture Structure of Mux_4to1 is


signal q1,q2:std_logic;
component Mux_2to1 is
port(x1,x2,sel:IN std_logic; y:OUT std_logic);
end component;

begin
x1: Mux_2to1 port map(x(0),x(1),c(0),q1);
x2: Mux_2to1 port map(x(2),x(3),c(0),q2);
x3: Mux_2to1 port map(q1,q2,c(1),y);
end;

16:1 MUX (behavioral)

library ieee;
use ieee.std_logic_1164.all;
entity Mux_16to1_b is
port(X: in std_logic_vector(15 downto 0);
Y: out std_logic;
sel: in std_logic_vector(3 downto 0));
end Mux_16to1_b;

Architecture Behaviour of Mux_16to1_b is


BEGIN
Y<= X(0) when (sel="0000") else
X(1) when (sel="0001") else
X(2) when (sel="0010") else
X(3) when (sel="0011") else
X(4) when (sel="0100") else
X(5) when (sel="0101") else
X(6) when (sel="0110") else
X(7) when (sel="0111") else
X(8) when (sel="1000") else
X(9) when (sel="1001") else
X(10) when (sel="1010") else
X(11) when (sel="1011") else
X(12) when (sel="1100") else
X(13) when (sel="1101") else
X(14) when (sel="1110") else
X(15) when (sel="1111") else
'0';
END Behaviour;
16:1 MUX (structural)

library ieee;
use ieee.std_logic_1164.all;

ENTiTY Mux_16to1 is
port(A:IN std_logic_vector(15 downto 0);
B:IN std_logic_vector(3 downto 0);
OP:OUT std_logic);
end Mux_16to1;

Architecture Structural of Mux_16to1 is


signal q1,q2,q3,q4:std_logic;

component Mux_4to1 is
port( x:IN std_logic_vector(3 downto 0);
c:IN std_logic_vector(1 downto 0);
y:OUT std_logic);
end component;

begin
x1: Mux_4to1 port map((A(3),A(2),A(1),A(0)),(B(1),B(0)),q1);
x2: Mux_4to1 port map((A(7),A(6),A(5),A(4)),(B(1),B(0)),q2);
x3: Mux_4to1 port map((A(11),A(10),A(9),A(8)),(B(1),B(0)),q3);
x4: Mux_4to1 port map((A(15),A(14),A(13),A(12)),(B(1),B(0)),q4);
x5: Mux_4to1 port map((q4,q3,q2,q1),(B(3),B(2)),OP);
end Structural;

TIMING ANALYSIS
16:1 MUX (behavioral)
16:1 MUX (structural)

SYNTHESIS REPORT
16:1 MUX (behavioral)

+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 06:28:35 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Mux_16to1_b ;
; Top-level Entity Name ; Mux_16to1_b ;
; Family ; Stratix II ;
; Met timing requirements ; Yes ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 5 / 12,480 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 12,480 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 21 / 343 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 419,328 ( 0 % ) ;
; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
; Device ; EP2S15F484C3 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 06:28:13 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Mux_16to1_b ;
; Top-level Entity Name ; Mux_16to1_b ;
; Family ; Stratix II ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 5 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 21 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 06:28:23 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Mux_16to1_b ;
; Top-level Entity Name ; Mux_16to1_b ;
; Family ; Stratix II ;
; Device ; EP2S15F484C3 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 5 / 12,480 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 12,480 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 21 / 343 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 419,328 ( 0 % ) ;
; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
-----------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 9.568 ns
From : X[2]
To : Y
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0

-----------------------------------------------------------------------------------
16:1 MUX (structural)

+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 00:23:01 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Mux_16to1 ;
; Top-level Entity Name ; Mux_16to1 ;
; Family ; Stratix III ;
; Met timing requirements ; N/A ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 5 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 21 / 296 ( 7 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 00:22:29 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Mux_16to1 ;
; Top-level Entity Name ; Mux_16to1 ;
; Family ; Stratix III ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 5 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 21 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 00:22:48 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Mux_16to1 ;
; Top-level Entity Name ; Mux_16to1 ;
; Family ; Stratix III ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 5 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 21 / 296 ( 7 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
-----------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 9.133 ns
From : A[10]
To : OP
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0

-----------------------------------------------------------------------------------

CONCLUSION

The functional analysis of the logic design follows the truth table of the 16:1 MUX model.
4:16 DECODER
USING 2:4 DECODER

ABSTRACT

A decoder is a device which does the reverse of an encoder, undoing the encoding so that the
original information can be retrieved. The same method used to encode is usually just reversed in
order to decode.

In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit
that converts coded inputs into coded outputs, where the input and output codes are different. e.g.
n-to-2n, binary-coded decimal decoders. Enable inputs must be on for the decoder to function,
otherwise its outputs assume a single "disabled" output code word.

RTL
4:16 DECODER (behavioral)
Y~[118..104]
Equal13
A[3..0]
X[3..0] SEL

4' h1 --
B[3..0]
= DATAA
OUT0
Y~[103..90] 15' h0000 --
Y[15..0]
EQUAL DATAB
Equal12
A[3..0]
SEL

4' h2 --
B[3..0]
= DATAA
MUX21
OUT0

EQUAL
Y~[89..77] 14' h0000 -- DATAB
Equal11
A[3..0]
SEL

4' h3 --
B[3..0]
= DATAA
MUX21

OUT0

EQUAL
Y~[76..65] 13' h0000 -- DATAB
Equal10
A[3..0]
SEL

4' h4 --
B[3..0]
= DATAA
MUX21
OUT0

EQUAL
Y~[64..54] 12' h000 -- DATAB
Equal9
A[3..0]
SEL

4' h5 --
B[3..0]
= DATAA
MUX21

OUT0

EQUAL
Y~[53..44] 11' h000 -- DATAB
Equal8
A[3..0]
SEL

4' h6 --
B[3..0]
= DATAA
MUX21
OUT0

EQUAL
Y~[43..35] 10' h000 -- DATAB
Equal7
A[3..0]
SEL

4' h7 --
B[3..0]
= DATAA
MUX21
OUT0

EQUAL
Y~[34..27] 9' h000 -- DATAB
Equal6
A[3..0]
SEL

4' h8 --
B[3..0]
= DATAA
MUX21
OUT0

EQUAL
Y~[26..20] 8' h00 -- DATAB
Equal5
A[3..0]
SEL

4' h9 --
B[3..0]
= DATAA
MUX21
OUT0

EQUAL
Y~[19..14] 7' h00 -- DATAB
Equal4
A[3..0]
SEL

4' hA --
B[3..0]
= DATAA
MUX21
OUT0

EQUAL
Y~[13..9] 6' h00 -- DATAB
Equal3
A[3..0]
SEL

4' hB --
B[3..0]
= DATAA
MUX21
OUT0

EQUAL
Y~[8..5] 5' h00 -- DATAB
Equal2
A[3..0]
SEL

4' hC --
B[3..0]
= DATAA
MUX21
OUT0

EQUAL
Y~[4..2] 4' h0 -- DATAB
Equal1
A[3..0]
SEL

4' hD --
B[3..0]
= DATAA
MUX21
OUT0

EQUAL
Y~[1..0] 3' h0 -- DATAB
Equal0
A[3..0]
SEL

4' hE --
B[3..0]
= DATAA
MUX21
OUT0

Equal14
EQUAL 2' h0 -- DATAB

A[3..0]

4' h0 --
B[3..0]
= MUX21

EQUAL
4:16 DECODER (structural)

Decoder_2x4:Dx0
Decoder_2x4:\loop1:3:Dx

en en
Y[3..0] en
X[3..0] X[1..0] Y[3..0]
X[1..0]

Decoder_2x4:\loop1:2:Dx

en
Y[3..0]
X[1..0]

Decoder_2x4:\loop1:1:Dx

en Y[15..0]
Y[3..0]
X[1..0]

Decoder_2x4:\loop1:0:Dx

en
Y[3..0]
X[1..0]

VHDL CODE
2:4 DECODER

library ieee;
use ieee.std_logic_1164.all;

ENTITY Decoder_2x4 is
port ( X:IN std_logic_vector(1 downto 0);
Y:OUT std_logic_vector(3 downto 0);
en: IN std_logic);
END Decoder_2x4;

Architecture Behaviour of Decoder_2x4 is


BEGIN
Y<= "0001" when (X="00" and en='0') else
"0010" when (X="01" and en='0')else
"0100" when (X="10" and en='0')else
"1000" when (X="11" and en='0') else
"0000";
END Behaviour;

4:16 DECODER (behavioral)

library ieee;
use ieee.std_logic_1164.all;

ENTITY Decoder_4x16_b is
port ( X:IN std_logic_vector(3 downto 0);
Y:OUT std_logic_vector(15 downto 0));
END Decoder_4x16_b;
Architecture Behaviour of Decoder_4x16_b is
BEGIN
Y<= "0000000000000001" when X="0000" else
"0000000000000010" when X="0001" else
"0000000000000100" when X="0010" else
"0000000000001000" when X="0011" else
"0000000000010000" when X="0100" else
"0000000000100000" when X="0101" else
"0000000001000000" when X="0110" else
"0000000010000000" when X="0111" else
"0000000100000000" when X="1000" else
"0000001000000000" when X="1001" else
"0000010000000000" when X="1010" else
"0000100000000000" when X="1011" else
"0001000000000000" when X="1100" else
"0010000000000000" when X="1101" else
"0100000000000000" when X="1110" else
"1000000000000000";
END Behaviour;

4:16 DECODER (structural)

library ieee;
use ieee.std_logic_1164.all;

Entity Decoder_4x16 is
port ( X: IN std_logic_vector(3 downto 0);
Y:OUT std_logic_vector(15 downto 0);
en: IN std_logic);
END Decoder_4x16;

Architecture Structure of Decoder_4x16 is


signal s:std_logic_vector(3 downto 0);

component Decoder_2x4 is
port ( X:IN std_logic_vector(1 downto 0);
Y:OUT std_logic_vector(3 downto 0);
en: IN std_logic);
end component;

BEGIN
Dx0: Decoder_2x4 port map (X(3 downto 2),s,en);
loop1: for i in 0 to 3 generate
Dx: Decoder_2x4 port map (X(1 downto 0),Y(3+(i*4) downto 0+(i*4)),not
s(i));
end generate loop1;
END Structure;
TIMING ANALYSIS
4:16 DECODER (behavioral)

4:16 DECODER (structural)


SYNTHESIS REPORT
4:16 DECODER (behavioral)

+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 09:18:24 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Decoder_4x16_b ;
; Top-level Entity Name ; Decoder_4x16_b ;
; Family ; Stratix III ;
; Met timing requirements ; N/A ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 16 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 20 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 11:36:32 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Decoder_4x16 ;
; Top-level Entity Name ; Decoder_4x16 ;
; Family ; Stratix III ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 16 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 21 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 11:36:57 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Decoder_4x16 ;
; Top-level Entity Name ; Decoder_4x16 ;
; Family ; Stratix III ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 16 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 21 / 296 ( 7 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Timing Analyzer Summary
+-------------------------------------------------------------------------+
; Type : Worst-case tpd
; Slack : N/A
; Required Time : None
; Actual Time : 11.315 ns
; From : X[3]
; To : Y[13]
; From Clock : --
; To Clock : --
; Failed Paths : 0

; Type : Total number of failed paths


; Slack :
; Required Time :
; Actual Time :
; From :
; To :
; From Clock :
; To Clock :
; Failed Paths : 0

+-------------------+-----------------------------------------------------+
4:16 DECODER (structural)

+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 11:36:32 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Decoder_4x16 ;
; Top-level Entity Name ; Decoder_4x16 ;
; Family ; Stratix III ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 16 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 21 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 11:36:57 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Decoder_4x16 ;
; Top-level Entity Name ; Decoder_4x16 ;
; Family ; Stratix III ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 16 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 21 / 296 ( 7 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 09:08:08 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Decoder_2x4 ;
; Top-level Entity Name ; Decoder_2x4 ;
; Family ; Stratix II ;
; Met timing requirements ; N/A ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 4 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 7 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Timing Analyzer Summary
+-------------------------------------------------------------------------+
; Type : Worst-case tpd
; Slack : N/A
; Required Time : None
; Actual Time : 11.315 ns
; From : X[3]
; To : Y[13]
; From Clock : --
; To Clock : --
; Failed Paths : 0

; Type : Total number of failed paths


; Slack :
; Required Time :
; Actual Time :
; From :
; To :
; From Clock :
; To Clock :
; Failed Paths : 0

+-------------------+-----------------------------------------------------+

CONCLUSION
The functional analysis of the logic design follows the truth table of the 4:16 Decoder model.
8:3 PRIORITY ENCODER
USING 4:2 ENCODERS

ABSTRACT

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller
number of outputs. The output of a priority encoder is the binary representation of the ordinal
number starting from zero of the most significant input bit. They are often used to control interrupt
requests by acting on the highest priority request.

If two or more inputs are given at the same time, the input having the highest priority will take
precedence.

RTL
8:3 PRIORITY ENCODER (behavioral)

Y~[2..1]
Y~[4..3]
Y~[7..5]
SEL
X[7..0] 0
Y~[10..8]
0 1 DATAA SEL Y~[13..11]
OUT0 DATAA SEL
OUT0
Y~0 2' h3 -- DATAB 2' h0 -- DATAB DATAA SEL
SEL
OUT0 DATAA
OUT0 DATAA
3' h5 -- DATAB 3' h6 -- DATAB
3' h7 --
OUT0 Y[2..0]
DATAB
MUX21 MUX21

MUX21 MUX21
MUX21

flag~6
C
8:3 PRIORITY ENCODER (structural)

VHDL CODE
2:1 MUX

library ieee;
use ieee.std_logic_1164.all;

ENTITY Mux_2to1 is
port (x1,x2,sel:IN std_logic; y:OUT std_logic);
end Mux_2to1;

Architecture behaviour of Mux_2to1 is


begin
process(x1,x2,sel)
begin
if sel='1' then
y<=x2;
else
y<=x1;
end if;
end process;
end behaviour;

4:2 PRIORITY ENCODER

library ieee;
use ieee.std_logic_1164.all;

entity PriorityEncoder_4to2 is
port( x:IN std_logic_vector(3 downto 0);
y:OUT std_logic_vector(1 downto 0);
c:OUT std_logic);
end PriorityEncoder_4to2;

Architecture Behaviour of PriorityEncoder_4to2 is


BEGIN
process(x)
BEGIN
c<=x(3) or x(2) or x(1) or x(0);
if (x(3)='1') then y<="11";
elsif (x(2)='1') then y<="10";
elsif (x(1)='1')then y<="01";
else y<="00";
end if;
END process;
END Behaviour;
8:3 PRIORITY ENCODER (behavioral)

library ieee;
use ieee.std_logic_1164.all;

ENTITY Priority_Encoder_8x3 IS
port (X:IN std_logic_vector(7 downto 0);
Y:OUT std_logic_vector(2 downto 0);
C:OUT std_logic);
END Priority_Encoder_8x3;

Architecture Behaviour of Priority_Encoder_8x3 is


BEGIN
process(X)
Variable flag:std_logic;
BEGIN
flag:='0';
for i in 7 downto 0 loop
flag:=flag OR X(i);
END loop;
C<=flag;
if(X(7)='1') then Y<="111";
elsif(X(6)='1') then Y<="110";
elsif(X(5)='1') then Y<="101";
elsif(X(4)='1') then Y<="100";
elsif(X(3)='1') then Y<="011";
elsif(X(2)='1') then Y<="010";
elsif(X(1)='1') then Y<="001";
else Y<="000";
END if;
END process;
END Behaviour;

8:3 PRIORITY ENCODER (structural)

library ieee;
use ieee.std_logic_1164.all;

ENTITY PE_8x3_S is
port( X:IN std_logic_vector(7 downto 0);
Y:OUT std_logic_vector(2 downto 0);
C:OUT std_logic);
END PE_8x3_S;

Architecture Structure of PE_8x3_S is


Signal s1,s2:std_logic_vector(1 downto 0);
Signal c1,c2:std_logic;

Component PriorityEncoder_4to2 is
port(x:IN std_logic_vector(3 downto 0);
y:OUT std_logic_vector(1 downto 0);
c:OUT std_logic);
End Component;

Component Mux_2to1 is
port (x1,x2,sel:IN std_logic; y:OUT std_logic);
end component;

BEGIN
x1: PriorityEncoder_4to2 port map((X(3),X(2),X(1),X(0)),s1,c1);
x2: PriorityEncoder_4to2 port map((X(7),X(6),X(5),X(4)),s2,c2);
m1: Mux_2to1 port map (s1(0),s2(0),c2,Y(0));
m2: Mux_2to1 port map (s1(1),s2(1),c2,Y(1));
Y(2)<=c2;
C<=c2 or c1;
END Structure;
TIMING ANALYSIS
8:3 PRIORITY ENCODER (behavioral)

8:3 PRIORITY ENCODER (structural)


SYNTHESIS REPORT

8:3 PRIORITY ENCODER (behavioral)

+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 06:53:58 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Priority_Encoder_8x3 ;
; Top-level Entity Name ; Priority_Encoder_8x3 ;
; Family ; Stratix II ;
; Met timing requirements ; Yes ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 6 / 12,480 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 12,480 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 12 / 343 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 419,328 ( 0 % ) ;
; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
; Device ; EP2S15F484C3 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 06:53:38 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Priority_Encoder_8x3 ;
; Top-level Entity Name ; Priority_Encoder_8x3 ;
; Family ; Stratix II ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 6 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 12 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 06:53:47 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Priority_Encoder_8x3 ;
; Top-level Entity Name ; Priority_Encoder_8x3 ;
; Family ; Stratix II ;
; Device ; EP2S15F484C3 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 6 / 12,480 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 12,480 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 12 / 343 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 419,328 ( 0 % ) ;
; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
-----------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 10.997 ns
From : X[5]
To : Y[0]
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0

-----------------------------------------------------------------------------------
8:3 PRIORTY ENCODER (structural)

+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 07:06:49 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; PE_8x3_S ;
; Top-level Entity Name ; PE_8x3_S ;
; Family ; Stratix II ;
; Met timing requirements ; Yes ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 5 / 12,480 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 12,480 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 12 / 343 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 419,328 ( 0 % ) ;
; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
; Device ; EP2S15F484C3 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 07:06:29 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; PE_8x3_S ;
; Top-level Entity Name ; PE_8x3_S ;
; Family ; Stratix II ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 5 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 12 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 07:06:37 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; PE_8x3_S ;
; Top-level Entity Name ; PE_8x3_S ;
; Family ; Stratix II ;
; Device ; EP2S15F484C3 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 5 / 12,480 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 12,480 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 12 / 343 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 419,328 ( 0 % ) ;
; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
+-------------------------------+-----------------------------------------+ --------
------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 10.650 ns
From : X[4]
To : C
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0

-----------------------------------------------------------------------------------

CONCLUSION
The functional analysis of the logic design follows the truth table of the 8:3 Priority Encoder model.
4 BIT CARRY LOOK-AHEAD ADDER

ABSTRACT

A carry look-ahead adder is a type of adder used in digital logic. A carry look-ahead adder improves
speed by reducing the amount of time required to determine carry bits. It can be contrasted with
the simpler, but usually slower, ripple carry adder for which the carry bit is calculated alongside the
sum bit, and each bit must wait until the previous carry has been calculated to begin calculating its
own result and carry bits (see adder for detail on ripple carry adders). The carry look-ahead adder
calculates one or more carry bits before the sum, which reduces the wait time to calculate the result
of the larger value bits.

RTL
p[0] c~11
A[3..0]
B[3..0] c[3]
Sum~7
p[1]
c~7
Sum[3..0]
c~21
p[2]
c~17
c~14
c~22
Cout
g[0] c~18
c~8

g[1]
c~5 c~15

g[2]
c~12
c[2]
Sum~5
p[3]
c~1
c[1]
Sum~3
g[3]

c~4
Sum~1

c~0
Cin
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;

ENTITY CLA is
port( A,B: IN std_logic_vector(3 downto 0);
Cin: IN std_logic;
Sum: OUT std_logic_vector(3 downto 0);
Cout: OUT std_logic);
END CLA;

Architecture Dataflow of CLA is


signal c: std_logic_vector(4 downto 0);
signal g,p: std_logic_vector(3 downto 0);
BEGIN
loop1: For i in 0 to 3 generate
g(i)<=A(i) and B(i);
p(i)<=A(i) or B(i);
end generate loop1;

c(0)<=Cin;
c(1)<=g(0) or (p(0) and Cin);
c(2)<=g(1) or (p(1) and g(0)) or (p(1) and p(0) and Cin);
c(3)<=g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0)) or (p(2) and p(1)
and p(0) and Cin);
c(4)<=g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1))
or (p(3) and p(2) and p(1) and g(0))
or (p(3) and p(2) and p(1) and p(0) and Cin);

Cout<=c(4);
loop2: For i in 0 to 3 generate
Sum(i)<=A(i) XOR B(i) XOR c(i);
end generate loop2;

END Dataflow;
TIMING ANALYSIS

SYNTHESIS REPORT
+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 08:51:25 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; CLA ;
; Top-level Entity Name ; CLA ;
; Family ; Stratix III ;
; Met timing requirements ; Yes ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 6 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 14 / 296 ( 5 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 08:50:48 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; CLA ;
; Top-level Entity Name ; CLA ;
; Family ; Stratix III ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 6 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 14 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 08:51:06 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; CLA ;
; Top-level Entity Name ; CLA ;
; Family ; Stratix III ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 6 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 14 / 296 ( 5 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
-----------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 12.112 ns
From : A[0]
To : Sum[1]
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0

-----------------------------------------------------------------------------------
CONCLUSION
The functional analysis of the logic design follows the truth table of the 4-bit Carry Look Ahead
Adder model. Improved performance was observed with this adder circuit.
8 BIT COMPARATOR
USING 2 BIT COMPARATOR

ABSTRACT

A magnitude comparator is a combinational circuit that compares two numbers A & B to


determine whether:
A > B, or
A = B, or
A<B
Inputs
First n-bit number A
Second n-bit number B
Outputs
3 output signals (GT, EQ, LT), where:
1. GT = 1
IFF A > B
2. EQ = 1
IFF A = B
3. LT = 1
IFF A < B
Note: Exactly One of these 3 outputs equals 1, while the other 2 outputs are 0`s

RTL
8 BIT COMPARATOR (structural)
Comparator_2b:\loop1:0:Comp
Comparator_2b:\loop1:1:Comp
0 eqi
Comparator_2b:\loop1:2:Comp
0 gti eq eqi
Comparator_2b:\loop1:3:Comp
0 lti gt gti eq eqi

p[7..0] p[1..0] lt lti gt gti eq eqi

q[7..0] q[1..0] p[1..0] lt lti gt gti eq eq


q[1..0] p[1..0] lt lti gt gt
q[1..0] p[1..0] lt lt
q[1..0]

8 BIT COMPARATOR (behavioral)

LessThan1
A[7..0]
p[7..0]
q[7..0]
B[7..0]
< lt

LESS_THAN
Equal0
A[7..0]

B[7..0]
= eq

EQUAL
LessThan0
A[7..0]

B[7..0]
< gt

LESS_THAN
VHDL CODE
2 BIT COMPARATOR

library ieee;
use ieee.std_logic_1164.all;

entity Comparator_2b is
port( p,q : IN std_logic_vector(1 downto 0);
gti,eqi,lti : IN std_logic;
gt,eq,lt : OUT std_logic);
end Comparator_2b;

architecture conditional of Comparator_2b is


begin
gt<='1' when (p>q or (p=q and gti='1')) else '0';
eq<='1' when (p=q and (eqi='1' or (gti='0' and eqi='0' and lti='0'))) else
'0';
lt<='1' when (p<q or (p=q and lti='1')) else '0';

end conditional;

8 BIT COMPARATOR (structural)

library ieee;
use ieee.std_logic_1164.all;

ENTITY Comparator_8b is
port( p,q : IN std_logic_vector(7 downto 0);
gt,eq,lt : OUT std_logic);
END Comparator_8b;

Architecture Structure of Comparator_8b is


signal g,e,l: std_logic_vector(4 downto 0);

COMPONENT Comparator_2b is
port( p,q : IN std_logic_vector(1 downto 0);
gti,eqi,lti : IN std_logic;
gt,eq,lt : OUT std_logic);
end component;

BEGIN
g(0)<='0';
e(0)<='0';
l(0)<='0';
loop1: For i in 0 to 3 generate
Comp: Comparator_2b port map(p(1+(i*2) downto 0+(i*2)),q(1+(i*2)
downto 0+(i*2)),
g(i),e(i),l(i),
g(i+1),e(i+1),l(i+1));
end generate loop1;

gt<=g(4);
eq<=e(4);
lt<=l(4);

END Structure;
8 BIT COMPARATOR (behavioral)
library ieee;
use ieee.std_logic_1164.all;
entity Comparator_8b_B is
port( p,q : IN std_logic_vector(7 downto 0);
gt,eq,lt : OUT std_logic);
end Comparator_8b_B;

architecture Behaviour of Comparator_8b_B is


begin
gt<='1' when p>q else '0';
eq<='1' when p=q else '0';
lt<='1' when p<q else '0';

end Behaviour;

TIMING ANALYSIS
8 BIT COMPARATOR (structural)
8 BIT COMPARATOR (behavioral)

SYNTHESIS REPORT
8 BIT COMPARATOR (structural)

+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 12:05:50 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Comparator_8b ;
; Top-level Entity Name ; Comparator_8b ;
; Family ; Stratix III ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 15 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 19 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 12:06:15 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Comparator_8b ;
; Top-level Entity Name ; Comparator_8b ;
; Family ; Stratix III ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 15 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 19 / 296 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 12:06:56 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Comparator_8b ;
; Top-level Entity Name ; Comparator_8b ;
; Family ; Stratix III ;
; Met timing requirements ; Yes ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 15 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 19 / 296 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
-----------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 12.274 ns
From : p[1]
To : lt
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0
8 BIT COMPARATOR (behavioral)
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 12:10:36 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Comparator_8b_B ;
; Top-level Entity Name ; Comparator_8b_B ;
; Family ; Stratix III ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 12 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 19 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 12:10:57 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Comparator_8b_B ;
; Top-level Entity Name ; Comparator_8b_B ;
; Family ; Stratix III ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 12 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 19 / 296 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 12:11:35 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Comparator_8b_B ;
; Top-level Entity Name ; Comparator_8b_B ;
; Family ; Stratix III ;
; Met timing requirements ; Yes ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 12 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 19 / 296 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
-----------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 11.234 ns
From : p[1]
To : lt
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0

-----------------------------------------------------------------------------------

CONCLUSION
The functional analysis of the logic design follows the truth table of the 8 Bit Comparator model.
4 BIT ADDER/SUBTRACTOR
USING 1 BIT ADDER

ABSTRACT
A device for addition/subtraction of two 4-bit binary numbers, formed by connecting n full adders in
cascade, with the carry output of each full adder feeding the carry input of the following full adder.

RTL
Adder_1b:\loop1:3:FAx
loop1~3 a
Cin co Cout
b
B[3..0] s
Adder_1b:\loop1:2:FAx ci

loop1~2 S[3..0]
a
co
b
s
Adder_1b:\loop1:1:FAx ci

loop1~1 a
co
b
s
Adder_1b:\loop1:0:FAx ci

loop1~0 a
co
b
s
ci

A[3..0]

VHDL CODE
1 BIT FULL ADDER

library ieee;
use ieee.std_logic_1164.all;

ENTITY Adder_1b is
port( a,b,ci: IN std_logic;
s,co: OUT std_logic);
END Adder_1b;

ARCHITECTURE Dataflow of Adder_1b is


BEGIN
s<= a xor b xor ci;
co<= (a and b) or ( ci and (a xor b));
END Dataflow;

4 BIT ADDER/SUBTRACTOR

library ieee;
use ieee.std_logic_1164.all;

ENTITY Adder_Subtractor_4b is
port ( A,B : IN std_logic_vector( 3 downto 0);
Cin : IN std_logic;
S : OUT std_logic_vector( 3 downto 0);
Cout: OUT std_logic
);
END Adder_Subtractor_4b;

ARCHITECTURE Structural of Adder_Subtractor_4b is

signal C:std_logic_vector( 4 downto 0);


COMPONENT Adder_1b is
port( a,b,ci: IN std_logic;
s,co: OUT std_logic);
END COMPONENT;
BEGIN
C(0)<=Cin;

loop1: FOR i in 0 to 3 GENERATE


FAx: Adder_1b port map (A(i),(B(i) XOR Cin), C(i) , S(i), C(i+1));
END GENERATE loop1;
Cout<=C(4);
END Structural;
TIMING ANALYSIS
SYNTHESIS REPORT
+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 09:14:11 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Adder_Subtractor_4b ;
; Top-level Entity Name ; Adder_Subtractor_4b ;
; Family ; Stratix III ;
; Met timing requirements ; Yes ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 6 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 14 / 296 ( 5 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 09:13:34 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Adder_Subtractor_4b ;
; Top-level Entity Name ; Adder_Subtractor_4b ;
; Family ; Stratix III ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 6 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 14 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 09:13:51 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Adder_Subtractor_4b ;
; Top-level Entity Name ; Adder_Subtractor_4b ;
; Family ; Stratix III ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 6 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 14 / 296 ( 5 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
-----------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 10.565 ns
From : Cin
To : S[1]
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0

-----------------------------------------------------------------------------------

CONCLUSION
The functional analysis of the logic design follows the truth table of the 4-bit Adder/Subtractor
model.
2 DIGIT DECIMAL ADDER

ABSTRACT

In a binary-coded-decimal (BCD) representation, each decimal digit is represented by four signals,


D[0], D[1], D[2], and D[3]. These are interpreted as a binary number, with D[0] being the least
significant digit, so that the digit 5 is represented by D[3]=0, D[2]=1, D[1]=0, and D[0]=1. Bit
combinations representing values of ten or greater are not valid BCD patterns.

A two-digit decimal number is represented by two sets of four signals: ONES and TENS. A two-digit
decimal adder takes two decimal numbers: A-ONES and A-TENS, and B-ONES and B-TENS (16 bits
of input in total); it produces a two-digit sum, SUM-ONES and SUM-TENS, and a single CARRY-
OUT bit (9 bits total).

RTL
Adder_4_Bit:Add1
Adder_4_Bit:Add2
Cin Cin
Cout 0 Cin Adder_4_Bit:Add3
A1[3..0] A[3..0] Adder_4_Bit:Add4
SUM[3..0] A[3..0]
B1[3..0] B[3..0] t~2 1' h0 --
Cout Cin
Cout 0 Cin
t[0] SUM[3..0] A[3..0]
B[3..0] SUM[3..0] A[3..0]
1' h0 --
B[3..0] t~5 1' h0 --
Cout Cout
t[1] SUM[3..0] Sum2[3..0]
t~0 B[3..0]
1' h0 --

t~3
A2[3..0]
B2[3..0]
Sum1[3..0]

VHDL CODE
HALF ADDER (dataflow)

library ieee;
use ieee.std_logic_1164.all;

entity Half_Adder is
port(a,b:in std_logic;sum,cout:out std_logic);
end Half_Adder;

architecture dataflow of Half_Adder is


begin
sum <= a xor b;
cout <= a and b;
end dataflow;

FULL ADDER (structural)

library ieee;
use ieee.std_logic_1164.all;

entity Full_Adder is
port(A,B,Cin :in std_logic;SUM, COUT:out std_logic);
end Full_Adder;
architecture struct of Full_Adder is

signal c1,c2,c3 : std_logic;


component Half_Adder is
port(a,b: in std_logic;sum,cout:out std_logic);
end component;
begin
x1: Half_Adder port map(A,B,c1,c2);
x2: Half_Adder port map(c1,Cin,SUM,c3);
COUT<= c2 or c3;

end struct;

2 DIGIT DECIMAL ADDER (structural)

library ieee;
use ieee.std_logic_1164.all;

ENTITY Decimal_Adder_2d is
port ( A1,A2,B1,B2: IN std_logic_vector(3 downto 0);
Cin: IN std_logic;
Sum1,Sum2: OUT std_logic_vector(3 downto 0);
Cout: OUT std_logic);
END Decimal_Adder_2d;

Architecture Structure of Decimal_Adder_2d is

signal s1,s2: std_logic_vector(3 downto 0);


signal c: std_logic_vector(4 downto 0);
signal t: std_logic_vector(1 downto 0);

COMPONENT Adder_4_Bit is
port( A,B:IN std_logic_vector(3 downto 0);
Cin:IN std_logic;
SUM:OUT std_logic_vector(3 downto 0);
Cout:OUT std_logic);
END COMPONENT;

BEGIN
c(0)<=Cin;
Add1: Adder_4_Bit port map(A1,B1,c(0),s1,c(1));

t(0)<=c(1) or (s1(3) and s1(1)) or (s1(3) and s1(2));


Add2: Adder_4_Bit port map(s1,('0',t(0),t(0),'0'),'0',Sum1,c(2));

Add3: Adder_4_Bit port map(A2,B2,c(2),s2,c(3));

t(1)<=c(3) or (s2(3) and s2(1)) or (s2(3) and s2(2));


Add4: Adder_4_Bit port map(s2,('0',t(1),t(1),'0'),'0',Sum2,c(4));

Cout<=c(4);
END Structure;
TIMING ANALYSIS

SYNTHESIS REPORT
+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 08:24:28 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Decimal_Adder_2d ;
; Top-level Entity Name ; Decimal_Adder_2d ;
; Family ; Stratix III ;
; Met timing requirements ; Yes ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 21 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 26 / 296 ( 9 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 08:23:52 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Decimal_Adder_2d ;
; Top-level Entity Name ; Decimal_Adder_2d ;
; Family ; Stratix III ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 21 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 26 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 08:24:10 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; Decimal_Adder_2d ;
; Top-level Entity Name ; Decimal_Adder_2d ;
; Family ; Stratix III ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 21 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 26 / 296 ( 9 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
-----------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 13.079 ns
From : B1[1]
To : Sum2[2]
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0

-----------------------------------------------------------------------------------
CONCLUSION
The functional analysis of the logic design follows the truth table of the 2 Digit Decimal Adder
model.
4 BIT BINARY-GRAY & GRAY-BINARY CONVERTER

ABSTRACT

The Gray Code is useful code in digital systems. This code is like binary in that it can have many bits
as and the more the bits, the more possible combinations of output codes.

The only difference between the Gray Code and the regular Binary Code is that the Gray Code
varies only 1 bit from entry to next entry. The conversion between these codes can be done using
exclusive-OR gates.

RTL
BINARY-GRAY CONVERTER (behavioral)
Equal4
A[3..0]
B[3..0]
4' hB --
B[3..0]
=
0
EQUAL 0
Equal5 0 1
1 1
0
0
A[3..0] 1 1 0
G[0]~19 0 1 0
G[0]~17
4' hA --
B[3..0]
= G[0]~16
G[0]~13
0 1
1 1
1
0
1
0
0
G[0]~11 0 1 0
0 G[0]~9 0 1 0 comb~2
EQUAL
Equal6 0 G[0]~8 1 1 0
1 1 0 G[0]~7 1 1
A[3..0] 1 1 0 G[0]~5 0 1
1 1 0 G[0]~4
G[2]~20 G[0]~3
4' h9 --
B[3..0]
= G[2]~24
G[2]~28
1 1
1 1
1
0
1
0
0
G[0]~1
G[2]~31 1 1 0
comb~4 comb~1
G[2]~40 0 1 0
EQUAL
Equal7 G[2]~41 0 1 0
G[2]~42 0 1 G[0]$latch
A[3..0] G[2]~43 0 1
G[2]~44 PRE
G[2]~45
4' h8 --
B[3..0]
= G[2]~46 comb~6 0
0
D
ENA
Q Equal7_OUT
CLR
EQUAL
G[2]$latch
Equal8 PRE
A[3..0] 0 D Q

4' h7 --
B[3..0]
= 0 ENA
CLR G[3..0]

EQUAL
Equal9
Equal8_OUT
A[3..0]

4' h6 --
B[3..0]
= Equal9_OUT
Equal6_OUT
EQUAL
Equal10
A[3..0]

4' h5 --
B[3..0]
= Equal10_OUT

EQUAL
Equal11
A[3..0]

4' h4 --
B[3..0]
= Equal11_OUT

EQUAL
Equal12
A[3..0]

4' h3 --
B[3..0]
= Equal12_OUT

EQUAL
Equal13
A[3..0]

4' h2 --
B[3..0]
= Equal13_OUT

EQUAL
Equal14
A[3..0]

4' h1 --
B[3..0]
=
EQUAL
Equal15
A[3..0] G[3]~58
4' h0 --
B[3..0]
=
G[3]~58_OUT0
EQUAL
Equal3
A[3..0]

4' hC --
B[3..0]
= Equal3_OUT

Equal2
EQUAL
A[3..0]

4' hD --
B[3..0]
= Equal2_OUT
Equal4_OUT
EQUAL
Equal14_OUT
Equal1
Equal15_OUT
A[3..0]

4' hE --
B[3..0]
= Equal1_OUT

EQUAL
Equal0
A[3..0]

4' hF --
B[3..0]
=
G[1]~15_OUT0 EQUAL 0
G[1]~21_OUT0
G[0]~22_OUT0 1 1

G[1]~21
comb~5
comb~5_OUT0
G[3]~59_OUT0

comb~3
comb~3_OUT0
G[1]~39_OUT0

comb~0
comb~0_OUT0

G[3]$latch_OUT0
G[1]$latch_OUT0
GRAY-BINARY CONVERTER (behavioral)

Equal15
A[3..0]
G[3..0]
4' h0 --
B[3..0]
=
EQUAL
Equal14
A[3..0]

4' h1 --
B[3..0]
=
B[3]~58
EQUAL comb~5
Equal13
A[3..0]

4' h3 --
B[3..0]
= 0 0
0 0 comb~7
0 1 0 1
0 1 0 1
EQUAL
Equal12 B[3]~53 B[3]~57 B[3]$latch
A[3..0] B[3]~55 B[3]~59
PRE

4' h2 --
B[3..0]
= 0
0
1
0
0 0
comb~3 0
0
D
ENA
Q

1 1 0 CLR B[3..0]
1 1 0 1
EQUAL
Equal11 B[1]~35 0 1
B[1]~36
A[3..0] B[1]~37 B[1]~38 comb~0
B[1]~39
4' h6 --
B[3..0]
= 0
0
1
0
B[1]$latch
0 1 0
0 PRE
EQUAL
Equal10 B[3]~49 1 1 0 comb~2 0 D Q
B[3]~51 0 1 0
A[3..0] 1 1 0 ENA
B[0]~6 0 1 CLR
B[0]~5
4' h7 --
B[3..0]
= 1
0
1
0 B[0]~3
B[0]~2
0 1 comb~1
EQUAL
Equal9 B[0]~9
B[0]~7
A[3..0] comb~4 B[0]$latch

4' h5 --
B[3..0]
= 0 0 D
PRE
Q

0 1 0 ENA
EQUAL CLR
Equal8 B[2]~46 comb~6
A[3..0]
B[2]$latch
4' h4 --
B[3..0]
= PRE
0 D Q
EQUAL ENA
Equal7 0
CLR
A[3..0]

4' hC --
B[3..0]
= 0
0
1 1 B[2]~42_OUT0
1 1
EQUAL
Equal6 B[2]~41
B[2]~42
A[3..0]

4' hD --
B[3..0]
= Equal6_OUT

EQUAL
Equal5
A[3..0]

4' hF --
B[3..0]
= Equal5_OUT

EQUAL
Equal4
A[3..0]

4' hE --
B[3..0]
= Equal4_OUT

EQUAL
Equal3
A[3..0]

4' hA --
B[3..0]
= Equal3_OUT

EQUAL
Equal2
A[3..0]

4' hB --
B[3..0]
= Equal2_OUT

EQUAL
Equal1
A[3..0]

4' h9 --
B[3..0]
= Equal1_OUT

EQUAL
Equal0
A[3..0]

4' h8 --
B[3..0]
=
B[1]~0_OUT0 EQUAL 0

B[2]~45_OUT0 0 1

B[0]~10_OUT0
B[1]~34
B[3]~47_OUT0
B[2]~40_OUT0
Equal14_OUT
Equal13_OUT
Equal12_OUT

Equal9_OUT
Equal8_OUT
Equal7_OUT

GRAY-BINARY / BINARY-GRAY CONVERTER (structural)

Y~3 Y~4
Y~2
X[3..0] 0 0
1 1
Y[3..0]
Y~0 Y~5 Y~6

Y~1

mode
VHDL CODE
BINARY-GRAY CONVERTER (behavioral)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity B_G_Converter_b is

Port (B: IN std_logic_vector(3 downto 0);


G: OUT std_logic_vector(3 downto 0));

end B_G_Converter_b;

architecture Behavioral of B_G_Converter_b is


begin
G <="0000" when B="0000" else
"0001" when B="0001" else
"0011" when B="0010" else
"0010" when B="0011" else
"0110" when B="0100" else
"0111" when B="0101" else
"0101" when B="0110" else
"0100" when B="0111" else
"1100" when B="1000" else
"1101" when B="1001" else
"1111" when B="1010" else
"1110" when B="1011" else
"1010" when B="1100" else
"1011" when B="1101" else
"1001" when B="1110" else
"1000" when B="1111";
end Behavioral;

GRAY-BINARY CONVERTER (behavioral)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity G_B_Converter_b is

Port (G: IN std_logic_vector(3 downto 0);


B: OUT std_logic_vector(3 downto 0));

end G_B_Converter_b;

architecture Behavioral of G_B_Converter_b is


begin
B <="0000" when G="0000" else
"0001" when G="0001" else
"0010" when G="0011" else
"0011" when G="0010" else
"0100" when G="0110" else
"0101" when G="0111" else
"0110" when G="0101" else
"0111" when G="0100" else
"1000" when G="1100" else
"1001" when G="1101" else
"1010" when G="1111" else
"1011" when G="1110" else
"1100" when G="1010" else
"1101" when G="1011" else
"1110" when G="1001" else
"1111" when G="1000";
end Behavioral;

GRAY-BINARY / BINARY-GRAY CONVERTER (structural)

library ieee;
use ieee.std_logic_1164.all;

ENTITY B_G_Converter is
port(X: IN std_logic_vector(3 downto 0);
mode: IN std_logic;
Y: BUFFER std_logic_vector(3 downto 0));
END B_G_Converter;

Architecture Behaviour of B_G_Converter is


BEGIN
process(mode,X)
BEGIN
Y(3)<= X(3);
--Binary to Gray
if mode='0' then
loop1: For i in 2 downto 0 loop
Y(i)<=X(i+1) XOR X(i);
end loop loop1;

--Gray to Binary
else
loop2: For i in 2 downto 0 loop
Y(i)<=Y(i+1) XOR X(i);
end loop loop2;
end if;
end process;

END Behaviour;

TIMING ANALYSIS
BINARY-GRAY CONVERTER (behavioral)
GRAY-BINARY CONVERTER (behavioral)
GRAY-BINARY / BINARY-GRAY CONVERTER (structural)

SYNTHESIS REPORT
BINARY-GRAY CONVERTER (behavioral)

+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 07:34:31 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; B_G_Converter_b ;
; Top-level Entity Name ; B_G_Converter_b ;
; Family ; Stratix III ;
; Met timing requirements ; Yes ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 3 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 8 / 296 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 07:33:56 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; B_G_Converter_b ;
; Top-level Entity Name ; B_G_Converter_b ;
; Family ; Stratix III ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 3 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 8 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 07:34:13 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; B_G_Converter_b ;
; Top-level Entity Name ; B_G_Converter_b ;
; Family ; Stratix III ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 3 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 8 / 296 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
-----------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 9.917 ns
From : B[1]
To : G[0]
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0

-----------------------------------------------------------------------------------
GRAY-BINARY CONVERTER (behavioral)

+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 07:41:37 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; G_B_Converter_b ;
; Top-level Entity Name ; G_B_Converter_b ;
; Family ; Stratix III ;
; Met timing requirements ; Yes ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 3 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 8 / 296 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Aug 31 23:27:26 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; G_B_Converter_b ;
; Top-level Entity Name ; G_B_Converter_b ;
; Family ; Stratix III ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 3 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 8 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Tue Aug 31 23:27:42 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; G_B_Converter_b ;
; Top-level Entity Name ; G_B_Converter_b ;
; Family ; Stratix III ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 3 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 8 / 296 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
-----------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 9.148 ns
From : G[3]
To : B[1]
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0

-----------------------------------------------------------------------------------

GRAY-BINARY / BINARY-GRAY CONVERTER (structural)

+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------+
; Flow Status ; Successful - Thu Sep 02 08:12:47 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; B_G_Converter ;
; Top-level Entity Name ; B_G_Converter ;
; Family ; Stratix III ;
; Met timing requirements ; Yes ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 3 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 9 / 296 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 08:12:08 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; B_G_Converter ;
; Top-level Entity Name ; B_G_Converter ;
; Family ; Stratix III ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 3 ;
; Memory ALUTs ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 9 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; DSP block 18-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-------------------------------+-----------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu Sep 02 08:12:28 2010 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
; Revision Name ; B_G_Converter ;
; Top-level Entity Name ; B_G_Converter ;
; Family ; Stratix III ;
; Device ; EP3SL50F484C2 ;
; Timing Models ; Final ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 3 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 9 / 296 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 1,880,064 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 216 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------+
-----------------------------------------------------------------------------------
Timing Analyzer Summary
-----------------------------------------------------------------------------------

Type : Worst-case tpd


Slack : N/A
Required Time : None
Actual Time : 12.964 ns
From : X[3]
To : Y[0]
From Clock : --
To Clock : --
Failed Paths : 0

Type : Total number of failed paths


Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0

-----------------------------------------------------------------------------------
CONCLUSION
The functional analysis of the logic design follows the truth table of the Binary to Gray model for
both Behavioral and Structural models.
8 BIT BARREL SHIFT REGISTER
USING 4:1 MUX

ABSTRACT

RTL

VHDL CODE

TIMING ANALYSIS

SYNTHESIS REPORT

CONCLUSION