c


 















 


 
 c


c
 stands for cHSIC (Very High Speed Integrated Circuits) ardware
escription anguage. In
the mid-1980͛s the U.S. Department of Defense and the IEEE sponsored the development of
this hardware description language with the goal to develop very high-speed integrated circuit.
It has become now one of industry͛s standard languages used to describe digital systems. The
other widely used hardware description language is Verilog. Both are powerful languages that
allow you to describe and simulate complex digital systems. A third HDL language is ABEL
(Advanced Boolean Equation Language) which was specifically designed for Programmable
Logic Devices (PLD). ABEL is less powerful than the other two languages and is less popular in
industry. This tutorial deals with VHDL, as described by the IEEE standard 1076-1993.

Although these languages look similar as conventional programming languages, there are some
important differences. A hardware description language is inherently parallel, i.e. commands,
which correspond to logic gates, are executed (computed) in parallel, as soon as a new input
arrives. A HDL program mimics the behavior of a physical, usually digital, system. It also allows
incorporation of timing specifications (gate delays) as well as to describe a system as an
interconnection of different components.

VHDL allows one to describe a digital system at the structural or the behavioral level. The behavioral
level can be further divided into two kinds of styles:
  and  !. The dataflow
representation describes how data moves through the system. This is typically done in terms of data
flow between registers (Register Transfer level). The data flow model makes use of concurrent
statements that are executed in parallel as soon as data arrives at the input. On the other hand,
sequential statements are executed in the sequence that they are specified. VHDL allows both
concurrent and sequential signal assignments that will determine the manner in which they are
executed. Examples of both representations will be given later.VHDL is commonly used to write text
models that describe a logic circuit. Such a model is processed by a synthesis program, only if it
is part of the logic design. A simulation program is used to test the logic design using simulation
models to represent the logic circuits that interface to the design. This collection of simulation
models is commonly called a R
R .

VHDL has file input and output capabilities, and can be used as a general-purpose language for
text processing, but files are more commonly used by a simulation testbench for stimulus or
verification data. There are some VHDL compilers which build executable binaries. In this case,
it might be possible to use VHDL to write a R
R  to verify the functionality of the design
using files on the host computer to define stimuli, to interact with the user, and to compare
results with those expected. However, most designers leave this job to the simulator.

VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (for FPGA
implementation such as Xilinx ISE, Altera Quartus, or Synopsys Synplify) to produce the
RTLschematic of the desired circuit. After that, the generated schematic can be verified using
simulation software which shows the waveforms of inputs and outputs of the circuit after
generating the appropriate testbench. To generate an appropriate testbench for a particular
circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a
loop process or an iterative statement is required.

The key advantage of VHDL when used for systems design is that it allows the behavior of the
required system to be described (modeled) and verified (simulated) before synthesis tools
translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system (many parts, each
with its own sub-behaviour, working together at the same time). VHDL is a Dataflow language,
unlike procedural computing languages such as BASIC, C, and assembly.

VHDL is a specific type of hardware description language or HDL. There are many other
examples of HDLs but the other one commonly used is called Verilog. The actual name VHDL is
a acronym that stands for "VHSIC Hardware Description Language". This article contains
information on the rudimentary topics that can be considered necessary to getting started with
VHDL. Additionally there are code examples to illustrate the concepts covered more clearly.

VHDL is a programming language, much like C++, it has its own syntax and semantics. The
big difference from what is considered a traditional programing language is that instead of
describing what instructions a processor will execute, it describes how circuits should be
organized. As it is emulating real hardware it is inherently parallel and also treats timing as
important. This language is a commonly used in the design of field-programmable gate
arrays(FPGA)and application specific integrated circuits(ASIC). What hardware description
languages provide is a way to run simulations, check the logic of the code, and something called
logic synthesis. Logic synthesis is simply the translation of the language in to a physical circuit
implementation. This allows for a much easier and less error prone hardware development
process.
















 " #$%

&'( )'*(*+*)'),
----"-
.


 entity gate is entity gate_tb is
 port(x,y:in BIT; end entity;
 outa,outb,outc,outd,oute,outf:out BIT); architecture gate_arch_tb of gate_tb is
 end entity; component gate is
 architecture gate_arch of gate is port(x,y:in BIT;
 begin outa,outb,outc,outd,oute,outf:out BIT);
 outa<=x and y; end component;
 outb<=x or y; signal in1,in2,o1,o2,o3,o4,o5,o6:BIT;
 outc<=x xor y; begin
 outd<=x nor y; inst:gate port
 oute<= not x; map(in1,in2,o1,o2,o3,o4,o5,o6);
 outf<=x nand Y; process
 end gate_arch; begin
 in1<='0';
 in2<='0';
 wait for 100 ns;

 in1<='0';
 in2<='1';
 wait for 100 ns;

 in1<='1';
 in2<='0';
 wait for 100 ns;

 in1<='1';
 in2<='1';
 wait for 100 ns;
 end process;
 end gate_arch_tb;






 






 " #$/

&'( 
0 1(*)+'0 *(*

 entitygate_four is entitygate_four_tb is
port(x,y:inBIT_vector(0 to 3); end entity;

outa:outBIT_vector(0 to 3)); architecturearch_gate_four_tb of gate_four_tb is
 end entity; componentgate_four is
architecturearch_gate_four of gate_four is port(x,y:inBIT_vector(0 to 3);
 begin outa:outBIT_vector(0 to 3));
outa(0)<=x(0) and y(0); end component;

outa(1)<=x(1) and y(1); signal in1,in2,o1:BIT_vector(0 to 3);
 outa(2)<=x(2) and y(2); begin
outa(3)<=x(3) and y(3); inst:gate_four port
 endarch_gate_four; map(in1,in2,o1);
process

begin
 in1(0)<='0';
in1(1)<='0';
 in1(2)<='1';
in1(3)<='1';

in2(0)<='0';
 in2(1)<='1';
in2(2)<='0';
 in2(3)<='1';
wait for 100 ns;

end process;
 endarch_gate_four_tb;


 " #$2

&'( )'*(*33'$

33'

 entityhalfadder is entityhalfadder_tb is
port(x,y:in bit; end entity;

sum,carry:out bit);
 end entity; architecturearch_halfadder_tb of halfadder_tb is
componenthalfadder is
 architecturearch_halfadder of halfadder is port(x,y:in bit;
 begin sum,carry:out bit);
sum<=x xor y; end component;
 carry<=x and y;
endarch_halfadder; signal in1,in2,sum,carry:bit;

begin
 inst:halfadder port map(in1,in2,sum,carry);
process
 begin
in1<='0';

in2<='0';

wait for 100 ns;

in1<='0';

in2<='1';

wait for 100 ns;

in1<='1';


 in2<='0';

 wait for 100 ns;

 in1<='1';
in2<='1';

wait for 100 ns;


 end process;
endarch_halfadder_tb;




 " #$

!1)*!
*33'*)1 33'

entityfulladder is  entityfulladder_tb is
port(sum, carry, z :in bit; end entity;
sum0,carry0:out bit); 
end entity; architecturearch_fulladder_tb of fulladder_tb is


architecturearch_fulladder of fulladder is  componentfulladder is

port(z,sum,carry:in bit;
componenthalfadder is  sum0,carry0:out bit);
port(x,y :in bit; end component;

sum,carry:out bit);
end component;  signal in1,in2,in3,sum0,carry0 :bit;
begin
 inst:fulladder port map(in1,in2,in3,sum0,carry0);
begin  process
sum0<=sum xor z; begin
carry0<=(sum and z) or carry;  in1<='0';
endarch_fulladder; in2<='0';


 wait for 100 ns;

 in1<='0';
in2<='1';


 wait for 100 ns;

 in1<='1';


in2<='0';

wait for 100 ns;
 in1<='1';
in2<='1';


 wait for 100 ns;

 end process;
endarch_fulladder_tb;



 


 " #$4

!1)*!0 (

entity compare is signalina,inb: bit_vector(3 downto 0);

port(a,b: in bit_vector(3 downto 0); signal of1,of2,of3: bit;
f1,f2,f3: out bit); begin
end entity; inst: compare port map(ina,inb,of1,of2,of3);
process
architecturearch_compare of compare is begin
begin
process(a,b) ina<="0000";
begin inb<="0000";

if(a>b) then wait for 100 ns;

f1<='0';
f2<='0'; ina<="1111";
f3<='1'; inb<="1111";

elsif(a<b) then wait for 100 ns;

f1<='1';
f2<='0'; ina<="0101";
f3<='0'; inb<="1010";

else wait for 100 ns;

f1<='0';
f2<='1'; ina<="1010";
f3<='0'; inb<="1011";
end if;
end process; wait for 100 ns;
endarch_compare;
ina<="1011";
inb<="1010";
 0 
wait for 100 ns;
entitycompare_tb is
end entity;
ina<="0010";
inb<="0011";
architecturearch_compare_tb of compare_tb is

wait for 100 ns;

end process;
component compare is
endarch_compare_tb;
port(a,b: in bit_vector(3 downto 0);
f1,f2,f3: out bit);
end component;

 " #$

!1)*!2"
'!3'

entity dec38 is wait for 100 ns;

port( a: in bit_vector(2 downto 0); inp<="000";
b: out bit_vector(7 downto 0));  wait for 100 ns;
end entity; 
inp<="001";
architecture arch_dec38 of dec38 is  wait for 100 ns;

begin  inp<="010";
b(0)<= (not a(2))and (not a(1)) and (not a(0));  wait for 100 ns;
b(1)<= (not a(2))and (not a(1)) and (a(0));
b(2)<= (not a(2))and (a(1)) and (not a(0));  inp<="011";
b(3)<= (not a(2))and (a(1)) and (a(0)); wait for 100 ns;

b(4)<= (a(2))and (not a(1)) and (not a(0));
b(5)<= (a(2))and (not a(1)) and (a(0));  inp<="100";
b(6)<= (a(2))and (a(1)) and (not a(0)); wait for 100 ns;
b(7)<= (a(2))and (a(1)) and (a(0)); 
inp<="101";

end arch_dec38; wait for 100 ns;

inp<="110";
 0   wait for 100 ns;
entity dec38_tb is 
end entity; inp<="111";
 wait for 100 ns;
architecture arch_dec38_tb of dec38_tb is
 inp<="101";
component dec38 is wait for 100 ns;

port( a: in bit_vector(2 downto 0);
b: out bit_vector(7 downto 0));  end process;
end component; end arch_dec38_tb;

signalinp: bit_vector(2 downto 0);
signaloutp:bit_vector(7 downto 0); 

begin 


inst: dec38 port map(inp,outp);
process 
begin


 " #$5

!1)*!
* *6!


entity subs is inx<='0';
port(x,y,bin: in bit;  iny<='0';
diff,bout: out bit); inbin<='0'; -- should be odiff-> 0, obout-> 0
end entity;  wait for 100 ns;

architecturearch_subs of subs is  inx<='0';

begin iny<='1';

-- logic relation for output pins inbin<='0'; -- should be odiff-> 1, obout-> 1
diff<= x xor y xor bin;  wait for 100 ns;
bout<= ((not x)and y) or (y and (not(x xor y)));
endarch_subs;  inx<='1';
iny<='0';
 inbin<='1'; -- should be odiff-> 0, obout-> 0
 0 
wait for 100 ns;

entitysubs_tb is
end entity;  inx<='0';
iny<='1';
architecturearch_subs_tb of subs_tb is  inbin<='1'; -- should be odiff-> 0, obout-> 1
wait for 100 ns;

component subs is
port(x,y,bin: in bit; inx<='1';

diff,bout: out bit); iny<='0';
end component;  inbin<='0'; -- should be odiff-> 1, obout-> 0
wait for 100 ns;

signalinx,iny,inbin,odiff,obout: bit;
begin inx<='1';
 iny<='1';
inst: subs port map(inx,iny,inbin,odiff,obout);
process inbin<='1'; -- should be odiff-> 1, obout-> 1

begin wait for 100 ns;

end process;
 endarch_subs_tb;


 " #$

!1)*!
-1378
(
(


(
(  clk_process:process
entitydff is begin
 clk<='0';
port (d,clk: in bit;
q: out bit); wait for clk_period/2;

end entity; clk<='1';
 wait for clk_period/2;
architecturearch_dff of dff is end process;

begin
process(clk) stim_process:process

begin begin
if(clk'event and clk='1') then 
q <= d; d1<='0';
end if;  wait for clk_period*2;
end process;
 d1<='1';
endarch_dff;
wait for clk_period*2;

 0 
 d1<='0';
entitydff_tb is
wait for clk_period*2;
end entity;

d1<='1';
architecturearch_dff_tb of dff_tb is  wait for clk_period*2;

componentdff is 
end process;
port (d,clk: in bit;
 endarch_dff_tb;
q: out bit);
end component;

signal d1,clk,q1: bit; 
constantclk_period:time:=50 ns;

begin
inst: dff port map (d1,clk,q1); 


 





(
(


 " #$9

!1)*!:0 ')'

Include dff.vhdl in the workspace.

entity shift8 is begin

port(dd,clka: in bit; inst: shift8 port map(inp,clk,outp);
oo: out bit); clk_process:process
end shift8; begin
architecture arch_shift8 of shift8 is  clk<='0';
signal output: bit_vector(6 downto wait for clk_period/2;
0):="0000000";  clk<='1';
componentdff is wait for clk_period/2;

port (d,clk: in bit; end process;
q: out bit);  stim_process:process
end component; begin
begin  inp<='1';
d0: dff port map(dd,clka,output(0)); wait for clk_period;
d1: dff port map(output(0),clka,output(1));  inp<='0';
d2: dff port map(output(1),clka,output(2)); wait for clk_period;

d3: dff port map(output(2),clka,output(3)); inp<='1';
d4: dff port map(output(3),clka,output(4));  wait for clk_period;
d5: dff port map(output(4),clka,output(5)); inp<='0';
d6: dff port map(output(5),clka,output(6));  wait for clk_period;
d7: dff port map(output(6),clka,oo); inp<='1';
end arch_shift8;  wait for clk_period;
 0  inp<='0';

entity shift8_tb is wait for clk_period;
end entity; 
inp<='1';
architecture arch_shift8_tb of shift8_tb is
 wait for clk_period;
component shift8 is 
port(dd,clka: in bit; end process;
oo: out bit); end arch_shift8_tb;

end component;
signaloutp,inp,clk: bit; 
constantclk_period: time:= 50 ns;