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used to raise the source voltage to (1 - a)V, thereby resulting in a This letter describes a new approach to the implementation of
gate-to-source voltage of Vo, = 0.5 V, +0.5al/, = 0.5V, +0.5Vns. high-speed A/D and D/A conversion which achieves an absolute
Thus as required by (6) for linearization, l/2 Vi,, is fed back to linearity which is independent of the matching accuracy of the
control Vos. The resulting input resistance is passive components used to implement the converter. This is
achieved by the use of a modified form of the algorithmic
-2 V =2=-R
av 1
converter in which the reference voltage is circulated around the
R1N- I,, DS
arDS a
loop as well as the signal, thereby canceling the gain error in the
while the input voltage is loop, in contrast to previously described approaches [2]. Experi-
1 mental fully differential CMOS prototype of this approach is
v, = ; vD, (11) currently being fabricated. Experimental results from this proto-
type will be reported in a later publication.
where a < 1. The smaller a, the wider becomes the dynamic range
for any prescribed amount of distortion that is deemed accept- II. CYCLIC A/D CONVERSION
able. In Fig. 6, the experimentally obtained curves for a = 0.1 are
The technique described in this paper is a modification of the
given. When compared to Fig. 2 or Fig. 3, these curves show
“cyclic” or “algorithmic” conversion technique [3]. The technique
remarkable linearity even for large values of ] V,,l.
described here is an approach to making an MOS implementa-
tion of such a converter which displays a differential and integral
REFERENCES linearity that is independent of the capacitor ratios within the
111 A. S. Sedra and K. C. Smith, Microelectronic Circuits. New York: Holt, converter. Traditional cyclic or algorithmic conversion involves
Rinehart, and Winston, 1982, p. 257. comparison, reference subtraction if applicable, and multiplica-
121 H. P. Von Ow, “Reducing distortion in controlled attenuators using tion of the result by a factor of two. The first step in the process
FET.” Proc. IEEE. pp. 1718-1719, Oct. 1968.
[31 M. Banu and Y. Tsividis. “Fullv inteerated active RC filters in MOS is the decision as to whether the signal is in the upper or lower
technology,” 1983 Dig. Tech. Pup&, 1683 IEEE Int. Solid-State Circuits half of the full range. If the signal is in the upper range, the
Conf. pp. 244-245, Univ. of Pennsylvania, Philadelphia, PA, 1983.
141 J. L. Huertas. J. I. Acha, and A. Gage, “Design of general voltage- or reference is subtracted from the signal and the difference is
current-controlled elements and their applications to the synthesis of doubled. The most significant bit of the digital output is set to
nonlinear networks,” IEEE Trans. Circuits Sysr., vol. CAS-27, pp. 92-103, one. If in the lower half, the input signal is simply doubled and
Feb. 1980.
the most significant bit is set to zero. In the next cycle, the
remainder from the previous cycle is used as the input and the
process is repeated. Following the procedure, the signal can be
encoded into a 1Zbit digital output in 12 iterations.
Ratio Independent Cyclic A/D and D/A Conversion In the D/A operation the least significant bit is decoded first.
Using a Recirculating Reference Approach The reference voltage is added depending on the digital input
code and the sum is divided by two each time. At the end of 12
CHENG-CHUNG SHIH, PING-WA1 LI, AND PAUL GRAY
cycles, the analog output is derived from the digital code. The
principal sources of error in these converters is offsets in the loop
Abstract -In this paper, a new method is described which uses switched
capacitor techniques to implement cyclic A/D and D/A converters. By and a loop gain which is not precisely two or one half. If the loop
periodically modifying the reference voltage to compensate for the non-ideal gain is not precisely two or one half, both integral and differen-
signal transfer loop gain, it is possible in principle to build analog-digital tial nonlinearity is introduced into the converter transfer char-
(A/D) and digital-analog (D/A) converters whose linearity is independent acteristic.
of component ratios and which occupy only a small die area. These The switched-capacitor implementation of the cyclic conver-
converters require two moderate-gain MOS operational amplifiers, one sion requires an amplifier with gain of two, a sample and hold
comparator, and a few capacitors. circuit and a comparator. The basic structure of the converter is
shown in Fig. 1. An operation of sampling and transferring the
I. INTRODUCTION
signal twice will result in multiplication of the signal by a factor
Previously described approaches to digital-analog (D/A) and of 2 Cl/C2. If Cl and C2 are equal, this will give a gain of two.
successive-approximation analog-digital (A/D) conversion have However, deviations from equal values in Cl and C2 will result in
relied on circuit techniques which require the matching of on-chip conversion errors. Taking into account of the capacitor ratio
precision passive components to an accuracy comparable with the inaccuracy and other high order errors existing in the loop, the
integral nonlinearity required in the converter. R-2R ladders, loop transfer equation is
resistor strings, and capacitor array DAC’s fall into this category.
The realization of the required matching has typically required T(x)=2x-t 2 E,x’
laser trimming or other forms of trimming in order to achieve i=O
nonlinearity smaller than 0.2 percent. Recently, a new technique
where E,, is the dc offset, E, is the loop gain error due to
has been described which allows the automatic calibration of a
capacitor mismatch, etc., and E,, E3 are the other high-order
capacitor array-based A/D converter. While very promising, this
distortions. These deviations result in both integral and differen-
approach requires considerable complexity in implementation [l].
tial nonlinearity.
Manuscript received May 25, 1983. This work was supported by the Na- III. REFERENCE REFRESH PRINCIPLE
tional Science Foundation under Grant ECS-8023872, State of California
MICRO program, Racal-Vadic Corporation, Fairchild Semiconductor, and In order to remove the gain errors in the loop, it is necessary to
GTE-Lenkurt Corporation.
The authors are with the Department of Electrical Engineering and Com- use a switching sequence which removes the dependence of the
puter Science, University of California, Berkeley, CA 94720. effective gain factor on capacitor ratios. It can be recognized that
A
-Vin -
A
-vret -
(4 (b)
Fig. 2. D/A with 10 percent gain error. (a) No reference refreshing integral
nonlinearity = l/4 LSB, differential nonlinearity = l/2 LSB. (b) With refer-
ence refreshing integral nonlinearity = 0 LSB, differential nonlinearity = 0
LSB.
2.250
Fig. 1. Fully differential switched-capacitor implementation of the converter.
It is, then, easy to verify that the cyclic convolution output, { y,, },
can be obtained in terms of { xn } and {h, } from the coefficients
REFERENCES of Y(z) polynomial given by
[l] H.-S. Lee and D. A. Hodges, “Self-calibration technique for A/D con-
verters,” IEEE Trans. Circuits Syst., vol. CAS-30, pp. 188-190, Mar. 1983. Y(z) = X(z)H(z)modP(z)
[2] C. C. Lee, “A switched-capacitor A/D converter that is insensitive to (4
capacitor ratios,” presented at the Dig. Papers, 1983 International Symp.
Circuits and Systems, Newport Beach, California, May, 1983.
[3] R. H. McCharles, “Charles circuits for analog LSI,” IEEE Trans. Circuits
.Sya., vol. CAS-25, pp. 490-497, July 1978. Manuscript received May 12, 1979. This work was supported by National
[4] R. C. Yen and P. R. Gray, “A MOS switched-capacitor instrumentation Sciences and Engineering Research Council of Canada under Grant A-7739.
amplifier,” IEEE J. Solid-State Circuits, vol. SC-17. pp. 1008-1013, Dec. The authors are with the Department of Electrical Engineering, Concordia
1982. University. Montreal, P.Q., H3G lM8 Canada.