172 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-30, NO.
10, OCTOBER 1983
used to raise the source voltage to (1 - a)V, thereby resulting in a
gate-to-source voltage of Vo, = 0.5 V, +0.5al/, = 0.5V, +0.5Vns.
Thus as required by (6) for linearization, l/2 Vi,, is fed back to
control Vos. The resulting input resistance is
-2 V =2=-R
av 1
R1N- I,, DS
arDS a
while the input voltage is
1 mental fully differential CMOS prototype of this approach is
v, = ; vD, (11)
where a < 1. The smaller a, the wider becomes the dynamic range
for any prescribed amount of distortion that is deemed accept-
able. In Fig. 6, the experimentally obtained curves for a = 0.1 are
given. When compared to Fig. 2 or Fig. 3, these curves show
remarkable linearity even for large values of ] V,,l.
REFERENCES
111 A. S. Sedra and K. C. Smith, Microelectronic Circuits. New York: Holt,
Rinehart, and Winston, 1982, p. 257.
121 H. P. Von Ow, “Reducing distortion in controlled attenuators using
FET.” Proc. IEEE. pp. 1718-1719, Oct. 1968.
[31 M. Banu and Y. Tsividis. “Fullv inteerated active RC filters in MOS
technology,” 1983 Dig. Tech. Pup&, 1683 IEEE Int. Solid-State Circuits
Conf. pp. 244-245, Univ. of Pennsylvania, Philadelphia, PA, 1983.
141 J. L. Huertas. J. I. Acha, and A. Gage, “Design of general voltage- or
current-controlled elements and their applications to the synthesis of
nonlinear networks,” IEEE Trans. Circuits Sysr., vol. CAS-27, pp. 92-103,
Feb. 1980.
Ratio Independent Cyclic A/D and D/A Conversion
Using a Recirculating Reference Approach
CHENG-CHUNG SHIH, PING-WA1 LI, AND PAUL GRAY
Abstract -In this paper, a new method is described which uses switched
capacitor techniques to implement cyclic A/D and D/A converters. By
periodically modifying the reference voltage to compensate for the non-ideal
signal transfer loop gain, it is possible in principle to build analog-digital
(A/D) and digital-analog (D/A) converters whose linearity is independent
of component ratios and which occupy only a small die area. These
converters require two moderate-gain MOS operational amplifiers, one
comparator, and a few capacitors.
I. INTRODUCTION
Previously described approaches to digital-analog (D/A) and
successive-approximation analog-digital (A/D) conversion have
relied on circuit techniques which require the matching of on-chip
precision passive components to an accuracy comparable with the
integral nonlinearity required in the converter. R-2R ladders,
resistor strings, and capacitor array DAC’s fall into this category.
The realization of the required matching has typically required
laser trimming or other forms of trimming in order to achieve
nonlinearity smaller than 0.2 percent. Recently, a new technique
has been described which allows the automatic calibration of a
capacitor array-based A/D converter. While very promising, this
approach requires considerable complexity in implementation [l].
Manuscript received May 25, 1983. This work was supported by the Na-
tional Science Foundation under Grant ECS-8023872, State of California
MICRO program, Racal-Vadic Corporation, Fairchild Semiconductor, and
GTE-Lenkurt Corporation.
The authors are with the Department of Electrical Engineering and Com-
puter Science, University of California, Berkeley, CA 94720.
009%4094/83/1000-0772$01.00
This letter describes a new approach to the implementation of
high-speed A/D and D/A conversion which achieves an absolute
linearity which is independent of the matching accuracy of the
passive components used to implement the converter. This is
achieved by the use of a modified form of the algorithmic
converter in which the reference voltage is circulated around the
loop as well as the signal, thereby canceling the gain error in the
loop, in contrast to previously described approaches [2]. Experi-
currently being fabricated. Experimental results from this proto-
type will be reported in a later publication.
II. CYCLIC A/D CONVERSION
The technique described in this paper is a modification of the
“cyclic” or “algorithmic” conversion technique [3]. The technique
described here is an approach to making an MOS implementa-
tion of such a converter which displays a differential and integral
linearity that is independent of the capacitor ratios within the
converter. Traditional cyclic or algorithmic conversion involves
comparison, reference subtraction if applicable, and multiplica-
tion of the result by a factor of two. The first step in the process
is the decision as to whether the signal is in the upper or lower
half of the full range. If the signal is in the upper range, the
reference is subtracted from the signal and the difference is
doubled. The most significant bit of the digital output is set to
one. If in the lower half, the input signal is simply doubled and
the most significant bit is set to zero. In the next cycle, the
remainder from the previous cycle is used as the input and the
process is repeated. Following the procedure, the signal can be
encoded into a 1Zbit digital output in 12 iterations.
In the D/A operation the least significant bit is decoded first.
The reference voltage is added depending on the digital input
code and the sum is divided by two each time. At the end of 12
cycles, the analog output is derived from the digital code. The
principal sources of error in these converters is offsets in the loop
and a loop gain which is not precisely two or one half. If the loop
gain is not precisely two or one half, both integral and differen-
tial nonlinearity is introduced into the converter transfer char-
acteristic.
The switched-capacitor implementation of the cyclic conver-
sion requires an amplifier with gain of two, a sample and hold
circuit and a comparator. The basic structure of the converter is
shown in Fig. 1. An operation of sampling and transferring the
signal twice will result in multiplication of the signal by a factor
of 2 Cl/C2. If Cl and C2 are equal, this will give a gain of two.
However, deviations from equal values in Cl and C2 will result in
conversion errors. Taking into account of the capacitor ratio
inaccuracy and other high order errors existing in the loop, the
loop transfer equation is
T(x)=2x-t 2 E,x’
i=O
where E,, is the dc offset, E, is the loop gain error due to
capacitor mismatch, etc., and E,, E3 are the other high-order
distortions. These deviations result in both integral and differen-
tial nonlinearity.
III. REFERENCE REFRESH PRINCIPLE
In order to remove the gain errors in the loop, it is necessary to
use a switching sequence which removes the dependence of the
effective gain factor on capacitor ratios. It can be recognized that
01983 IEEE
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-30,
A
-Vin -
A
-vret -
Fig. 1. Fully differential switched-capacitor implementation of the converter.
an equivalent result to a precise gain of two would be obtained if
the reference was modified on each cycle by a factor which was
the same as the factor by which the loop gain was different from
two. In other words, the gain error E, can algorithmatically
corrected by modifying the reference voltage (&.r) at each cycle
based on the loop error. The reference voltage of the circuit is not
fixed in the processing but is updated once each cycle. The
effective reference voltage (@r) at the k th cycle will be
Vrer(1-t ( Ei /2)) k. The following example explicitly shows the
correction effect for a 3-bit A/D conversion.
where
A=2
I+? . 1Zbit digital output.
( 1
Through the use of the reference refresh operation, A/D and
D/A linearity is made independent of the mismatch of capaci-
tors. The great advantage of this technique is that as long as the
reference and the signal are passed through the same loop, the
errors related to charge injection and finite operational amplifier
gain are automatically canceled, as long as they contribute only
gain errors. This fact greatly simplifies the implementation of
high-resolution converters.
IV. REFERENCE REFRESHIMPLEMENTATION
The reference recirculation technique can be implemented so as
to give both ratio independent analog-to-digital conversion and
digital-to-analog conversion. The signal flow through the circuit,
shown as Fig. 1, is briefly described below. The signal is first
sampled on C, and transferred to C,. The reference is next
subtracted from the signal by changing one end of C, from
ground to - V,,. If the signal is smaller than the reference,
simply reconnecting the C, back to ground will make the signal
return to its initial value. The new outcome is doubled by
sampling the voltage on C, and dumping the charge twice on C,
NO. 10, OCTOBER 1983 113
(4 (b)
Fig. 2. D/A with 10 percent gain error. (a) No reference refreshing integral
nonlinearity = l/4 LSB, differential nonlinearity = l/2 LSB. (b) With refer-
ence refreshing integral nonlinearity = 0 LSB, differential nonlinearity = 0
LSB.
2.250
I I I I
0.000 0.750 1.500 2 250 3.000
(a) (b)
Fig. 3. 4 bit A/D with 20 percent gain error, (a) No reference refreshing,
integral nonlinearity = 1 LSB, differential nonlinearity = 7/4 LSB. (b) With
reference refreshing integral nonlinearity = 0 LSB, differential nonlinearity
= 0 LSB.
without discharging C, at the second time. At this moment, the
reference is also sampled on C, and transferred to C,. When the
signal is transfered back to C,, the reference is passed through C,
and C, without being doubled. When the reference is needed at
the next cycle to determine the signal level, the newly changed
reference is used. This reference is at the output of the second
operational amplifier will experience the same gain error as the
signal did. This whole process is repeated 12 times to derive a
For digital to analog conversion, the least significant bit is
processed first. If the bit is one, the reference is added to the
temporary result and the temporary result is divided by two. At
next frame, the reference is refreshed by passing through the
loop. Unlike the A/D, the loop gain of the D/A is one half
instead of two. In order to achieve the unity gain for the
reference voltage, this time the reference voltage is integrated
twice. For the same reason as the A/D conversion, reference
refreshing must be interleaved during the development of the
analog output. By implementing the above correction method, the
D/A can also be ratio independent. A comparison of the D/A
with and without the reference refresh technique is shown in
Fig. 2.
V. SIMULATIONRESULTS
5.1. Gain Error
Simulation of the reference recirculation technique have shown
that indeed it removes the sensitivity of the converter linearity to
capacitor ratio mismatch and finite operational amplifier gain.
Fig. 3(a) and 3(b) shows the transfer curve of a 4-bit algorithmic
 114 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-30, NO. 10, OCTOBER 1983

3.000 On Deriving Rectangular Transform Matrices for

2.625 - Cyclic Convolution
N. SRIDHAR REDDY AND M. N. S. SWAMY

Ahstruct -Rectangular transforms (RT’s) were proposed for efficient

0.000,, I 1 1 1 1 routine may be used to solve such systems of equations.
.375 ,750 I.125 1.500 1.875 2.250 2.625
Fig. 4. 4 bit A/D with 1.06 LSB operational amplified offset, integral non-
linearity = l/2 LSB. differential nonlinearity = 1 LSB.
A/D converter with a capacitor mismatch error of 10 percent
with and without reference refreshing.
5.2. Offset Errors
The presence of dc offset voltages in the loop of a magnitude
comparable with an lsb results in both integral and differential
nonlinearity in the converter transfer characteristic. Since for a
13-bit converter with a reference voltage of 3 V one lsb is less
than 1 mV, the removal of offsets from the loop is essential.
The principal contributions to offset voltage are the opera-
tional amplifier offset voltage and the offsets resulting from
mismatches in charge injection from the MOS switches. Fig. 4
shows the transfer curve of a 4-bit A/D with dc offset in the
operational amplifier. The offset error distorts not only the signal
itself but also the refreshed reference.
The proposed experimental implementation of this converter
utilizes fully differential operational amplifiers with multi-phase
active offset compensation [4]. This permits offset voltages in the
loop to be nulled to an arbitrary degree of precision, in this case
chosen to be approximately 0.1 mV assuming a lo-percent rnis-
match in the gate capacitance of a minimum sized switch pair.
computation of cyclic convolution. The algorithms were derived with the
aid of the Chinese remainder theorem (CRT). In this letter, we present a
simpler procedure to derive the RT algorithms by posing the problem as a
set of over-determined linear systems of equations. Any standard sub-
3.000
I. INTRODUCTION
Recently, a class of algorithms known as rectangular trans-
forms (RT’s) [l]-[3] were proposed for efficient implementation
of cyclic convolution. The RT may be described as follows. The
cyclic convolution of two sequences {x, } and { h, } of length N
given by
N-l
.h= c Xmh(n-m)modN, n=O,l;..,N-1 0)
m=O
can be expressed as
d= Bh@Ax
y=Cd (2)
where 8 denotes point-by-point multiplication of column vec-
tors, A and B are M X N matrices, C is a matrix of order N X M,
M( > N) is the number of multiplications required by the algo-
rithm, and d, h, x, and y are column vectors. In a fast implemen-
tation of (2), Bh is precomputed since the impulse response,
{ h ,, }, is normally known a priori. Ax and Cd are implemented by
a sequence of additions/ subtractions. Considering the signal-to-
noise ratio (SNR) performance and hardware complexity, it was
shown [4] that for small-wordlength digital-filtering applications,
RT’s are better suited than other convolution algorithms. RT
matrices are derived with the aid of the polynomial version of the
Chinese remainder theorem (CRT). In this letter, we present a
simple and novel procedure to derive the same.

VI. CONCLUSIONS II. DERIVATION OF RT MATRICES

A new approach to algorithmic A/D and D/A conversion has Let
been described which combines the techniques of switched capa- N-l
citor cyclic conversion and reference voltage refreshing. The X(z) = c x,z”
performance of the converter is capacitor ratio independent and n=O
the analog portion of the coverter can be realized by two opera- N-l
tional amplifiers, one comparator, and a few small capacitors in H(z)= c h,z”
the range of a few pica farads. Because of the ratio independent n=O
aspect, very small component values can be used and as a result N-l
the die area required for this circuitry can be scaled as techno- Y(z) = c y,z”. (3)
logical feature sizes are reduced. n=O

REFERENCES
[l] H.-S. Lee and D. A. Hodges, “Self-calibration technique for A/D con-
verters,” IEEE Trans. Circuits Syst., vol. CAS-30, pp. 188-190, Mar. 1983.
[2] C. C. Lee, “A switched-capacitor A/D converter that is insensitive to
capacitor ratios,” presented at the Dig. Papers, 1983 International Symp.
Circuits and Systems, Newport Beach, California, May, 1983.
[3] R. H. McCharles, “Charles circuits for analog LSI,” IEEE Trans. Circuits
.Sya., vol. CAS-25, pp. 490-497, July 1978.
[4] R. C. Yen and P. R. Gray, “A MOS switched-capacitor instrumentation
amplifier,” IEEE J. Solid-State Circuits, vol. SC-17. pp. 1008-1013, Dec.
1982.
It is, then, easy to verify that the cyclic convolution output, { y,, },
can be obtained in terms of { xn } and {h, } from the coefficients
of Y(z) polynomial given by
Y(z) = X(z)H(z)modP(z)
(4
Manuscript received May 12, 1979. This work was supported by National
Sciences and Engineering Research Council of Canada under Grant A-7739.
The authors are with the Department of Electrical Engineering, Concordia
University. Montreal, P.Q., H3G lM8 Canada.

0098-4094/83/1000-0774$01.00 01983 IEEE