Operational Amplifier

Prof. Yang Xu
Electrical and Computer Engineering Department
Illinois Institute of Technology
Chicago, IL 60616 USA

Reading Material: Sections 5.2, 5.5, 6.8, 7.4, 9.4.5

 High Level Viewpoint of an Op Amp

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 Ideal Op Amp

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 General Configuration of Op Amp as Voltage Amplifier

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 Simplified Analysis of an Op Amp Circuit

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 Linear and Static Characteristics of Op Amp

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 Linear and Dynamic Characteristics of Op Amp

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 Op-amp Specifications

Dynamic Characteristics

Open-loop DC Gain
3-dB Bandwidth
Unity Gain Frequency
Phase Margin
Gain Margin

Power!
Area!

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 Two-stage Op Amp Topology

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 Input common mode range and output swing

Input common mode range

Output Swing

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 Gain and bandwidth

Small-signal model

DC gain

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 Frequency response

Small-signal model

Dominate pole:

Unity-gain frequency:

Frequency response: (>>p1)

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 Phase Margin and Gain Margin

Definition

Phase Margin:

Gain Margin check by simulation

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 Systematic and random input offset

Systematic input offset: caused by current imbalance at the output stage

Can be minimized following this condition

Random input offset: caused by mismatch between identical elements.

Minimize through careful layout and other physical design.

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 Slew Rate

Internal Slew Rate

External Slew Rate

Overall Slew Rate: The minimal of the above two

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 Noise

Input referred thermal noise spectral density

Noise and Power Trade-off

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 Two-stage Op Amp Topology (PMOS input)

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 Example  Put everything together

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 Op-amp v.s. OTA (1)

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 Op-amp v.s. OTA (2)

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 Fully Differential vs. Single-ended

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 Other Op-amp Topologies

Simple OTA op-amp

OTA op-amp

Two-stage cascoded op-amp

Folded-cascode op-amp

Telescopic op-amp

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 Classification of CMOS Op-amp

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 Simple op-amp OTA

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 OTA op-amp

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 Two-stage cascoded op-amp

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 Folded-cascode op-amp

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 Telescopic Op-amp

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 http://www.nxp.com/documents/data_sheet/NE5234_SA5234.pdf

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 Architecture

Biasing

(+)
Input Stage Second Stage Output Stage Out
(-)

 Provides differential  Provides  Provides high

input with large additional current drive
common mode voltage gain capability
range
 Output can
 Provides some (approximately)
voltage gain, swing rail-to-rail
approximately
independent of
common mode

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 Basic PNP Differential Pair Input Stage

 Circuit works for input common mode

down to VEE (0V), as long as

VBE  VCE(sat)  VR1

VR1  VBE  VCE(sat)  0.8V  0.2V  0.6V

 This limits the gain we can extract from

this stage

IBIAS V 600mV
gm1R1  R1  R1   23
2VT VT 26mV

Text, p. 449

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 PNP Folded Cascode Input Stage

 Circuit still works for input

common mode down to VEE
(0V), as before
 But, the low frequency voltage
gain is much larger

v od R3
 gm1 Ro
v id 1
R3 
gm
Ro  ro6 1  gm6R6  ro3 1  gm3R3 

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 NE5234 Input Stage

~0.9V

 Provides rail-to rail common-mode input range by combining the

currents from a PNP and NPN pair
 The NPN pair “steals” current from the PNP pair at node X whenever the
input common mode is greater than |VBE|
– Total Gm is approximately constant
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 Second Stage

0.5V 0.5V

0.5V

~0.9V

+ 0.4V -

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 Common Mode Operating Point of Stage 1 Output

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 Basic Emitter Follower (“Class-A”) Output Stage

 Issues
– Output voltage cannot go
higher than VCC – VBE
– Need large quiescent current
IQ to provide good current
sinking capability
– IQ flows even if no signal is
present, i.e. Io=0

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 Output Stage Nomenclature

 Class-A
– Output devices conduct for entire cycle of output sine wave
 Class-B
– Output devices conduct for 50% of sine wave cycle
 Class-AB
– Output devices conduct for >50%, but <100% of cycle

Class-A Class-B Class-AB

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 Class-AB Emitter Follower Output Stage

 Small quiescent current, but

large drive capability
 Remaining issue
– Output voltage swing is
severely limited

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 Class-AB Common Emitter Output Stage

 Q1 and Q2 are large

devices
 Want to set the quiescent
point such that IC1 and IC2
are small when no signal is
applied

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 Analysis

 Assuming IC3 = IC4 = IREF by symmetry, we can write

VBE6  VBE8  VBE4  VBE2

IREF IREF IREF IC2


Is6 Is8 Is4 Is2

Is2 Is4
IC2  IREF
Is6 Is8

 Quiescent current is set by IREF and emitter area ratios (Is  AE)
 The same principle applies to CMOS implementations
– Original paper by Monticelli, JSSC 12/1986

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 CMOS Version

[Hogervorst, JSSC 12/1994]

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 Simulated Currents (Vo=0)

 Output transistors
never turn off
 Quiescent current set
Iout by transistor ratios
Current [A]

ID(M26)
 Large drive capability
ID(M25)

Iin1=Iin2 [A]

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 NE 5234 Output Stage

 Feedback through Q39-40 ensures that both transistors remain on at

extreme output swings

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 Simplified AC Schematic of Complete OpAmp

Nested Miller
Compensation

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 Compensation Issue (1)

 The designer of a general purpose OpAmp knows nothing about the

feedback network that the user will connect around the amplifier
 Therefore, general purpose OpAmps are typically compensated for the
"worst case", i.e. unity feedback configuration
 This tends to be wasteful, since much less compensation may be
needed for other feedback configurations
– To overcome this issue, some general purpose OpAmps provide an
external pin to let the user decide on the required compensation
capacitor

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 Compensation Issue (2)

Wasted BW

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 “Internal” Amplifiers (1)

 Most amplifiers used in large

systems-on-chip (SoC) are not as
complex as a typical general
purpose OpAmps
– Typically, no output stage is
needed, since the loads are
either small and/or purely
capacitive
 Operational Transconductance
Amplifier (OTA) = OpAmp minus
Output Stage
 More in textbook (see text, section
6.1.7, and chapter 12) Mehta et al., "A 1.9GHz Single-Chip
CMOS PHS Cellphone," ISSCC 2006.

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 “Internal” Amplifiers (2)

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