Accuracy Limitations of Pipelined ADCs

Patrick J. Quinn Arthur H.M. van Roermund

Xilinx Eindhoven University of Technology
Citywest Business Campus Department of Electrical Engineering
Logic Drive, Dublin, Ireland 5600 MB Eindhoven, The Netherlands

Abstract In this paper, the key characteristics of the main MDAC

errors which affect the performance of a switched capacitor C1
Vin clk2 dclk2

pipelined ADC are presented and their effects on the ADC i clk1 dclk1

clk1 C2
transfer characteristics demonstrated. Clear and concise Vref
dclk2

Vout
top i
relationships are developed to aid optimized design of the mid
clk1
(Analog
Vref
pipeline ADC and error bounds are derived. bot Residue)

I. INTRODUCTION Vref top

4 Latches
Previous authors [1],[2],[3] have presented generalized anal- and mid
yses of the switched capacitor (SC) pipeline but a more compre- Vref
Clkgen
bot
4
hensive analysis is needed to aid its exact design. The analysis in
this paper includes, for instance, a model for capacitor mismatch, Sub-ADC bMSB b
LSB

slewing behaviour and an exact choice of capacitor sizing based

on the ADC resolution and hence noise specification.
The lowest resolution stage, using redundant-signed-digit
decoding and delivering one effective output bit, is the most
effective for achieving high throughput with high accuracy and
low power [1],[2]. The ideal transfer gain of the converter stage
is 2, while the residue equation is
Vouti = 2 ◊ Vini - Di ◊ Vref ,
(1)
where data bits Di have values of 0 (for Vini falling within
± Vref 4), or -1 (for Vini falling below - Vref 4) or +1 (for Vini
going above + Vref 4). In reality, the residue voltage is affected
by a number of non-idealities associated with practical imple-
mentation which cause deviations from the ideal linear ADC
transfer characteristic. Familiarity with the effect a particular
error can have on the ADC transfer will help identify the source
of any serious errors should they arise in fabrication. The most
important errors are explored and quantified in the following sec-
tions, while the effects the errors have on the ADC transfer char-
acteristics are illustrated. Error bounds are derived to ensure the
ADC specification is met.
II. CONTEMPORARY PIPELINE ADC STAGE
The typical implementation of a SC pipeline ADC stage (1-bit
effective output) is depicted in Fig. 1 and is based on charge transfer
techniques [2],[3]. In the bottom path, the sub-ADC (just 2
Fig. 1 Contemporary single-ended SC charge transfer
implementation of pipeline ADC stage (K=2)
and C2 in parallel, while at the same time the sub-ADC determines
whether it falls into the top, middle or bottom of the ADC reference
range. At the end of the clk1, Vin is completely sampled on to C1
and C2, while the output of the sub-ADC is latched and held. On
clk2, C1 is switched and placed across the amplifier, closing its neg-
ative feedback loop, while at the same time only one of the input
switches of C2 is closed by the sub-DAC using only one of clock
signals top, mid, bot, connecting C2 to either +Vref, 0, or -Vref. By
choosing C1 = C2, a nominal transfer gain of 1 + C2 C1 = 2 is
achieved. Note that the analysis which follows can be applied to
other implementations of MDAC, for instance, reference [2].
III. LUMPED ERROR MODEL
Each ADC pipeline stage is specified such that all accumulated
errors at the end of the conversion process remain inside 1/2 LSB.
Although 1 LSB is enough for monotonicity, 1/2 LSB is specified
to be safe. The total fractional error e tot is the accumulation of all
errors from the NS stages referred back to the ADC input, i.e.
NS
ei
e tot = Â i
, (2)
i =1 ’G j
j =1

comparators with thresholds set at ± Vref 4 ) reacts instanta- where e i is the net fractional stage error. Usually 1-bit redun-
neously to the analog input signal to produce a coarse digital dancy is employed per stage for redundant-signed digit
representation. The resultant digital code is output to a digital decoding [1] so that for a K-bit stage, K-1 bits are effectively
decoder, while at the same time it is converted back to its resolved and the stage gain factor becomes Gi = 2 K -1. Hence
gained-up analog equivalent by the equally coarse multiplying NS
ei
DAC (MDAC). The MDAC performs the level shifting, analog e tot = Â . (3)
2(
K -1)◊i
i =1
multiplication by 2 and sample-and-hold buffering needed to pro-
The magnitude of the largest allowed total input referred voltage
duce the stage analog residue. On clk1, the Vin is sampled on to C1
error is

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 1
(a) Stage 1 transfer with offset=+5Vref/16
1
(c) Stage 1 transfer with offset=-5Vref/16 conditions are set for e s ,e d of each stage in order to ensure a
0.75
non-ideal
0.75
robust design:
e s,d £ 2 -( N -i + 2).
0.5 0.5

0.25 0.25
(7)
Vout Vref

Vout Vref
0 0

-0.25
ideal -0.25 The various sources of static and dynamic errors are described in
-0.5

-0.75
-0.5

-0.75
the following sections.
-1 -1 The worst-case INL can be evaluated from the standard devi-
ation (stot) of the total equivalent input error. The error should be
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
Vin Vref Vin Vref

(b) ADC transfer with stage 1 offset=+5Vref/16 (d) ADC transfer with stage 1 offset=-5Vref/16 obtained for the expected worst case code transition, for instance
1 1

0.75
missing 0.75 when Vin crosses Vref 4 . Assuming a Gaussian distribution for
codes
the voltage difference e between the actual and ideal transfers,
0.5 0.5

0.25 wide 0.25

Vout Vref

Vout Vref

code

the INL can be obtained as the expected value of e :

0 0

-0.25 -0.25

-0.5 -0.5
• e2
-
INL = E ÈÎ e ˘˚ = Ú e◊ ◊e de
-0.75 -0.75 2
1 2◊s tot
-1 -1
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
2◊p ◊s tot
2
Vin Vref Vin Vref -•

Fig. 2 Effects of excessive input offset on ADC transfers = 2

p
◊ s tot (8)

Ve tot £ e tot ◊ Vref . (4) IV. LIMITATIONS ON STATIC ACCURACY

The magnitude of the total voltage error should be less than 1/2
LSB to reliably guarantee monotonicity, i.e.
e tot ◊ Vref £ LSB
fi e tot £
2N
Alternatively, each individual stage should be designed to have
a total voltage error less than 1/4 LSB of the total effective reso-
lution of the remaining stages. Note that this is approximately at
the level of the quantization noise error of the remaining stages,
which is 1 12 ª 1/4 LSB . Assuming each stage i is K-bits, the
total fractional output error is specified as
e i ◊ Vref £ 14 ◊
fi ei £
The stage error arises from the addition of all the errors from var-
ious static (e s ) and dynamic (e d ) sources. Usually, the stage is
designed such that the dynamic and static errors add up in roughly
equal measure. Hence, for the usual K=2-bit stage, the following
1
(a) After stage 2 with bott comp offset = +3Vref/8
0.75
0.5
A. Offset Errors
There are two basic forms of offset which have different
2 (= 1
2
◊
2◊Vref
2N ) effects on the ADC transfer. Firstly, there is input offset which
adds up with the input signal to the stage. This offset is due mainly
1 . (5) to the amplifier and to a lesser extent to the switches. The transfer
function in this case is of the form:
( )
Vouti = 2 ◊ Vini + Voffin - Di ◊ Vref , (9)
where the offset gets multiplied up by the stage gain. The second
form of offset is that due to the comparators which has the effect
of shifting either one or both decision levels of the sub-ADC.
The total offset from all sources must remain within the
2◊Vref bounds of ± Vref 4 to avoid saturating the following stage and
N -( K -1)◊i
2 causing missing codes. This requirement is not dependent on the
N -( K -1)◊i +1
1
. (6) required accuracy of the whole ADC, nor indeed accuracy of each
2
individual stage. The offset accumulates according to equation
(2) though, so that some low offset ADC applications may need
some kind of active offset cancellation mechanism.
In Fig. 2, the effects of input offset going beyond ± Vref 4 are
shown. The grey curves show the ideal and the black the non-ideal
1
(c) After stage 2 with top comp offset = -3Vref/8 transfers. Consider Fig. 2(a),(b), where the input offset goes beyond
0.75
+ Vref 4 : the ADC transfer characteristic shows a single wide code
0.5

0.25 0.25 for when the stage output voltage exceeds +Vref, followed by miss-
Vout Vref
Vout Vref

0 0

-0.25 -0.25
ing codes, the number of which depends on how much the stage out-
-0.5 -0.5 put voltage exceeds +Vref. In Fig. 2(c),(d), the input offset goes
-0.75 -0.75

-1
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
-1
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
under - Vref 4, in which case the ADC characteristic first has
Vin Vref Vin Vref
missing codes followed by a single wide code. In Fig. 3, the separate
1
(b) ADC with stage 2 bott comp offset = +3Vref/8
1
(d) ADC with stage 2 bott comp offset = -3Vref/8 effect of sub-adc comparator offsets exceeding ± Vref 4 in stage
0.75 0.75
2 are demonstrated for both the top and bottom comparators.
0.5 0.5

0.25 0.25
B. Capacitor mismatch gain errors
Vout Vref

Vout Vref

0 0

-0.25 -0.25 The generalized transfer function of the ADC stage including
-0.5 -0.5
capacitor mismatch errors is

( ) - D ◊V
-0.75 -0.75

◊ (1 + D c ) ,
Dc
Vouti = 2 ◊ Vini ◊ 1 +
-1 -1
-1 -0.75 -0.5 -0.25 0
Vin Vref
0.25 0.5 0.75 1 -1 -0.75 -0.5 -0.25 0
Vin Vref
0.25 0.5 0.75 1
2 i ref (10)

Fig. 3 Effects of excessive stage 2 compr offsets on ADC transfers

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 where D c represents the mismatch of nominally equal capacitors 1
(a) After stage 2 with positive ∆c in stage 2
1
(c) After stage 2 with negative ∆c in stage 2

C1 and C2. The capacitor matching requirement for the i-th 2-bit- 0.75 0.75

0.5 0.5

stage is 0.25 0.25

Vout Vref
Vout Vref
s DC £
0 0
1
, (11) 3¥ 2 N -i -1
-0.25 -0.25

-0.5 -0.5
An important observation with this kind of gain error is that there -0.75 -0.75

is always an exact mapping of input values to output values, irre- -1

-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
-1
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1

spective of D c :
Vin Vref Vin Vref

{
Vin Œ -Vref , 0 , +Vref Æ Vout Œ -Vref , 0 , +Vref . (12) } { } 1

0.75
(b) ADC transfer with stage 2 positive ∆c
1

0.75
(d) ADC transfer with stage 2 negative ∆c

This suggests a very effective way of calibrating out capacitor 0.5 0.5

mismatch errors by extrapolating between these correctly 0.25 0.25

Vout Vref

Vout Vref
0 0
mapped points. -0.25 -0.25

The effects of capacitor mismatch errors in stage 1 are illus- -0.5

-0.75
missing codes at
-0.5

stage 1 transitions -0.75

trated in Fig. 4 Positive capacitor mismatch errors (Fig. 4(a),(b)) -1

-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
-1
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1

cause a series of wide codes and negative code jumps resulting Vin Vref Vin Vref

in non-monotonicity. Negative capacitor mismatch errors (Fig. Fig. 5 Effects of stage 2 cap mismatch errors on ADC transfers
4(c),(d)), on the other hand, cause a series of narrow codes and
positive code jumps, resulting in missing codes. Fig. 5(a),(b) The stage transfer, including OTA gain error e A0 , is

( )( )
show the result of positive capacitor mismatch in stage 2. Here
again there are wide codes corresponding to the six transition Vouti = 2 ◊ Vini - Di ◊ Vref ◊ 1 + e A0 , (13)
points from the ADC input to the second stage output. Further- where e A0 ª - 1
A 0 ◊ b fb
. (14)
more, there are also two sets of missing codes at ± Vref 4 which In general, the DC gain requirement for stage i is given by
are the transition points of the previous stage. A similar scenario
exists for negative capacitor ratio errors (Fig. 5(c),(d)), except A0 > 1
b fb
◊ 2 N -i + 2. (15)
that wide codes are replaced by narrow codes and negative and To take an example, say the SC ADC stage of Fig. 1 is
positive code jumps are interchanged. designed as the first stage in a 12-bit pipeline ADC. The feedback

C. Amplifier Gain Errors factor is b fb = C1 C1 +C2. With C1 = C2 nominally, b fb = 1

2, so
The OTA, in a switched-capacitor configuration of any stage that the amplifier DC gain is required to be A0 (dB) > 84dB !
i along the pipeline, must linearly amplify the input voltage by a An important observation with this kind of gain error is that
factor of 2 over the full scale range of -Vref to +Vref to within a there is always an exact mapping of the zero crossings irrespec-
maximum error of 2- ( N - i + 2). As a result of the sampled-data oper- tive of DC gain error, be it linear or non-linear, i.e.
ation of the stage, only end values count at the end of sample clock
periods. Hence, only DC gain variations around DVin = 0 count,
Vin Π- { Vref
4 , 0, +
Vref
4 } Æ 0.
since the differential OTA input always settles back to around 0V IV. LIMITATIONS ON DYNAMIC ACCURACY
as the output end value is reached. The OTA DC gain has an effec-
A. Linear and Non-linear Settling Constraints
tively even characteristic and the DC gain doesn’t vary much
around DVin = 0 whether the outputs end up at 0V or at ±Vref . The stage amplifier slews when the step voltage at the ampli-
fier differential input goes beyond the maximum linear input
1
(a) Stage 1 transfer with positive ∆c
1
(c) Stage 1 transfer with negative ∆c range of 2 ◊ Von which corresponds to it delivering its maximum
0.75 0.75 current I to the load. The dynamic settling error e settle caused by
0.5 0.5

0.25 0.25
the amplifier not settling out in sample period T is
Vout Vref

Vout Vref

Ï 2 ◊Von
0 0

-0.25 -0.25
Ô e - n , Vstep £ g
-0.5 -0.5
e settle =Ì (16)
2 ◊V 2 ◊Von
Ô g ◊V on ◊ e - n , Vstep >
-0.75 -0.75

-1 -1
Ó step g

( )
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
Vin Vref Vin Vref
T - tslew g ◊Vstep
where n = t
and tslew = t ◊ -1 . (17)
(b) ADC transfer with stage 1 positive ∆c (d) ADC transfer with stage 1 negative ∆c 2 ◊Von
1 1

0.75 0.75 Note g ◊ Vstep is that proportion of Vstep which the amplifier
0.5
co
d es 0.5
input sees through capacitor division before it starts to react. This
0.25 de 0.25
wi
Vout Vref

Vout Vref

0 all 0 error (16) must be no larger than the required stage dynamic set-
£2 (
- N - i + 2)
tling error, e
-0.25 -0.25 missing
-0.5 -0.5
codes
. The effect of combined finite set-
settle
-0.75 -0.75
tling time and finite slew rate is shown in Fig. 6. The limited
-1 -1
-1 -0.75 -0.5 -0.25
Vin Vref
0 0.25 0.5 0.75 1 -1 -0.75 -0.5 -0.25 0
Vin Vref
0.25 0.5 0.75 1
settling time produces a similar effect to limited DC gain in the
sense that end values are not achieved within a sampling clock
Fig. 4 Effects of stage 1 cap mismatch errors on ADC transfers

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 ( )
◊ Ê 34 ◊ b fb ◊ CkT ◊ 1 + N eOTA + kT ˆ.
(a) Stage 1 transfer with slewing in 1st stage (c) After stage 2 with slewing in 2nd stage

s N2 stage ª
1 1
1 (23)
Ë C ¯
0.75 0.75

0.5 0.5
b 2fb Leff
0.25 0.25
The equivalent input noise power for each stage is obtained by
Vout Vref

Vout Vref
0 0

-0.25 -0.25 dividing the stage output noise power by the signal gain up to that
-0.5 -0.5

-0.75 -0.75
stage. For similar stages, the power gain factor per stage is just
1 b 2fb , and the total equivalent noise calculated back to the input is
-1 -1
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
Vin Vref Vin Vref

( ) b 2

1
(b) ADC transfer with slewing error in 1st stage
1
(d) ADC transfer with slewing error in 2nd stage s N2 tot = s N2 stage ◊ b fb2 ◊ 1 + b fb2 + b 4fb + … ª s N2 stage ◊ 1- bfb2 . (24)
fb
0.75 0.75

0.5 0.5 Substituting (23) into (24), the total input-referred pipeline ADC
0.25 0.25
noise power ends up as
Vout Vref

Vout Vref

0 0

(
◊ Ê 34 ◊ b fb ◊ CkT ◊ 1 + N eOTA + kT )
ˆ.
-0.25 -0.25

-0.5 -0.5
s N2 tot ª 1 (25)
-0.75 -0.75
Ë
1- b 2fb Leff C ¯
-1 -1
-1 -0.75 -0.5 -0.25 0
Vin Vref
0.25 0.5 0.75 1 -1 -0.75 -0.5 -0.25 0
Vin Vref
0.25 0.5 0.75 1
To ensure that the total SNR is degraded by just 1.76 dB, the ther-
mal noise power is specified with respect to the quantization
Fig. 6 Effects of non-linear settling errors on ADC transfers
noise power s D2 by s Ntot < 12 ◊ s D . Hence,
2 2

( )
interval. This is a linear effect though, unlike limited slew rate
1
◊ Ê 34 ◊ b fb ◊ CkT ◊ 1 + N eOTA + kT ˆ < 1 ◊ FS 2 . (26)
which is input level dependent. This is clear from Fig. 6, where 1- b fb
2
Ë Leff C ¯ 24 22 N
large input levels up to ±Vref cause a tapering off effect leading The minimum value of C, based on noise considerations, can
to poor INL and harmonic distortion. Note again that the zero be found for the SC MDAC pipeline stage of Fig. 1. Assuming
crossings are correctly mapped despite the non-linear distortion. parasitic capacitance at the amplifier input is small compared
to C, then CL = C1 + C2 + b fb ◊ C2 , which with C1 = C2 = C ,
B. Thermal Noise eff
The output noise power produced by a single ADC stage, 5 N eOTA is typically in the range of 1 (single-
gives CL =
2
◊ C.
eff
such as Fig. 1, has 3 constituents:
stage OTA) to 2 (dual-stage OTA) - N eOTA = 2 is chosen here.
s N2 = s N2 + s N2 + s N2 , (18)
stage OTA Cread Cwrite The minimum value of C is now defined by:
with s N2 amp the amplifier (OTA) noise sampled only in the write
2N
C > 45 ◊ kT ◊ 2 2 . (27)
FS
phase and s N2 C ,s N2 C the noise produced by the switches in For a 12-bit differential application with 1V signal range and full
Nyquist operation, C > 3.1pF . Note the importance of maximiz-
read write

both the read and write phases. The thermal noise power of the
OTA, referred to the output, is given by ing signal range for the sake of minimizing signal capacitance, so

( )
that if the signal range is doubled to 2V, the capacitance is reduced
s N2 OTA = 163 ◊ kT ◊ g1 ◊ 1 + N eOTA ◊ BNOTA ◊ b12 , (19) by a factor of 4 (C=3/4pF) for the same 12-bit performance.
m fb

where 16
3
◊ kT ◊ g1 is the noise power spectral density of a differ- III. CONCLUSIONS
m

ential pair and N eOTA is the noise excess factor depending on OTA A lumped error model was developed in this paper to account
architecture used. The amplifier input noise power is multiplied for static and dynamic errors due to hardware imperfections in
by G 2 = 1 b 2fb , which is the noise power gain from stage input fabricated pipelined ADCs. Errors arising, for instance, due to
imperfect capacitor matching, non-linear settling behavior and
to output. For an essentially first order amplifier settling noise were analyzed. The effects of various expected error
response, the amplifier noise bandwidth is sources on the ADC transfer characteristics were described. It
b fb ◊ g m
BNOTA ª 1
4◊t OTA
= 4◊CLeff
, (20) was emphasized that familiarity with the effects specific errors
have on the ADC charactersictics can be a useful aid for debug-
with t OTA the linear settling time constant and CL the total ging hardware errors after ADC fabrication.
eff
effective load capacitance. Hence, the amplifier noise power for-
REFERENCES
mula can be reduced to
( )
[1] S. Lewis, “Optimizing the stage resolution in pipelined, multi-stage,
s N2 OTA = 4
3◊ b fb
◊ CkT ◊ 1 + N eOTA . (21) analog-to-digital converters for video-rate applications,” IEEE
Leff
Trans. Circuits Syst. II, vol. 39, Aug. 1992.
For the SC ADC stage, the switch noise contributions for the read [2] P. Quinn, M. Pribytko, A. van Roermund, “Calibration-Free High-
and write phases can be calculated as: Resolution Low-Power Algorithmic and Pipelined AD Conversion,”
s N2 C
read
= 2
b 2fb
◊ C kT
+C 1 2
and s N2 C
write
=
2◊ BNOTA
BN
swit
◊ ( kT
C1
+ CkT . (22)
2
) in “Analog Circuit Design,” Kluwer Academic Publishers, ISBN 1-
4020-2786-9 (HB), 2004, pp.327-349.
The factor 2 in (22) is for the differential case and BNOTA BN [3] Thomas B. Cho and Paul R. Gray, “A 10 b, 20 Msample/s, 35mW
swit
Pipeline A/D Converter,” IEEE J. Solid-State Circuits, vol. 30, no.
is the bandwidth reduction factor in the write phase Since noise 3, pp. 166-172, Mar, 1995.
in the read phase is pre-sampled, it is not affected by the OTA band- [4] J. Goes, J. Vital, and J. Franca, “Systematic design for optimization
width. Generally, BNOTA BN and with C1 = C2, the ADC stage of high-speed self-calibrated pipelined A/D converters,” IEEE
swit
Trans. Circuits Syst. II, vol. 45, Dec. 1998.
output noise power for full Nyquist operation becomes:

1959
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