Ques 1:

The access time of cache memory is 100 ns and that of main memory is 1000 ns. If
cache hit ratio is 0.9, determine the effective access time of the system.
Solution:
Access time of cache = 100 ns
Access time of main memory = 1000ns
Cache hit ratio =0.9
Effective time=100+(0.1)(1000)
= 100+100
=200 ns
Therefore from above we calculate that the access time of the system with
access time of cache memory 100 ns and that of main memory 1000ns with
cache hit ratio 0.9 is 200ns.
Ques 2:

A digital computer has memory unit of 64K x 16 words and cache memory of 1K words. If
direct mapping policy is used, determine the number of bits in:
a) Main Memory address
b) Cache Memory address
c) Tag and Index fields
Answer:

Ques 3:
Determine the number of page faults and number of page replacements for the
reference string: 1, 7, 3, 3, 2, 1, 7, 1, 2, 1, 3, 4 using FIFO, LRU and Optimal
algorithms.
Answer:

Ques 4:
Show Memory connections to CPU with four 128X8 RAM and one 512X8
ROM chip.
Answer:
Ques 5:

The content of Key register is 0001 1000. Determine which of the following words
of CAM match the Argument 1100 1011:
a) 1100 1011
b) 0010 1011
c) 1101 0101
d) 0011 0101
Answer:
Argument register 1100 1011
Key register 0001 1000
Word 1 1100 1011
Word 2 0010 1011
Word 3 1101 0101
Word 4 0011 0101
Only word 1 and word 2 matches because the bits of only word 1 and word 2 match
with the argument register at the place where the bits of the key register are 1.

Ques 6:

Design the architecture of DMA mode of operation and illustrate how various
components namely, CPU, RAM, DMA Controller and I/O Peripheral interface each
other.
Answer:

The position of DMA controller among other components in a computer system is

illustrated in the above figure.
The CPU communicates with the DMA through the address and data buses as with
any interface unit. The DMA has its own address lines which activates the DS and RS
lines. The CPU initializes the DMA through the data bus. Once the DMA receives the
start control command it can start the transfer between the peripheral device and
the memory.
When the peripheral device sends a DMA request, the DMA controller activates the
BR line, informing the CPU to relinquish the buses. The CPU responds with its BG
line, informing the DMA that its buses are disabled. The DMA then puts the current
value of its address register into the address register into the address bus, initiates
the RD and WR signal, and sends a DMA acknowledge to the peripheral device. RD
and WR lines in a DMA controller are bidirectional. The direction of the transfer
depends on the status of BG line. When BG=0, the RD and WR are input lines
allowing the CPU to communicate with the internal DMA registers. When BG=1, the
Rd and WR are output lines from the DMA controller to the RAM to specify the read
or write operation for the data.
When the peripheral receives a DMA acknowledge, it puts a word in the data bus
( for write) or receives a word from the data bus (for read). Thus the DMA controls
the read or write operations and supplies the address for the memory. The
peripgheral unit can then communicate with memory through the data bus for direct
transfer between the two units while the CPU is momentarily disabled.