Cmos Dac

Linköping Studies in Science and Technology
Dissertation No. 667
STUDIES ON CMOS
DIGITAL-TO-ANALOG CONVERTERS
J Jacob Wikner
Department of Electrical Engineering

Linköpings universitet, SE-581 83 Linköping, Sweden
Linköping 2001
Linköping Studies in Science and Technology
Dissertation No. 667
STUDIES ON CMOS
DIGITAL-TO-ANALOG CONVERTERS
J Jacob Wikner

Linköpings universitet, SE-581 83 Linköping, Sweden
Linköping 2001
Studies on CMOS Digital-to-Analog Converters
Copyright © 2001 J Jacob Wikner

Linköpings universitet,
SE-581 83 Linköping
ISBN 91-7219-910-5 ISSN 0345-7524

Printed in Sweden by UniTryck, Linköping, 2001
Abstract
In this thesis we present an overview and study on digital-to-analog converters (DAC), mainly
for communications applications. Especially, we look at some digital subscriber line (DSL)
specifications and communication over twisted-pair channels. It is pointed out that the required
resolution on the DACs in such systems is in the order of 12 to 14 bits of resolution. At the
same time the bandwidth stretches from below MHz to several tens of MHz. These figures are
the guiding specification throughout the thesis.
In this work we consider many of converter architectures and chips. The current-steering DAC
is pointed out as a suitable converter for both high speed and high resolution. We also investi-
gate the oversampling DAC (OSDAC) and discuss its properties in detail.
The performance of the converters is limited by both static and dynamic errors. The static
errors are usually caused by mismatch of the components and limit the accuracy at low speed.
The static performance is often described by measures of differential and integral nonlineari-
ties, (DNL and INL). For communication applications these measures are not especially used
for characterization of the DACs. Instead, the dynamic errors, such as settling errors, glitches,
etc., are more important since they increase with higher sample rates and signal frequencies.
To analyze the effect of errors it is usually easier to consider the DAC’s behavior in frequency
domain using measures, such as the spurious-free dynamic range (SFDR) and signal-to-noise-
and-distortion ratio (SFDR). These measures are normally derived from the output spectrum
when a sinusoidal input signal is used. In some applications it may be necessary to use several
sinusoidal tones to get relevant measures. Two common measures are the multi-tone power
ratio (MTPR) and the peak-to-average ratio (PAR). The PAR of the input signal affects the
maximum signal-to-noise ratio (SNR) of the converter and a small PAR is preferred since it
maximizes the SNR.
To help us understand how to design a converter several models and algorithmic expressions
are presented. The models are verified through simulations and partially through measure-
ments and experiments. Some of the most dominating error sources in converters, such as lim-
ited output impedance, device mismatch, and noise, are highlighted. We give suggestions on
how to reduce and minimize the influence of these types of error sources. These techniques
involve calibration and randomization, as well as cancellation through for example pre-distor-
tion algorithms. We also present the basics of dynamic element matching techniques (DEM).
5
Abstract 6
The usage of the models is to reduce the design time and get a good understanding for funda-
mental limitations on performence. Instead of time-consuming circuit-level simulations, we
point out the behavioral-level and algorithmic-level simulation of the converters. Most of the
models have been described in languages, such as Matlab and Mathematica.
Several chips have been implementated in CMOS and some improvement in performance has
been measured from generation to generation. By comparing two similar DACs with small
variations, we show how the performance of the converter depends on typical mismatches in
the layout. The measurement results are analyzed by using simulation results from the pro-
posed DAC models. By identifying distortion terms we can partially determine matching
errors, output impedance, and parasitic impedance.
Often the design of DACs is focused on the actual converter alone. We emphasize the need for
a broad view, where a more integrated digital/analog design is considered. The typical mixed-
signal and analog circuits, e.g., DAC, ADC, filters, amplifiers. In e.g. a transceiver must be co-
optimized. Analog circuits mix with digital circuits and signal processing algorithms on the
same chip and we have to carefully investigate how the different subcircuits interact.
We discuss the design and implementation of current-steering DACs for wideband applica-
tions. Different architectures are outlined and we emphasize the segmented DAC as the most
suitable converter structure for high speed and high resolution. Here, a key design issue is to
find the proper number of bits to encode into a thermometer code. This increases the digital
contents of the DAC, but reduces the glitches.
Further, we discuss issues involving design of OSDACs. We use the sigma-delta modulators to
reduce the number of bits representing the digital signal and then we use small and simple ana-
log circuits, which can be optimized with respect to the device. As a design case, we select an
OSDAC for ADSL applications. It is found that the requirements on the OSDAC are tough. It
is emphasized that the design of an oversampling converter essentially is a filter design prob-
lem. There is a large number of possible trade-offs that can be made between the different
building blocks in the OSDAC. Here, the key design issue is to define a proper cost function
that lets us find a good overall solution.
The thesis also presents some special converter architectures. A DAC’s behavior for different
input codes is examined. The thermometer code is the optimum code in terms of glitches and is
simplest for allowing interdigitized layout structures. However, for larger number of bits in the
encoder becomes rather large and complex. In the thesis we presentmore work where a linear
code is used. This code ends up in-between the thermometer code and the binary code in terms
of performance and complexity.
Acknowledgment
There are so many to thank for supporting the work that has been compressed into this thesis. I
thank all the members that have co-worked with me at Electronics Systems and Electronic
Devices at Linköping University and Ericsson Microelectronics AB, Ericsson Radio Systems
AB, and Ericsson Telecom AB. The head of the Electronics Systems group at the Department
of Electrical Engineering, Linköping University, Prof. Dr. Lars Wanhammar, is acknowledged
for the support and the encouragement.
I especially want to thank Dr. Mikael Gustavsson and Dr. Nianxiong Tan, Globespan, Inc., for
their help and the needed boost throughout my work. Thanks to Dr. Yonghong Gao, Ericsson
Radio Systems AB, for the great help with oversampling converters. Thanks to Peter Peters-
son, Ericsson Radio Systems AB, for the help with measurements on my first chips. I want to
thank Dr. Gunnar Björklund at the Ericsson Microelectronics Research Center for his indus-
trial competence and clear view on research issues. Further on, I want to thank the small Erics-
son Microelectronics group at Linköping with which I have been working.
A large portion of Thank You to my parents, Christina and Lars-Erik, who – I guess – have
always believed in (although not understood) what I have been doing. Thanks for all the com-
puters you have given me throughout the years.
Thank you, Ulrica, for still letting me come home after all long working nights.
7
Acknowledgment 8
Abbreviations and Acronyms
AC Alternating current
A/D Analog-to-digital
ADSL Asymmetric digital subscriber line
ADC Analog-to-digital converter
AFE Analog front-end
AHDL Analog high-level description language
AP Allpass
APK Amplitude-phase keying
ASK Amplitude-shift keying
ATM Asynchronous transfer mode
AWGN Additive white Gaussian noise
BER Bit error rate

bit Binary digit
BP Bandpass
BSIM Simulation model
CAP Carrierless amplitude and phase

CD Compact disc
CDMA Carrierless division multiplexing access
CFT Clock feedthrough
CMOS Complementary metal-oxide semiconductor
CO Central office
CPE Customer’s premises equipment
CSFR Clock-to-signal frequency ratio
D/A Digital-to-analog
DAC Digital-to-analog converter
9
Abbreviations and Acronyms 10
dB Decibel
dBFS Decibel with respect to the full scale level
DC Direct current
DCVSL Differential clocking style logic
DEM Dynamic element matching
DMT Discrete multi-tone
DR Dynamic range
DSL Digital subscriber line
DSP Digital signal processor
EDGE Enhanced data for GSM evolution

ENOB Effective number of bits
ERB Effective resolution bandwidth
FDM Frequency-division multiplexing

FEXT Far-end crosstalk
FFT Fast Fourier transform
FIR Finite-length impulse response
FRDEM Full randomization dynamic element matching
FS Full scale
FSK Freqsuency-shift keying
GCN General cubic network

GPRS General packet radio service
GSM Global system mobile telephony
GPIB General Purpose Interface Bus
GPRS General packet radio service
HD Harmonic distortion
HDL High-level description language
HDTV High-definition television
HP High pass
IFFT Inverse fast Fourier transform

IFIR Interpolated finite-length impulse response filter
IIR Infinite-length impulse response
IMD Intermodulation distortion
I/O Input / output
I/Q In-phase and quadrature-phase
ISDN Integrated services digital network
LP Lowpass
11 Abbreviations and Acronyms
LSB Least significant bit
LSI Large-scale integration
MASH Multi-stage
MF Multiple feedback
MOS Metal-oxide semiconductor
MOSFET Metal-oxide semiconductor field effect transistor
MSB Most significant bit
MTPR Multi-tone power ratio
NEXT Near-end crosstalk

NMOS N-channel metal-oxide semi-conductor
NOB Number of bits
NSDEM Noise-shaping dynamic element matching
NTF Noise transfer function
OFDM Orthogonal frequency division multiplexing

OP Operational amplifier
OSADC Oversampled A/D converter
OSDAC Oversampled D/A converter
OSR Oversampling ratio
OTA Operational transconductance amplifier
PAM Pulse-amplitude modulated

PAR Peak-to-average ratio or crest factor
PCB Printed circuit board
PGC Programmable gain control
PDA Personal digital assistant
PDP Power delay product
PLL Phase-locked loop
PMOS P-channel metal-oxide semi-conductor
POTS Plain old telephone service
PR Power ratio
PRBS Pseudo-random binary sequence
PRDEM Partial randomization dynamic element matching
PSD Power spectral density
PSK Phase-shift keying
QAM Quadrature amplitude modulation
R2Z Return-to-zero
RAM Random access memory
Abbreviations and Acronyms 12
ROM Read-only memory
RMS Root mean square
RX Receiver path
SC Switched capacitor
S/H Sample-and-hold
SUFR Signal-to-sample frequency ratio
SFDR Spurious-free dynamic range
SI Switched current
SNDR Signal-to-noise-and-distortion ratio
SNR Signal-to-noise ratio
SOC System on chip
SQNR Signal-to-quantization noise ratio
SR Slew rate
SR Set-reset
STF Signal transfer function
TDM Time-division multiplexing

THD Total harmonic distortion
TSPC True single-phase clocking
TX Transmission path
ULSI Ultra-high large-scale integration

UMTS Universal mobile telecommunications system
VDSL Very high data rate DSL

VLSI Very high large-scale integration
WCDMA Wideband CDMA
xDSL All/Any DSL

Notation and Nomenclature
In general, throughout the thesis, an analog output value (current, voltage,
or charge) from a D/A converter is denoted A . The input digital code/
word is denoted X and the corresponding bits in X are denoted b i .
x(t), x(τ), … Continuous-time signals
F {*} Fourier transformation of *
V (ω) Fourier transform of a continuous-time voltage v(t)
L{*} Laplace transformation of *
V (s) Laplace transform of a continuous-time voltage v(t)
x(k), x k, X (k) Discrete-time signals or sequences
X ( ωT ) Fourier transforms of a discrete-time signal x
X (z) z-transform (Laplace) of a discrete-time signal x
X (k) k -th Fourier coefficient of a discrete-time signal x
Eδ{*} Expectation value of * with respect to the entity δ
N ( µ, σ ) Normal distribution with mean µ and standard deviation σ
U (µ, σ) Uniform distribution with mean µ and standard deviation σ
Ã Expected output value
X̂ , Â Wanted value of X , A
X, A Average value of X , A
X̃ , x̃ AC varying part of the input code/word
fu Update frequency
fs Sample frequency (equal to update frequency, f s = f u )
fN Nyquist frequency, f N = f u ⁄ 2 = f s ⁄ 2
f O, u Oversampling frequency
ωT normalized angular frequency, sometimes also referred to as the angle

gm transconductance of a CMOS transistor
g ds output conductance of a CMOS transistor
For relative errors, we use ε and δ for absolute errors.
13
Notation and Nomenclature 14
Publications Related to the Author
Publications Related to Thesis Chapters
Most of the work presented in the thesis has previously been published in internal reports [1-
9], theses [10-11], journals [12-17], and in conference proceedings [18-33]. Major parts of the
work has been compiled in a text book [34]. However, in this thesis we present the background
to the results presented in these publications. Further, we have also extended some of the work
to cover more generalized problems. Some of the material has also resulted in patents [35-37].
Some of the results in publications – where the author is co-author – have been intentionally
left-out in the thesis and is to be more thoroughly examined in other students’ licentiate theses
and dissertations. The reader of this thesis is therefore also referred to references as “related
work” for further information on the topics.
List of Publications
Internal Reports at Linköping University
[1] H. Träff and J.J. Wikner, “Snapshot Sampling for Ultra-High Speed Data Acquisition,”
LiTH-ISY-R-1933, Linköping University, Sweden, March 1997.
[2] J.J. Wikner and N. Tan, “Modelling of DACs for Telecommunication,” LiTH-ISY-R-
1983, Linköping University, Sweden, Sept. 1997.
[3] M. Karlsson, O. Gustafsson, J.J. Wikner, T. Johansson, W. Li, M. Hörlin, and H. Ekberg,
“Understanding Multiplier Design Using ‘Overturned-Stairs’ Adder Trees,” LiTH-ISY-
R-2016, Linköping University, Sweden, Feb. 1998.
[4] M. Karlsson and J.J. Wikner, “Variations of ‘Fast Filter’ Implementations Using
Different DFL Descriptions in Mentor Graphics Design Tools,” LiTH-ISY-R-2xxx,
Linköping University, Sweden, May. 1998.
[5] J.J. Wikner and N. Tan, “Influence of Parameter Variations on the Performance of
Current-Steering DACs,” LiTH-ISY-R-2074, Linköping University, Sweden, Nov. 1998.
[6] J.J. Wikner and N. Tan, “Comparison of the Impact of Matching Errors on the
Performance of Current-Steering CMOS Digital-to-Analog Converters,” LiTH-ISY-R-
2075, Linköping University, Sweden, Nov. 1998.
15
Publications Related to the Author 16
[7] J.J. Wikner, Y. Gao, and N. Tan, “A 3.3V CMOS Oversampling D/A Converter for
DMT-ADSL,” LiTH-ISY-R-2076, Linköping University, Sweden, Nov. 1998.
[8] J.J. Wikner, “A Chipset Consisting of 15 CMOS Wideband D/A Converters for
Telecommunications. Design and Study,” LiTH-ISY-R-2xxx, Linköping University,
Sweden, Nov. 1998.
[9] J.J. Wikner, “Measurement and Simulations of a CMOS DAC Chipset,” LiTH-ISY-R-
2xxx, Linköping University, Sweden, Dec. 1998.
Theses
[10] J. J. Wikner, Measuring and Specification of Integrated Analog Circuits - with emphasis
on measuring Analog-to-Digital and Digital-to-Analog Converters, M.Sc. thesis,
Linköping University, Nov. 1996.
[11] J. J. Wikner, CMOS Digital-to-Analog Converters for Telecommunication Applications,
Linköping studies in science and technology, Thesis No. 715, ISBN 91-7219-277-1,
Linköping, Aug. 1998.
Journal Papers
[12] H. Träff and J.J. Wikner, “Snapshot Sampling for Ultra-High Speed Data Acquisition,”
Electronics Letters, vol. 33, no. 13, p. 1137-9, June 1997.
[13] N. Tan and J.J. Wikner, “A CMOS Digital-to-Analog Converter Chipset for
Telecommunications,” IEEE Magazine of Circuits & Devices, vol. 13, no. 5, p. 11-6,
Sept. 1997.
[14] J.J. Wikner and N. Tan, “Influences of Circuit Imperfections on the Performance of
DACs,” Analog Integrated Circuits and Signal Processing, no. 1, Jan. 1999.
[15] J.J. Wikner, Y. Gao, and N. Tan, “D/A Conversion Interface Design for DMT-ADSL
Applications,” IEEE Magazine of Circuits & Devices, vol. 1, no. 6, p. 7-13, Nov. 1998.
[16] J.J. Wikner and N. Tan, “Modeling of CMOS Digital-to-Analog Converters for
Telecommunication,” IEEE Transactions on Circuits and Systems II, vol..46, no. 5,
p. 489-99, May 1999.
[17] Y. Gao, J.J. Wikner, and H. Tenhunen, “Design and Analysis of an Oversampling D/A
Converter in DMT-ADSL Systems,” Analog Integrated Circuits and Signal Processing,
2001.
Conference Papers
[18] J.J. Wikner and N. Tan, “Influences of Circuit Imperfections on the Dynamic
Performance of DACs,” in Proc. 17th NorChip Conference, Tallinn, Estonia, Nov. 10-11,
1997.
[19] J.J. Wikner and N. Tan, “Modelling of CMOS Digital-to-Analog Converters for
Telecommunication,” in Proc. IEEE Symposium on Circuits and Systems 1998,
ISCAS’98, vol. 1, p. 25-8, Monterey, USA, May 30 - June 3, 1998.
Converter for DMT-ADSL Systems,” in Proc. IEEJ 3rd Analog VLSI Workshop,
AVLSIWS’99, Taiwan, May, 1999.
[21] J.J. Wikner, “Design and Implementation of Current-Steering CMOS DACs,” in Proc.
RVK’99 (Radiovetenskapskonferensen), Karlskrona, Sweden, June 1999.
17 Publications Related to the Author
[22] J.J. Wikner, “Simulation and Measurement of Two 3-5V CMOS Current-Steering
DACs,” in Proc. IEE 3rd International A/D and D/A Conference, p. 130-3, Glasgow,
Scotland, July 28, 1999
[23] K.O. Andersson and J.J. Wikner, “Modeling of the Influence of Graded Element
Matching Errors in CMOS Current-Steering DACs,” in Proc. 17th NorChip Conference,
Oslo, Norway, Nov. 8-9, 1999.
[24] N.U. Andersson and J.J. Wikner, “Comparison of Different Dynamic Element Matching
Techniques for Wideband CMOS DACs,” in Proc. 17th NorChip Conference, Oslo,
Norway, Nov. 8-9, 1999.
[25] N.U. Andersson and J.J. Wikner, “A Strategy of Implementing Dynamic Element
Matching in Current-Steering DACs,“ in Proc. IEEE 2000 Southwest Symposium on
Mixed-Signal Design, SSMSD’00, p. 51-6, San Diego, CA, USA, Feb. 2000.
[26] J.J. Wikner and M. Vesterbacka, “D/A Conversion with Linear-Coded Weights,” in Proc.
IEEE 2000 Southwest Symposium on Mixed-Signal Design, SSMSD’00, p. 61-6, San
Diego, CA, USA, Feb. 2000.
[27] J.J. Wikner and M. Vesterbacka, “Characteristics of Linear-Coded D/A Converters,” in
Proc. IEEE 2000 Southwest Symposium on Mixed-Signal Design, SSMSD’00, p. 67-72,
San Diego, CA, USA, Feb. 2000.
[28] K.O. Andersson and J.J. Wikner, “Characterization of a CMOS Current-Steering DAC
using State-Space Models,“ in Proc. IEEE 2000 Midwest Symposium on Circuits and
Systems, MWSCAS’00, Lansing, MI, USA, Aug. 2000.
[29] M. Vesterbacka and J.J. Wikner, “Characteristics of Linear-Coded D/A Converters,” in
Proc. IEEJ 4th Analog VLSI Workshop, AVLSIWS’00, Stockholm, Sweden, June 2000.
[30] M. Vesterbacka, M. Rudberg, J.J. Wikner, and N.U. Andersson, “Dynamic Element
Matching in D/A Converters with Restricted Scrambling,” in Proc. IEEE 7th
International Conference on Electronics, Circuits, and Systems, ICECS’00, Beirut,
Lebanon, Dec. 17-20, 2000.
[31] K.O Andersson, N.U. Andersson, and J.J. Wikner, “Spectral Shaping of DAC
Nonlinearity Errors through Modulation of Expected Errors,” to appear in Proc. IEEE
2001 International Symposium on Circuits and Systems, ISCAS’01, Sydney, Australia,
May 6-9, 2001.
[32] M. Vesterbacka and J.J. Wikner, “Design of Encoders for Linear-Coded D/A
Converters,” to appear in Proc. IEEE 2001 International Symposium on Circuits and
Systems, ISCAS’01, Sydney, Australia, May 6-9, 2001.
[33] M. Rudberg, M. Vesterbacka, N.U. Andersson, and J.J. Wikner, “Glitch Minimization
and Dynamic Element Matching in D/A Converters,” in Proc. IEEE 7th International
Conference on Electronics, Circuits, and Systems, ICECS’00, Beirut, Lebanon, Dec. 17-
20, 2000.
Book
[34] M. Gustavsson, J.J. Wikner, and N. Tan, CMOS Data Converters for Communications,
Kluwer Academic Publishers, Jan. 2000.
Patents
[35] N. Tan, J. Erlands, and J.J. Wikner, “A Differential Line Driver“, Swedish patent
9800635-6 and U.S. patent pending, 1998.
Publications Related to the Author 18
[36] J.J. Wikner and M. Vesterbacka, “D/A Conversion Method and D/A Converter”, Swedish
patent 9903500-8, U.S. patent pending, Oct. 1999.
[37] N. U. Andersson, M. Vesterbacka, J. J. Wikner, and M. Karlsson Rudberg, “Improvement
of segmented DACs,” Swedish patent 0001917-4 U.S. patent pending, May 2000.
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Integrated Circuits and the Digital/Analog Interface 4

1.1.1 Digital Circuits 5
1.1.2 Analog Circuits 6
1.1.3 Mixed-Signal Circuits 8
1.2 Communication Circuits 8
1.2.1 Modulation Schemes 9
Quadrature Amplitude Modulation (QAM)
1.2.2 Channel Models 10
1.2.3 Transmission Modes 11
1.3 Digital Subscriber Line Technique (DSL) 11
1.3.1 DSL Analog Front End (AFE) 12
1.3.2 Discrete Multi-Tone (DMT) Signals in DSL 13
Frames and cyclic prefix
1.3.3 Spectral Requirements for ADSL and VDSL 20
1.3.4 The Twisted-Pair Channel 20
Crosstalk
1.4 Requirements on D/A Converters for xDSL 22
1.5 Data Converter Applications 23
2 Introduction to D/A Conversion . . . . . . . . . . . . 25
2.1 Introduction 25
2.2 The Ideal D/A Converter 26
2.2.1 Ideal Transfer Function 28
2.2.2 Codes for D/A Conversion 29
2’s complement
Offset binary
Signed-digit
“Walking one”
Thermometer code
Linear code
2.3 Static Performance 31
2.3.1 Quantization or Truncation Noise 31
2.3.2 Offset Error 34
2.3.3 Gain Error 35
2.3.4 Differential (DNL) and Integral Nonlinearity (INL) 37
2.3.5 Monotonic Behavior 39
2.3.6 Nonuniform Quantization 40
i
Table of Contents ii
2.4 Dynamic Performance 42

2.4.1 Nonlinear Settling 44
2.4.2 Glitches 45
2.4.3 Clock Feedthrough (CFT) 47
2.5 Frequency-Domain Measures 48
2.5.1 Harmonic Distortion (HDk) 50
2.5.2 Total Harmonic Distortion (THD) 50
2.5.3 Signal-to-Noise Ratio (SNR) 50
2.5.4 Signal-to-Noise and Distortion Ratio (SNDR) 50
2.5.5 Spurious-Free Dynamic Range (SFDR) 51
2.5.6 Effective Number Of Bits (ENOB) 51
2.5.7 Multi-Tone Power Ratio (MTPR) 51
2.5.8 Intermodulation Distortion (IMD) 52
2.5.9 Linearity as Function of Amplitude and Frequency 52
Dynamic range (DR)
Effective resolution bandwidth (ERB)
2.5.10 Peak-to-Average Ratio (PAR) 54
3 D/A Converter Architectures . . . . . . . . . . . . . 55
3.1 Introduction 55
3.2 Nyquist-Rate D/A Converters 56
3.3 Interpolating D/A Converters 57
3.3.1 Gain in Resolution Using Interpolation 60
3.4 Oversampling D/A Converters (OSDACs) 62
3.4.1 Noise-Shaping Modulators 62
Interpolative or multiple-feedback modulator
3.4.2 Improvement in Resolution Using Noise-Shaping 66
3.5 DAC Architectures 67
3.5.1 Binary-Weighted DAC Architecture 68
3.5.2 Thermometer-Coded DAC Architecture 68
3.5.3 Direct Encoded DAC Architecture 69
3.5.4 Linear-Coded DAC Architecture 70
3.5.5 Hybrid DAC Architectures 70
3.5.6 Algorithmic DAC Architecture 71
Pipelined algorithmic DAC
3.6 Common DAC Circuit Implementations 72
3.6.1 Current-Steering DAC 73
3.6.2 Charge-Redistribution DAC 74
3.6.3 R-2R Ladder DAC 74
3.6.4 Resistor-String DAC 75
3.6.5 Switched-Current Algorithmic DAC 75
3.7 DAC Comparison 77
iii Table of Contents
4 Behavioral-Level Models for Current-Steering,

Nyquist-Rate D/A Converters . . . . . . . . . . . . . 81
4.1 Introduction 81
4.2 Unit-Element Approach 84
4.2.1 Matching Errors of Unit Current Sources 85
4.3 Limited Output Impedance 87
4.3.1 Settling-Time Error with Ideal Current Sources 95
4.3.2 Static Error Current 98
4.3.3 DNL and INL as Function of the Output Resistance 98
4.3.4 SNDR as Function of the Output Resistance 100
4.3.5 SFDR as Function of the Output Resistance 103
4.3.6 Influence of Parasitic Resistance 107
4.3.7 SNDR and SFDR as Functions of the Output Impedance 108
4.3.8 Influence of Parasitic Impedance 109
4.4 Influence of Circuit Noise 110
4.5 Current Source Mismatch 113
4.5.1 SNDR as Function of the Stochastic Mismatch Errors 115
4.5.2 SFDR as Function of the Stochastic Mismatch Errors 117
Influence of segmentation and thermometer code
4.5.3 SNDR and SFDR as Function of the Graded and
Correlated Mismatch Errors 121
4.6 Glitches and Influence of Bit Skew 122
5 Current-Steering D/A Converters . . . . . . . . . . 127
5.1 Introduction 127

5.2 Current-Steering DAC Architectures 128
5.2.1 Flat and Folded Array Structures 129
5.2.2 Segmented Structures 131
5.2.3 Encoded Array Structures 133
5.3 Practical Design Considerations 134
5.3.1 Unit Current Source 134
Output impedance
Matching
5.3.2 Current Switches 139
On-resistance
Clock feedthrough (CFT)
Switching signals
Switch memory
Segmentation circuits
5.3.4 Mixed-Signal Design 145
Table of Contents iv
5.4 CMOS Current-Steering DACs for VDSL Applications 147

5.4.1 Current Sources and Bias 147
Bias and supply network
Matching considerations
5.4.2 Current Switches 149
5.4.4 Chip Implementations 150
5.5 Measurement Results 150
5.5.1 Measurement Setup and Techniques 152
Test signal generation
5.5.2 Measured Results 154
Single-ended vs. differential outputs
Comparison of two generation DACs
5.5.3 Measured, Calculated, and Simulated Results 157
General considerations
Output impedance
Device matching
Measurement conclusions
6 Oversampling D/A Converters. . . . . . . . . . . . 161

6.2 OSDAC Building Blocks 161
6.2.1 Interpolator and Interpolation Filters 164
Cascaded accumulator structure
6.2.2 Noise-Shaping Modulator 169
Multiple-feedback modulators
Multi-stage modulators (MASH)
6.2.3 M-bit DAC 174
One-bit DAC and semi-digital FIR filter
6.2.4 Interpolated Semi-Digital FIR Filter 176
6.2.5 Image-Rejection and LP Filter 177
6.3 Simulation Results of OSDAC Blocks 178
6.3.1 DMT-ADSL Input Signal 180
6.3.2 Interpolation Filters 180
6.3.3 Noise-Shaping Modulators 182
6.3.4 Semi-Digital FIR Filters and Image-Rejection Filter 184
6.4 A CMOS Current-Steering 5th-Order
OSDAC for DMT-ADSL 185
6.4.1 Semi-Digital FIR Filter 185
Unit current source
Current switches
D-latches
Filter taps
6.4.2 Complete Chip Layout 189
v Table of Contents
7 Special Techniques for Enhanced D/A Conversion 191

7.2 Nonlinear Error Compensation 192
7.2.1 Pre-Distortion Circuits 193
7.2.2 Combinations and Variations on Linearization Techniques 196
7.3 Current Source Calibration 197
7.4 Dynamic Element Matching (DEM) Techniques 199
7.4.1 Dynamic Randomization 200
7.4.2 Dynamic Element Matching (DEM) with Encoder 202
Full-randomization DEM (FRDEM)
Partial-randomization DEM (PRDEM)
Noise-shaping DEM (NSDEM)
Performance comparison
7.4.3 Dynamic Randomization with Reduced Glitching 205
Generalized cubic network (GCN)
Hardware Efficient dynamic randomization with reduced glitching
7.5 Special Codes in DACs 208
7.5.1 Linear-Coded DACs 209
Weight distribution
Encoder complexity
Glitch performance
Dual linear-coded approach
Layout consideration
7.5.2 Signed-Digit Coded DACs 215
7.5.3 Return-to-Zero Code 217
8 Appendices . . . . . . . . . . . . . . . . . . . . . . 219

8.2 Resolution Improvement Through Noise Shaping 219
8.3 SNDR and SFDR as Functions of Output Conductance 221
8.4 Fourier Series Coefficients for the MSBs of Sinusoid Inputs 228
Table of Contents vi
List of Figures
1 Introduction
1.1, p. 2: Data converters as interface between the analog and digital domain.
1.2, p. 8: Switching noise from digital circuits is spreading through the substrate and affecting the
sensitive analog circuits.
1.3, p. 9: Illustration of a communication system.
1.4, p. 10: 16-QAM code constellation in the IQ-space. The point (3,1) is high-lighted.
1.5, p. 10: Example of a model of a memoryless Gaussian channel.
1.6, p. 11: Illustration of different transmission modes. (a) simplex, (b) half-duplex, and (c) full-
duplex.
1.7, p. 12: Illustration of a DSL communication system.
1.8, p. 13: DSL analog front-end.
1.9, p. 14: Examples on echo cancelling techniques (dashed). On (a) the analog side, (b) digital side,
(c) using and (d) passive hybrid.
1.10, p. 15: Example of a multi-tone signal in the (a) time and (b) frequency domain
1.11, p. 17: Example of a multi-tone signal with (a) high and (b) low PAR.
1.12, p. 18: Illustration of Gaussian distributed amplitude levels of (a) high- and (b) low-PAR DMT
signals.
1.13, p. 18: Standard deviation of amplitude distribution as function of PAR for a multi-tone signal.
1.14, p. 19: Clipping probability as function of the PAR.
1.15, p. 19: Use of cyclic prefix in transmission in batches.
1.16, p. 20: Transmitted power spectral density specifications on (a) CO and (b) CPE side for ADSL.
1.17, p. 22: Input impedance of a twisted-pair cable as function of frequency and length.
1.18, p. 23: Overview of application areas as function of resolution and sample frequency.
2 Introduction to D/A Conversion

2.1, p. 26: Alternative representations of ideal DACs.
2.2, p. 27: Image-rejection filter (LP) is used at the output of the DAC to reconstruct the signal.
2.3, p. 27: Output signal spectrum with images at centers of the update frequency.
2.4, p. 28: Output amplitude levels as function of the input digital codes.
2.5, p. 32: Transfer function (a) and quantization error (b) for a 3-bit DAC when ramping the input.
Solid lines illustrate the actual behavior and dashed lines the ideal behavior.
2.6, p. 34: Output amplitude levels as function of the input digital codes with (dashed) and without
(solid) errors for a 3-bit DAC.
2.7, p. 35: Characteristics of (a) linear and (b) nonlinear DAC gain error.
2.8, p. 37: (a) Nonideal transfer characteristics illustrating INL and DNL errors in a 3-bit DAC and
(b) compensated transfer characteristics.
2.9, p. 39: (a) DNL and (b) INL for the transfer function shown in Fig. 2.8.
2.10, p. 40: Example of a transfer function of a nonmonotonic DAC.
2.11, p. 40: DC transfer characteristics of a DAC with nonuniform quantization.
2.12, p. 43: Actual output signal and ideal output signal (dashed) of a DAC.
2.13, p. 46: Glitch modeled as a pulse with height Xg and duration Tg.
2.14, p. 48: Illustration of the effect of clock feedthrough on MOS switches. (a) MOS switch and (b)
typical output signal.
2.15, p. 49: Frequency spectrum of a single-tone output signal from a nonlinear DAC with typical
frequency-domain measures.
2.16, p. 49: Frequency spectrum of a (a) dual-tone and (b) multi-tone output signal from a nonlinear
DAC with typical frequency-domain measures.
vii
List of Figures viii
2.17, p. 53: Typical SNDR and SFDR vs. amplitude level for a 14-bit DAC.
2.18, p. 53: Measured SFDR as function of update and signal frequencies.
3 D/A Converter Architectures

3.1, p. 56: (a) Output spectrum from a Nyquist-rate DAC. The images are centered at multiples of
the update frequency. (b) DAC with an image-rejection filter (LP).
3.2, p. 57: Sinc attenuation of the output signal as function of the signal to sampling frequency ratio.
3.3, p. 58: Interpolator without (a) and with (b) filters (interpolation filters).
3.4, p. 59: Illustration of interpolation of order 4. The original spectrum, the interpolated spectrum
with filtering (dashed), and the final interpolated signal are shown.
3.5, p. 60: Interpolation together with lower-resolution DAC where the N-M LSBs are discarded.
3.6, p. 62: OSDAC including interpolation, modulation, and filtering.
3.7, p. 63: Different sigma-delta modulators. (a) Signal feedback and (b) error feedback. In (c) and
(d) we find the respective noise models for the quantization error in (a) and (b),
respectively.
3.8, p. 64: First-order modulators using (a) signal- and (b) error-feedback.
3.9, p. 65: Power spectral density for 1st-, 2nd-, and 3rd-order modulators.
3.10, p. 65: Interpolative or multiple-feedback modulator structure.
3.11, p. 67: Simulated achievable ENOB as function of the modulator order and oversampling ratio.
3.12, p. 68: General algorithm for converting codes.
3.13, p. 69: Illustrations of the (a) binary-weighted, (b) thermometer-coded, and (c) direct encoded
DAC architectures.
3.14, p. 71: Hybrid DACs use a combination of a number of different types of DACs.
3.15, p. 71: Schematic view of an algorithmic DAC.
3.16, p. 72: Pipelined algorithmic DAC.
3.17, p. 73: An N-bit binary-weighted current-steering DAC with output buffer.
3.18, p. 74: Example of an N-bit charge-redistribution DAC without reset phase.
3.19, p. 75: An N-bit R-2R ladder DAC.
3.20, p. 76: An N-bit resistor string DAC where M=2N-1.
3.21, p. 76: A switched-current (SI) implementation of an algorithmic DAC.
3.22, p. 78: Reported measured performance of different DAC types. In (a) the performance vs. the
update frequency and in (b) vs. the signal frequency (bandwidth).
4 Behavioral-Level Models for Current-Steering, Nyquist-Rate D/A Con-

verters
4.1, p. 83: An N-bit binary weighted current-steering DAC. The output is terminated over a 50-W
load.
4.2, p. 84: (a) Symbols for two capacitors. (b) Unit element capacitors. (c) Individual layout. (d)
Even distribution of unit element capacitors.
4.3, p. 85: Variation of oxide thickness over the wafer and the individual chips. The thickness may
vary significantly over the wafer, but may be approximated by a plane for small
dimensions.
4.4, p. 86: PMOS implementation of a unit current source.
4.5, p. 88: Generalized view of a differential-mode current-steering DAC.
4.6, p. 89: Linearized model of the unit current source (a) with and (b) without parasitics from
switches and interconnection wires.
4.7, p. 90: Change of input signal causes additional sources to be connected to the output. We find
the situation before (a) and after (b) the switching instant.
4.8, p. 94: Output (a) step response for the positive output with ideal step shown (dashed) and (b)
corresponding error current.
4.9, p. 95: Output spectra for (a) lower and (b) higher signal frequencies.
ix List of Figures
4.10, p. 95: Simulated SFDR as function of signal frequency.
4.11, p. 98: (a) Single-ended and (b) differential output spectra with a conductance ratio of 10–8.
4.12, p. 100: Simulated DNL and INL as a function of input code for a resistance ratio of 108.
4.13, p. 102: Simulated (solid) and calculated (dashed) (a) single-ended and (b) differential SNDR as
function of the conductance ratio for 10-, 12-, and 14-bit DACs.
4.14, p. 103: Simulated (solid) and calculated (dashed) single-ended SNDR as function of the AC
level.
4.15, p. 106: Simulated (solid) and calculated (dashed) (a) single-ended and (b) differential SFDR as
4.16, p. 107: (a) Model of the current source at bit position k with parasitic resistance, Rpar,k, from
switches and internal wires and (b) modified model.
4.17, p. 109: Measured and simulated SFDR as function of the signal and update frequencies.
4.18, p. 110: Unit current source with noise current source, diu,m.
4.19, p. 112: Simulated (solid) and calculated (dashed) single-ended SNR as function of the the LSB
current for a 14-bit DAC.
4.20, p. 114: Modeling of current source with error current source, DIu,m.
4.21, p. 116: Output spectrum for a 14-bit DAC with approximate mismatch error standard deviation
of 1.5 %.
4.22, p. 117: Calculated (dashed) and simulated (dashed) SNDR as function of the mismatch error
standard deviation for 10-, 12-, and 14-bit DACs.
4.23, p. 119: Transient behavior of the individual bits when applying a full-scale sinusoid.
4.24, p. 120: Simulated SNDR as function of the input amplitude for mismatch standard deviation of
5%.
4.25, p. 121: Calculated and simulated SFDR as function of the mismatch for 10-, 12-, and 14-bit
DACs.
4.26, p. 122: Layout of the unit current sources in a folded array structure.
4.27, p. 124: Model of timing uncertainty. The ideal switching signal (dashed) is compared with the
actual signal (solid). In (a) a linearized model and in (b) a box model.
4.28, p. 125: Simulated output spectrum for (a) ideal signal, (b) randomly varying glitch model, and
(c) fixed glitch model.
5 Current-Steering D/A Converters

5.1, p. 128: Principle of an N-bit current-steering DAC.
5.2, p. 129: (a) “Flat” and (b) “folded” array layout of unit current sources.
5.3, p. 130: Influence of gradients for a (a) flat layout approach on the (b) INL.
5.4, p. 131: Influence of gradients for a (a) distributed layout approach on the (b) INL.
5.5, p. 132: Illurstration of a segmented current source array. The M binary MSBs are encoded into T
= 2M–1 thermometer coded bits.
5.6, p. 132: Estimated glitch power as function of the number of segmented bits in a 14-bit DAC.
5.7, p. 133: Unit current source array with decoding circuits.
5.8, p. 134: Schematic view of PMOS current sources using (a) single transistor and (b) single
cascode, and (c) double cascode.
5.9, p. 136: Simulated output impedance of three different unit current source configurations.
5.10, p. 138: Simulated output impedance of the unit current sources as function of the (a) supply
voltage and (b) output DC voltage level.
5.11, p. 139: Model of the voltage supply wire connected to a number of DAC current sources and the
drop of accuracy in the currents.
5.12, p. 139: Differential current switch as (a) circuit model and (b) MOS transistor implementation.
5.13, p. 141: Simulated switch on-impedance as function of the (a) supply voltage and (b) output DC
voltage.
5.14, p. 141: Transmission gates used as current switches.
5.15, p. 142: Dummy transistor used in the switch to reduce the effect of channel charge injection.
5.16, p. 143: (a) Wanted switch signals for a differential current switch and (b) and (c) show possible
List of Figures x
circuit implementations generating overlapping signals.
5.17, p. 144: Iterative implementation of a binary-to-thermometer encoder. Note that there is AND
and OR gates in parallel.
5.18, p. 145: Example of a 2-to-3 encoder with AND-OR pair (a). Same encoder implemented by (b)
2-2 multiplexers. (c) Pass-transistor implementation of the 2-2 multiplexer.
5.19, p. 145: Shielding of sensitive analog blocks by using guard rings.
5.20, p. 146: Shielding of sensitive analog signal wires (a) by using ground wires and (b) also using n-
doped substrate layer in the p-substrate underneath the wires.
5.21, p. 146: Separation of analog and digital pins at the board level.
5.22, p. 148: Layout view of a (a) double-cascoded and (b) single-cascoded PMOS unit current source.
5.23, p. 149: (a) Cascoded and (b) wideswing PMOS current mirror bias circuits.
5.24, p. 150: Layout view of a differential current switch for the LSBs.
5.25, p. 151: Chip photograph of the 14-bit current-steering 0.60-mm CMOS DAC.
5.26, p. 151: Chip photograph of the 12-bit current-steering 0.25-mm CMOS DAC.
5.27, p. 153: View of a measurement system.
5.28, p. 154: Output amplitude spectra from a 14-bit DAC with (a) ideal input signal, (b) clipped signal
at 99.9% of its maximum value, and (c) repeated signal but with its period truncated.
5.29, p. 155: Measured differential output spectra from (a) DAC A and (b) DAC B.
5.30, p. 156: Measured SFDR for different update frequencies. The results for DAC A is shown in (a)
and for DAC B in (b). The supply voltages are 3.3 and 5 V.
5.31, p. 156: Measured SFDR for DAC C as function of the signal and update frequency.
5.32, p. 157: Comparison of the measured SFDR from DAC A and C.
5.33, p. 157: Part of current source array for the (a) second and (b) third generation DAC with double
cascode current sources.
5.34, p. 158: (a) Measured power in the fundamental, 2nd, and 3rd harmonics vs. signal power for a
14-bit DAC and in (b) derived harmonic distortion from the results in (a).
5.35, p. 159: (a) Measured output spectrum for a 14-bit DAC. Update frequency is 25 MHz and signal
frequency 670 kHz. The input amplitude level is –15 dBFS.
5.36, p. 160: Simulated output spectrum for a 14-bit DAC with similar conditions as used for the
measured DAC result in Fig. 5.35.
6 Oversampling D/A Converters

6.1, p. 162: Generalized OSDAC architecture including interpolator, modulator, DAC, and analog
LP filter.
6.2, p. 163: Example spectra for different signals in an OSDAC with OSR = 8: (a) Original input
spectrum, (b) interpolated spectrum, (c) filtered interpolated signal, (d) introduction of
noise by the modulator, (e) same as (d), but with logarithmic axis, and (f) final output
signal.
6.3, p. 165: One-stage FIR interpolation filter. The delay To is related to the oversampling frequency.
6.4, p. 165: Principle description of multi-stage interpolation filtering.
6.5, p. 166: Illustration of normalized sinc-weighting through S/H interpolation.
6.6, p. 167: Interpolation filter structure using differentiators, D(z), and accumulators, A(z).
6.7, p. 168: (a) A filter is compensating the large loss within the passband due to the sinc filters. (b)
Simulated characteristics of the sinc filter (dotted) and the result with compensation filter
(solid).
6.8, p. 169: Basic structure of signal- and error-feedback modulators.
6.9, p. 170: Simulated modulator output (solid) for ramped input (dashed) for (a) 1st and (b) 2nd
order.
6.10, p. 171: General multiple-feedback modulator of higher order (N).
6.11, p. 171: General multiple-feedback modulator with feedforward coefficients, c.
6.12, p. 173: Root locus for a 4th-order MF modulator without the ai feedback zeros.
6.13, p. 174: Two-stage 4th-order modulator structure using two 2nd-order modulators.
xi List of Figures
6.14, p. 175: DC transfer characteristcs of a one-bit DAC with (solid) and without (dashed) matching
errors.
6.15, p. 175: Cascaded one-bit DACs forming a K-tap FIR filter structure.
6.16, p. 177: Magnitude responses for an FIR filter and an interpolated (4 times) FIR filter. The IFIR
has a 5-dB offset for illustration.
6.17, p. 178: Images are rejected and noise attenuated with (a) continuous-time filter and (b) additional
discrete-time filters.
6.18, p. 179: Filtering functions in the of the OSDAC output signal, illustrated in the frequency
domain.
6.19, p. 181: 256-tone DMT Input signal.
6.20, p. 181: Magnitude responses of (a) Cauer and (b) FIR interpolation filters for OSR = 16 and 32.
Solid lines indicate the 0.5-dB specification on the passband ripple and dashed lines the
0.1-dB specification.
6.21, p. 183: Examples on modulator output spectra for single-tone inputs. Modulator orders are (a) 3,
(b) 4, (c) 5 for OSR = 32 and in (d) a 5th-order modulator for OSR = 16.
6.22, p. 184: Magnitude response of the semi-digital FIR filter, SD FIR I, (a) with and (b) without
truncated coefficients.
6.23, p. 186: (a) Current-steering implementation of a semi-digital filter with coefficient length K. (b)
Differential current switches where negative coefficients are realized by cross connecting
the outputs.
6.24, p. 188: Impulse response from a circuit-level simulation of the semi-digital FIR filter.
6.25, p. 189: Transistor schematics of (a) P- and (b) N-type latches.
6.26, p. 189: Die photograph view of the OSDAC with modulator and semi-digital FIR filter.
7 Special Techniques for Enhanced D/A Conversion

7.1, p. 192: Error cancellation by using an inverse function (a) at the input, (b) at the output, and (c)
compensating DAC in parallel.
7.2, p. 195: Use of comparators in a hardware-efficient pre-distortion circuit.
7.3, p. 196: Output spectra from a nonlinear DAC without (a) pre-distortion, and (b) through (d) with
pre-distortion. In (b) we use complete inverse function, (c) comparator pre-distortion, and
(d) pre-distortion with Taylor expansion.
7.4, p. 197: Use of loops and adaptation for pre-distortion circuits.
7.5, p. 198: Use of signal-feedback sigma-delta modulators to spectrally shape the influence of
nonlinear errors.
7.6, p. 198: Example on circuit solution to calibrate the unit current sources during (a) calibration and
(b) operation phases.
7.7, p. 200: Randomization of thermometer-coded bits in a DAC.
7.8, p. 202: Averaged output spectra from an 8-bit thermometer-coded DAC (a) without and (b) with
randomization.
7.9, p. 202: Simple binary-to-thermometer encoder to be used before the randomizer.
7.10, p. 203: Block view of a full randomization DEM architecture.
7.11, p. 203: Switching block used in randomization trees.
7.12, p. 204: Block view of a partial randomization DEM architecture.
7.13, p. 206: State-controlled DEM to minimize glitches.
7.14, p. 207: Segmentation and scrambling 3-to-7 binary-to-thermometer encoding circuit
implemented by a GCN.
7.15, p. 208: Hardware-efficient switching block for glitch reducing in DEM.
7.16, p. 210: Total number of weights for different codes in DACs as function of the number of bits.
7.17, p. 212: Illustration of (a) the 5 linear-coded weights in a 4-bit converter and (b) representation of
the number 10. Un-filled circles represent unused unit weights.
7.18, p. 213: Simulated glitch behavior for a ramped input in (a) binary-weighted and (b) linear-coded
DAC.
7.19, p. 214: Simulated normalized glitch power for different DAC configurations.
List of Figures xii
7.20, p. 215: (a) Complementary or the dual representation of the number 10 and (b) simulated glitch
behavior for a ramped input in dual linear-coded DAC.
7.21, p. 216: Use of signed-digit coded DAC.
7.22, p. 217: Illustration (a) of the return-to-zero code and (b) its effect on the output signal.
8 Appendices
8.1, p. 229: Transient behavior of the individual bits when applying a full-scale sinusoid.
List of Tables
1 Introduction
1.1 Some performance measures in the different operation regions. is the channel-length modula-
tion factor, q is the electron charge, k is the Bolzmann constant, and T is the absolute tempera-
ture. 7
1.2 Specifics of different xDSL standards compared to voice channel techniques and ISDN. The
bandwidths are given by approximate numbers. 12
1.3 Spectral requirements on transmitted signal for ADSL at both CO and CPE sides. 21

2.1 Some digital codes used for D/A conversion. 29

3.1 Different digital interpolation filter orders for attenuation of images by more than 60 dB. 59
3.2 Different continuous-time image-rejection filter orders for stop-band attenuation of 60 dB. 60
3.3 Reported performance of mainly telecommunication DACs. 79
4 Behavioral-Level Models for Current-Steering, Nyquist-Rate D/A Con-

verters

5.1 Data summary of some implemented DACs. 152

6.1 Feedback coefficients for different multi-feedback modulator orders for OSR=32. 173
6.2 Achievable ENOB for different OSDAC configurations. 180
6.3 Interpolation filter orders for different structures and OSR. 181
6.4 Modulator feedback coefficients used in the OSDAC simulations. 182
6.5 Semi-digital FIR filter orders for different OSR and stopband attenuation. 184

7.1 Decision table for hardware efficient DEM. 208
8 Appendices
xiii
List of Tables xiv
1 Introduction
Throughout the years there has been an increase of demand for high-speed communications.
During the last decades, the Internet and mobile terminal usage has increased dramatically. In
our part of the world, they are now to a large extent every man’s property. The offered trans-
mission data rate on ordinary telephone wires, i.e., voice-band modem, has been pushed up to
approximately 56 kbit/s. This achievable limit is basically set by the noise and linearity of the
channel – the line quality –, but mostly by the limited bandwidth provided by the plain old
telephone service (POTS), which typically is in the order of 3.1 to 5 kHz [1, 2]. To overcome
this limited data rate, we can use dedicated wires with higher bandwidth, e.g., cable-TV net-
work, integrated service digital network (ISDN), ethernet, wireless access through radio,
fibres, or a higher bandwidth on the available telephone wires has to be offered. The latter is
the concept of the digital subscriber line (DSL) standards. With filters we split the frequency
range into the DC to 4-kHz band for POTS and the frequencies above 4 kHz for DSL. The
DSL standards allow data-rates up to several tens of Mbit/s [1, 2, 3] dependent on the length,
physical dimensions, and quality of the line. The increase of bandwidth and transmission
speed does not only put high demands on the quality of the telephone wire itself, i.e.,
crosstalk, noise, and interference. The interfacing circuits and front-ends in the modems and
base stations have to be very carefully designed and constructed. Some of the bottle-necks in a
DSL front-end are the analog circuits and the data converters, since the requirements on lin-
earity and low noise are very demanding [1, 2].
The same kind of problems with too low bandwidth have arosen for mobile terminals (mobile
phones). In the common, established global system mobile telephony (GSM) standard the
maximum transmission data rate is approximately 9.6 kbit/s. New wideband radio standards,
e.g., EDGE, UMTS, WCDMA, GPRS, will overcome the limitation, but still some of them
only allow rates up to 160 kbit/s [4].
This thesis overviews the interface between the digital and analog domains. Within these
interfaces, we find the analog-to-digital converter (ADC) and digital-to-analog converter
(DAC). These data converters are not only used for conversion of audio via microphone or
loudspeakers, video via camera or display, into information that the computer or digital signal
processor (DSP) can handle. In Fig. 1.1 we illustrate the concept of the interfacing ADC and
1
2 Introduction
DAC between the analog and digital domains. The data converters are also used for data trans-
mission via a channel, where the channel is either wireline or wireless (radio). Typically, the
data (signal) is modulated onto a carrier according to some scheme. The signal is then sent
over the channel with the carrier. The receiver will demodulate and extract the data (signal).
The modulation can be done in both the digital and analog domain dependent on application
and feasability.
ADC
g
D
lo
ig
a
An
ita
DAC
l
Figure 1.1 Data converters as interface between the analog and digital domain.
A low power dissipation of the electronic circuits is very important, both in mobile terminals
to increase the stand-by time, but also in the base stations where the number of relatively large
and expensive cooling devices should be kept at a minimum. The newtork operators want a
single base station to be able to concurrently handle as many channels (users) as possible. The
same holds for the size of the modems (line cards) in the central office (CO) in DSL systems.
This also implies that in both cases the circuits should be low-cost and occupy a small vol-
ume, hence the circuits should be highly integrated. Both issues, power dissipation and small
area, are handled by integrating as much as possible in semi-conductors and preferably in as
few chips as possible. In this way, the off-chip communication is reduced, i.e., the intercon-
nection wires become much shorter and the power dissipation can be reduced through less
driver circuits. Supply voltages can be shared, etc. To integrate as many components as possi-
ble in as few chips as possible implies, today, that a CMOS technology should be used due to
its scalability and low-power operation [5]. In terms of linearity and low noise, the CMOS
technology might not be the best choice for analog circuits, whereas the bipolar or BiCMOS
technology might be a better choice due to the higher gain of bipolar devices [7, 8]. However,
most of the research today on analog circuits is focused on CMOS, so that they can be imple-
mented together with digital circuits in a mixed-signal environment. There is a rapid perfor-
mance increase of the CMOS processes and the achievable unity-gain frequency ( f T ) is soon
in the same order as for the bipolar transistors [8].
This thesis focuses on the study and design of – analysis and synthesis – of CMOS digital-to-
analog converters in analog front-ends (AFEs) for wideband and high-resolution applications.
As main target specifications, the asymmetric and very high data-rate DSL (ADSL and
VDSL) applications were chosen. The specified transmission bandwidths are 1.104 MHz and
11.04 MHz, respectively, and the required resolution is in the order of 12-14 bits [1, 2, 3].
(Actually, the specifications on the data converters in for example wideband radio are very
similar to those of the VDSL [4]).
We discuss models of the DACs which helps us understand the fundamental limits on perfor-
mance. The models are implemented in a higher-level language, such as Matlab which
increases the flexibility (in terms of architecture modification and signal generation and/or
3
analysis) over circuit-level languages, such as Spice or Spectre. The simulation time can be
reduced from several days to a couple of minutes. The behavioral-level models are of course
not as detailed and accurate as the circuit-level models, but they give us a guideline for the
design.
Limits on the DAC performance are typically circuit noise, mismatch between internal refer-
ences or weights, nonlinear analog circuits, delay skew between switches, and parasitic resis-
tance and capacitance [7, 9]. How these nonidealties affect the performance are addressed in
this thesis and we discuss different approaches to reduce the influence of the errors. In gen-
eral, the errors or limitations can be considered to be of two types; static and dynamic, where
the former relates to signal-independent errors and the latter to signal-dependent errors. Tradi-
tional error reduction techniques focus on the static errors, for example, distortion terms may
be averaged into signal-independent noise. In order to obtain high performance special tech-
niques, such as spectral matching error shaping or inverse functions can be used [10, 11]. The
influence of dynamic errors must be treated in special ways and the analysis of their behavior
is complex.
To illustrate some of the design complexities, we give in this introductory chapter a back-
ground and an overview of the current research on data converters and especially for wireline
communications. We also outline the requirements put on the data converters by DSL specifi-
cations.
In Chapter 2 we give a more detailed description of D/A conversion in general. Properties of
quantization noise, discrete-time signals, etc. are discussed. Different important performance
measures valid for telecommunications applications are also described.
In Chapter 3 the most common D/A converter architectures used in communications applica-
tions are discussed and their properties are discussed and compared. Several high-perfor-
mance D/A converters found in literature and from data sheets are used in a performance
comparison. Since the output of the D/A converter is mostly pulse amplitude modulated
(PAM), e.g., sample-and-held, the output spectrum becomes sinc weighted and repeats itself
at multiples of the sample frequency. The images must be attenuated by analog filters (image-
rejection filters) and to be able to use a lower filter order we cannot use the whole frequency
range up to half the sampling frequency. This is referred to as oversampling or interpolation.
Since we are using a higher sample frequency than required, we may also apply noise-shaping
to effectively utilize the unused frequency space. We will refer to D/A converters with noise-
shaping loops and oversampling as oversampling D/A converters (OSDACs) and to converters
with oversampling only as interpolating D/A converters.
To assist the designer to understand some of the fundamental limitations on performance of
DACs, extensive models of the influence of different typical analog error sources is discussed
in Chapter 4. For example, we show how limited output impedance and matching errors of
unit DAC elements affect the linearity of the converter. These models are also referred to in
following chapters, where we compare measured, simulated, and calculated results. The work
has also yielded some closed formulas expressing some linearity measures as functions of
parameters given by the error sources.
Chapter 5 and Chapter 6 discuss the circuit-level implementation of D/A converters. In Chap-
ter 5 we discuss the design of some 2.7-V to 5-V CMOS current-steering Nyquist-rate D/A
converters. The nominal resolution is 10 through 14 bits. The design of oversampling D/A
converters with noise-shaping loops (OSDAC) is discussed in Chapter 6. The design of a 3.3-
4 Introduction
V to 5-V CMOS oversampling D/A converter is presented. The differences between some
generations of converters are highlighted and we show the improved measured results after
minor changes to the design.
In Chapter 7 we discuss the implementation of special techniques to further improve perfor-
mance of DACs. Especially dynamic element matching (DEM) techniques are considered but
also other pre-distortion techniques to cancel specific DAC errors. In most cases the binary
code is not optimum in terms of performance, since it will give rise to glitches and sensitivity
to matching errors. Instead the thermometer code is widely used. We show an interesting com-
parison of the results when using several different input codes in the DAC. A compromise
between extremes is the proposed linear-coded approach.
Chapter 8 contains appendices with derivation of formulas throughout the thesis.
Some of the chapters are slighlty overlapping to simplify for the reader to focus a single chap-
ter rather than reading the whole thesis. The author’s publications are related to the material
presented in the thesis, and in the preface the disposition of those was presented.
1.1 Integrated Circuits and the Digital/Analog Interface

The invention or construction of the integrated circuit is probably one of the most important
inventions during the previous century. Its impact on modern communication and in fact life-
style is tremendous. The first large-scale integrated (LSI) circuit is considered to be the Intel
4004 microprocessor. It was delivered in 1971 and contained about 2300 transistors and now-
adays (Jan. 2001), the largest chips contain several tens of millions of transistors. According
to the so called Moore’s law, the density of transistors on a chip is approximately doubled
every 18th month.
In this information technology era, products such as wireless terminals (mobile phones), lap-
top computers, bluetooth modules, and personal digital assistants (PDAs), require fast, dense,
and low power consuming integrated circuits. For high-integration, low-power applications
the bipolar technique has been replaced by the CMOS technique. However, still for very high-
speed and high-performance applications the bipolar technique is widely used [5]. We will in
our case consider the CMOS technology throughout the thesis and leave the bipolar technol-
ogy for now.
In general, we want to implement both analog and digital circuits on the same chip, since it
reduces the off-chip design complexity, e.g. layout of printed circuit board (PCB), and the
induced disturbance on sensitive interconnection wires is reduced. With the rapid develop-
ment of digital circuits, the supply voltage is decreasing which reduces the power consump-
tion. For the analog side, the design of high-efficiency circuits becomes complicated as the
voltage range is shrinking. Future design of analog circuits will most likely focus on low-volt-
age operation and maybe even subthreshold operation.
A mixed-signal circuit is more or less considered to be a subcircuit in which both analog and
digital circuits are used. Typically, the interface between the digital and analog domain, such
as the D/A or A/D converter, as well as phase-locked loops (PLL) are considered to be mixed-
signal circuits.
Integrated Circuits and the Digital/Analog Interface 5
1.1.1 Digital Circuits

The design of digital circuits can be divided into a number of different disciplines. Dependent
on application, either one of the disciplines become more or less important. With decreasing
transistor dimensions, the influence of wire lengths, parasitic capacitance, etc., becomes very
important and in some sense this requires knowledge in pure analog design as well.
The accuracy of the circuit is increased by simply increasing the word length (number of bits
used to represent the signals) to a desired level. This increases the chip area and the power
dissipation, which in an actual implementation probably set the upper limit on the accuracy.
With carefully evaluated algorithms and long word lengths the digital noise can be kept at a
very low level.
For a digital CMOS circuit, the power dissipation is approximately [5]
P ≈ αf ⋅ C L ⋅ V DD ⋅ n ⋅ ∆V , (1.1)
where α is the circuit’s switching activity, f is the clock frequency, C L is the average capaci-
tive load for each gate, n is the number of gates, V DD is the supply voltage, and ∆V is the
swing. The speed is inversely proportional to the time constant R on C L where R on is the on-
resistance of the CMOS transistor approximately [7] given by
R on ≈ [ K' ⋅ ( W ⁄ L ) ⋅ ( V DD – V T ) ] –1 , (1.2)
where K' is a process-dependent parameter, W ⁄ L is the transistor size aspect ratio, and V T
is the threshold voltage. Although it affects the speed of the circuit, it is a natural choice to
reduce the supply voltage in order to lower the power dissipation due to the quadratic depen-
dency in (1.1). By reducing the average load capacitance we gain in both higher speed and
lower power consumption. This is done by using as short wires and as small transistors as
possible. We also find the obvious conclusion that with fewer gates, n , we get a lower power
consumption. Therefore, the algorithms are very important, since with good algorithms we
can reduce the number of gates as well.
As measures on performance the maximum speed, power dissipation, chip area, etc., can be
used to characterize and compare digital circuits. But a general, good comparison method
does not exist. However, the achievable speed is dependent on the supply voltage and one
alternative performance measure is the power delay product (PDP) [5], which basically con-
siders both (1.1) and (1.2) but is defined as
PDP = P ⋅ τ P , (1.3)
where τ P is the propagation time. This may not be equal to the time constant ( R on C L ) but is
in the same order of magnitude. Using (1.1) in (1.3) and assuming full-scale swings gives the
approximate PDP
2 2
αf ⋅ C L ⋅ V DD ⋅ n
PDP ≈ k ⋅ ------------------------------------------------------------- , (1.4)
K' ⋅ ( W ⁄ L ) ⋅ ( V DD – V T )
where k is a constant given by the ratio between the propagation speed and the time constant.
We find that the PDP approximately is linearly dependent on the supply voltage. The load
capacitance is determined by the following number of transistor gates and length of the inter-
connection wires. Today, with shrinking dimensions, the wire capacitance is becoming more
6 Introduction
important than the number of gates [6].
To increase speed and throughput, special logic styles such as precharged logic, domino, true
single-phase clocking (TSPC), etc., are used [12]. There are also special adiabatic techniques
used to reduce power dissipation [6].
1.1.2 Analog Circuits

There are automated tools for layout and design of analog circuits, but still much of the work
has to be done by hand. An experienced designer is needed to implement high-performance
analog circuits. Due to short-channel effects, analog circuits do not scale as well as digital cir-
cuits. We mostly have to completely redesign our circuit when the process is changed or
updated. However, smaller process dimensions also give less parasitic capacitance and there-
fore the achievable bandwidth can be increased, etc.
For analog designers, one of the major problems with modern CMOS technologies is the
decreasing supply voltage. A low supply voltage slows down the circuits [8]. It becomes diffi-
cult to design for example a current source with high output impedance which is one limiting
factor on performance. Some other important design issues is the matching of components.
Very careful layout has to be used to reach good matching.
When analyzing and designing analog circuits we consider the linearization of the circuit
around the operating point. Unlike digital circuits, analog circuits, such as amplifiers or simi-
lar, are typically biased to a certain voltage level with a DC bias current. Therefore, the power
dissipation is given by the bias current times the supply voltage.
P = I bias ⋅ V DD . (1.5)
The bias current is typically set by a slew rate (SR) specification (or by the power specifica-
tion, etc.), where we may have
I bias
SR ≥ ---------- , (1.6)
CL
where C L is the load capacitance. The speed is given by the bandwidth of the analog circuit.
For an amplifier in a feedback configuration, we have
1
τ g = -------------- , (1.7)
β ⋅ ωu
where β is the feedback factor and ω u is the unity-gain frequency of the amplifier in open-
loop configuration. Approximately, we have that
CL
τ g = -------------
-, (1.8)
β ⋅ gm
where g m is the small-signal transconductance of the amplifier. Typically, g m ∼ V GS – V T and

hence for smaller voltage levels we get a poor g m and thereby a slow amplifier.
As measures on accuracy and performance we consider for example, DC gain, phase margin,
bandwidth, distortion, noise, power dissipation, slew rate, common-mode rejection, etc.
The CMOS transistor operates in a number of different regions, the cut-off or subthreshold,
Integrated Circuits and the Digital/Analog Interface 7
linear (triode), and saturation (active, pinch-off) regions. In analog circuits, we mostly let the
transistors operate in their saturation regions, since then the output impedance is high and
hence we have high gain (i.e. the output current is nearly independent on the voltage applied
across the drain and source terminals) . In the future, when very low voltage operation is
required, the subthreshold operation region of the transistors and may have to be considered.
Here, the CMOS transistor is behaving more as the bipolar transistor, where the drain current
is described by [7]
q V GS
------ ⋅ ----------
I D ≈ I D0 ⋅  ----- ⋅ e kT n ,
W
(1.9)
 L
where n ≈ 1.5 is a process-dependent constant, q is the electron charge, k is the Boltzmann

constant, T is the absolute temperature, and I D0 is a constant current in the order of nA.
However, the transistor is very slow and sensitive to matching errors in the subthreshold
region and is not suitable for high-speed operation. The transistor needs to be large to achieve
a high SNR.
As a measure of efficiency and gain we show in Table 1.1 the transconductance-over-current
parameter, g m ⁄ I D , for all operation regions. If we want to have a better g m ⁄ I D in the satura-
tion region than in the linear region, we require that
2 2
-------------------------------- < ------------- (1.10)
2V EFF – V DS V EFF
for the same V EFF applied to the transistor. We see that (1.10) ends up in
2V EFF – V DS > V EFF ⇒ V EFF > V DS , (1.11)
which is fulfilled for the linear region and hence we have that g m ⁄ I D is higher for the satura-
tion region. Typically, we choose V EFF to be larger than approximately 100 to 150 mV.
Hence g m ⁄ I D < 20 for the saturation region and > 25 for the sub-threshold region at room
temperature, T = 300 K.
Sub-threshold Linear Saturation
V EFF < 0
Requirements V EFF > 0 V EFF > 0
( V EFF = V GS – V T ) V DS = ? > 200 m
V DS < V EFF V DS > V EFF
V
q 2 2
gm ⁄ I D ---------- -------------------------------- -------------
nkT 2V EFF – V DS V EFF
Small-signal voltage gain V DS 2

----------------------------
- ---------------------
g m ⁄ g out V EFF – V DS V EFF ⋅ λ
Table 1.1. Some performance measures in the different operation regions. λ is the channel-length modulation
factor, q is the electron charge, k is the Bolzmann constant, and T is the absolute temperature.
8 Introduction
1.1.3 Mixed-Signal Circuits

The mixed-signal circuits contain both analog and digital circuits and mostly we consider
them to be integrated on the same chip. This is especially the case in highly integrated func-
tional blocks, i.e., so called system-on-chip (SOC) approaches. We may also consider the
interface (Fig. 1.1) between the digital and analog domains as typical mixed-signal circuits.
The data converters contains circuits operating on both analog and digital signals.
Typically, the digital circuits have a high switching activity yielding large current and voltage
spikes through the supply wires and substrate. In a low-ohmic, positively doped substrate
without twin-well option, the bulks (the potential of the substrate) of the analog and digital
NMOS transistors are almost shorted. Through the capacitive coupling the current spikes are
influencing the sensitive analog signals yielding a poor signal-to-noise ratio (SNR). Consider
the example in Fig. 1.2 where we have illustrated the analog and digital circuits on the same
substrate. We show both the noise coupling between wires and between transistors. The digi-
tal circuits are through the capacitive coupling inducing changes in current through the sub-
strate. Dependent on high-ohmic or low-ohmic substrates, this can be spread either through
the upper thin layer of the silicon or directed down to the back-plate connector. Hence, we
have (amoung others) both vertical and horizontal noise connection. To minimize the noise,
we should properly guard the sensitive analog circuits and wires through substrate contacts,
quite wells for the transistors, etc. [7, 8, 13].
Analog Digital
wires wires
transistors transistors
Oxide Oxide
Substrate
Figure 1.2 Switching noise from digital circuits is spreading through the substrate and affecting the
sensitive analog circuits.
High-level or behavioral-level design is important and the trade-off between the digital and
analog circuits can/must be made. In, e.g. a data converter, more digital circuits and computa-
tion can be used in order to reduce errors introduced in the analog domain. Some simple
examples on this are the Gray or thermometer coding techniques [9, 14]. This is also what
motivates the work (Chapter 4) to find models and formulas that help us understand the
behavior of the circuits.
1.2 Communication Circuits

The work presented in this thesis is focused on circuits for telecommunications and especially
wireline applications. As was discussed previously the objective with the data converters is to
be part of the send and receive paths in modems or transceivers. In Fig. 1.3 we show a gener-
alized view on a communication system [15]. In the transmission path we find the source and
channel coders and the modulator. The output is transmitted over a channel (radio, fibre, cop-
Communication Circuits 9
per). In the receive path we have the demodulator and channel and source decoders. The cod-
ers and modulators can also be combined into so called coded modulation to find the optimum
performance of the system [15].
Source Channel Modulator

encoding encoding
l
Channe
Source Channel Demodulator
decoding decoding
Figure 1.3 Illustration of a communication system.
1.2.1 Modulation Schemes

Dependent on application the modulation can be done either in the digital or the analog
domain [1, 15]. Typically, in radio (wireless) applications the modulation is done in the analog
domain, but for DSL the modulation is done in the digital domain through an inverse fast Fou-
rier transform (IFFT) operation. Roughly, through the modulation a carrier (e.g. a sine wave)
is modified as a function of the specific data to be modulated so that a receiver is able to
extract the data from the carrier. A sine wave is described by four parameters, its offset,
amplitude, frequency, and phase. Although it is possible to use the offset level as modulation,
one normally prefer to modify the three other parameters by so called amplitude-shift, phase-
shift, or frequency-shift keying (ASK, PSK, or FSK), respectively [15]. The modulation meth-
ods can be combined and we have for example the amplitude-phase keying (APK) where both
phase and amplitude are modulated. For an M -ary modulation, there are M = 2 m ( m is an
integer) available variations to transmit.
In the following we highlight M -ary quadrature amplitude modulation (QAM) since it is
widely used in ADSL and in the next chapter pulse amplitude modulation (PAM) is discussed
since it is widely used in D/A conversion.
Quadrature Amplitude Modulation (QAM)

With quadrature amplitude modulation (QAM) we have for the carrier an in-phase ( I ) and
quadrature ( Q ) signal [15], and they are combined into an expression as
C(t) = I (t) + Q(t) = ϕ I (t) ⋅ cos ( ω c ⋅ t ) – ϕ Q(t) ⋅ sin ( ω c ⋅ t ) , (1.12)
where ω c is the angular frequency of the carrier and ϕ I , k(t) and ϕ Q, k(t) are pulses with
amplitude levels determined by the specific data or code that is modulated on the carrier. We
may also write them as
ϕ I (t) = A I ⋅ p(t) and ϕ Q(t) = A Q ⋅ p(t) , (1.13)
where p(t) is a proper pulse, e.g., raised cosine or square wave. The pulses are limited in time
and typically raised cosine is preferred over square wave since then the modulation signal will
require less bandwidth [15]. In Fig. 1.4 (a) we show a 16-QAM code constellation, e.g., the
IQ diagram. The code is obviously two-dimensional, since the in-phase and quadrature (I and
Q) signals are orthogonal over one period T . With a b -bit QAM there are M = 2 b different
10 Introduction
complex symbols. For example, the code indicated with a box in Fig. 1.4 is determined by
( A I , A Q ) = ( 3, 1 ) or expressed by complex numbers A = A I + j ⋅ A Q = 3 + j .
Figure 1.4 16-QAM code constellation in the IQ-space. The point (3,1) is high-lighted.
The assignment of symbols to the corresponding point in the IQ-space is often done with
Gray coding which minimizes the number of bits differing between two adjacent symbols,
which further improves the sensitivity towards error and noise [15].
1.2.2 Channel Models

The channel, as illustrated by Fig. 1.3, can be of several different kinds. In this thesis we focus
on the twisted-pair as part of the POTS and we will take a closer look at it in Sec. 1.3.4. First,
we highlight the common model for the physical channel; the memory-less Gaussian channel
[15, 16]. This is illustrated in Fig. 1.5 where the noise added on the channel is modeled as
white, Gaussian distributed noise. This is also referred to as an additive white Gaussian noise
(AWGN) channel. Over the required signal bandwidth, the noise has the power P n . The sig-
nal-to-noise ratio (SNR) on the channel is given by the signal power, P s , and the noise power
as
P
SNR = -----s- . (1.14)
Pn
Noise
Channel
Figure 1.5 Example of a model of a memoryless Gaussian channel.
Basically, we say that the higher SNR the higher data rate can be achieved. This rough
description is formed in the channel capacity theorem, which states that the channel capacity
[16] is given by
C = BW ⋅ log2 ( 1 + SNR ) bit/s, (1.15)
Digital Subscriber Line Technique (DSL) 11
where BW is the bandwidth of the channel. This is a theoretical limit and it is very hard to
reach it. However, as long as we transmit at a rate lower than the channel capacity, C , the bit
error probability will to go towards zero with time. We see that three fundamental parameters
describe the capacity; the channel bandwidth, the signal power, and the induced noise power.
To approach the upper bound in (1.15) we require that the transmitted signal has certain prop-
erties and for our case; one of them is that the signal should have characteristics of white
noise [16]. This is further described in Sec. 1.3.2 for the discrete multi-tone (DMT) signals
used in DSL.
A nonlinear channel will give rise to distortion and add a lot of complexities to the informa-
tion theory. Roughly, we may however in most cases model the distortion as noise [15] and
hence the SNR will decrease and thereby the achievable data rate.
1.2.3 Transmission Modes

The channel can be used for transmission in different ways as is illustrated for three different
cases in Fig. 1.6. We can for example allow that only one is able to send and we have a sim-
plex transmission mode (a), hence the channel is only used in a single direction. We can allow
two (or more) to send, but not simultaneously (b), which is referred to as half-duplex mode. In
a full-duplex mode (c), both are allowed to send simultaneously.
(a) (b) (c)

Figure 1.6 Illustration of different transmission modes. (a) simplex, (b) half-duplex, and (c) full-
duplex.
When using the full-duplex mode, it must be made possible for the sender/receiver to separate
the sent signal from the received. Typically, an echo cancelling technique is used [1, 2], where
the sent signal is subtracted from the received signal (see Sec. 1.3.1).
In the receiver it can be difficult to separate the signals from several different senders (includ-
ing it self). Therefore, frequency-division multiplexing (FDM) or time-division multiplexing
(TDM) can be used [1, 2]. For FDM the signals are separated in frequency and with TDM
they are separated in time.
1.3 Digital Subscriber Line Technique (DSL)

The digital subscriber line (DSL) standards allow very high transmission rates over the ordi-
nary telephone lines [1, 2, 3]. The standards are still not fully established. In this thesis we
focus on the so called asymmetric DSL (ADSL) and very-high data rate DSL (VDSL) stan-
dards. For ADSL some different standards have evolved, in which the modulation schemes
differ [3]. One uses carrierless amplitude and phase modulation (CAP) and others use discrete
multi-tone modulation (DMT). This type of modulation is similar to the orthogonal frequency
division modulation (OFDM) where data is modulated onto a number of carriers or tones by
using for example quadrature amplitude modulation (QAM) on each tone. In this thesis, we
only consider the DMT modulation scheme.
12 Introduction
In Fig. 1.7 we illustrate the concept of DSL. The interconnection between the customers pre-
mises equipment (CPE) – the user side – and the central office (CO) – the service provider
side – is the twisted-pair wires of the plain old telephone service (POTS). The voice channel is
limited to the lower kHz band and we have to use a low pass (LP) filters to separate the DSL
data signal from the voice channel. These filters are referred to as splitter filters and are found
at both the CO and in the CPE. The backbone networks may be optical fibres or similar high-
speed data networks, typically in asynchronous transfer mode (ATM). The VDSL system may
be somewhat different, but the basic topology is the same as shown in the figure [1, 2].
Backbone
CPE CPE
CO CO
CPE
CPE
CPE
Figure 1.7 Illustration of a DSL communication system.
In Table 1.2 we compare the ADSL and VDSL with some voice channel modem techniques
and the ISDN service in terms of transmission speed and required bandwidth [1, 2, 3]. We find
that the increase in data rate using DSL is large over the established, common techniques.
Transmission Upstream Downstream Channel bandwidth

Standard
mode rate [kbit/s] rate [kbit/s] [kHz]
V.34 voice modem Asymmetric < 28.8 28.8 4

V.90 voice modem Asymmetric 33.6 54 4
V.120 ISDN modem Asymmetric 32 - 64 64 - 128 4
ADSL Asymmetric 100 - 800 1000 - 8000 1104
VDSL Both 25000 25000 11040
Table 1.2. Specifics of different xDSL standards compared to voice channel techniques and ISDN. The
bandwidths are given by approximate numbers.
1.3.1 DSL Analog Front End (AFE)

We will take a closer look at the analog front end (AFE) for DSL to illustrate some of the
design challenges. A principle block view of an AFE for ADSL [1, 2, 17] is shown in Fig. 1.8
and we see that the picture reassembles that of the general communication system shown in
Fig. 1.3. Components that are required for good performance, such as equalizers, echo cancel-
ling, etc., have not been added to the figure, we have included the FFT and IFFT (inverse
FFT) operations although they are not analog. In the DSL systems it is the IFFT that modu-
lates and the FFT that demodulates the signal. However, Fig. 1.8 gives a good picture of the
analog front end. We have the transmission (send) path (Tx) and the receive path (Rx). In the
Tx path we find the IFFT operation that generates the carriers with their corresponding phase
and amplitude. The D/A converter generates an analog representation of the signal. The signal
is filtered and amplified. A transformer is used to separate the twisted-pair channel and the
AFE. In the Rx path we find filters, programmable gain control (PGC) or automatic gain con-
trol (AGC), A/D converter to extract the digital representation, and finally the FFT to extract
the modulated data. With equalizers and training sequences the data can be aligned and
adopted to the properties of the channel [1, 2, 3].
Digital Analog
Send IFFT DAC LP A
path
l
Channe
Receive
path FFT ADC LP A
Figure 1.8 DSL analog front-end.
For multi-user channel and full-duplex as illustrated in Fig. 1.6 echo cancelling is required.
Using this we significantly improve the situation for the circuits (mainly analog) in the receive
path. The noise power can be held at reasonable level and the received signal from another
sender does not become drowned in the own sent signal. The echo cancelling can be done in
several different ways [1, 2, 18], both in the digital and analog domain, both with active and
passive components. In Fig. 1.9 we illustrate some of these techniques. In (a) we find the
approach to remove the echo in the analog domain and (b) in the digital domain. A combina-
tion with a separate D/A converter combined with digital circuits that simulates the inverse
influence from the channel is illustrated in (c). In (d) we find a common passive hybrid which
extracts the sent signal through an impedance bridge. Here we have to be careful with the
impedance matching and especially how the impedance of the bridge match to the channel
(e.g., Z 3 and Z line ). In some cases passive circuits are used to simulate the impedance to get
more control on the frequency behavior. Mostly, the analog domain is preferred since it
reduces the noise power at the input of the A/D converter (and amplifier) in the receive path
and we reduce the probability for clipping in the analog components.
1.3.2 Discrete Multi-Tone (DMT) Signals in DSL

When using discrete-multi tone (DMT) modulation a batch of codes (a symbol) is modulated
onto a number of different carriers instantaneously [1, 2]. This is done through the IFFT oper-
ation and to the IFFT a vector of complex values is fed. The elements of the vector are deter-
mined by corresponding I and Q values as illustrated in Fig. 1.4 for a QAM. The number of
carriers in the DMT is dependent on the quality of the upstream/downstream link and can in
some cases be chosen in a more or less adaptive way [3]. Each carrier has a frequency that is a
multiple of a fundamental frequency, hence the angular frequencies are given by ω c = k ⋅ ω 0
14 Introduction
DAC
ADC
(a) (b)
DAC Z1 Z2
DSP DAC
+ Vrcv -
ADC Z3
Zline
(c) (d)
Figure 1.9 Examples on echo cancelling techniques (dashed). On (a) the analog side, (b) digital side,
(c) using and (d) passive hybrid.
where ω 0 = 2π ⋅ f 0 is the fundamental angular frequency. For ADSL, we have

f 0 = 4.3125 kHz and a maximum k of 256. The maximum code constallation is 1024-QAM
on each carrier. For VDSL, we have f 0 = 43.125 kHz. and a maximum number of carriers is
also 256. These values will vary with the quality on the equipment and channel. In (1.12) we
find a describtion for QAM on a single carrier. Generalizing this expression to the k -th carrier
gives
C k(t) = I k(t) + Q k(t) = ϕ̂ k(t) ⋅ sin ( kω 0 ⋅ t + φ k ) , (1.16)
where the amplitudes are given by
ϕ̂ k(t) = [ ϕ I , k(t) ] 2 + [ ϕ Q, k(t) ] 2 = A I2, k + A Q2 , k ⋅ p(t) = A k ⋅ p(t) , (1.17)
and the phase shifts are
– ϕ Q, k ( t ) A Q, k
φ k = atan -------------------
- = atan ----------
- = arg A k . (1.18)
ϕ I , k(t) AI, k
The DMT signal becomes in the time domain

K
D(t) = p(t) ⋅ ∑ A k ⋅ sin ( kω 0 ⋅ t + φ k ) . (1.19)
k=1
The pulse p(t) is typically a raised-cosine or similar [1, 2, 3]. The modulation is done in the
digital domain by simply applying the vector
A = ( A I , 1 + j ⋅ A Q, 1, …, A I , 256 + j ⋅ A Q, 256 ) (1.20)

to the IFFT. Actually, we need to apply a vector of length 512, since an anti-symmetrical input
is required for a real output. This is however mostly done internally in the IFFT. Except for
p(t) the output of the IFFT will equal the sum in (1.19). This sum may become very large if
the number of carriers is large. In Fig. 1.10 we show a simulated DMT signal at the output of
a 14-bit D/A converter. In (a) we plot the signal in the time domain and in (b) in the frequency
domain. Due to the quantization of the signal there is a quantization noise floor in the spec-
trum. Some tones have been left out to illustrate the concept of allocating different number of
bits to different carriers. The codes that have been applied to the carriers were randomly cho-
sen, but each tone has an equal amplitude of –24 dBFS.
The peak-to-average ratio (PAR) is defined as the ratio between the peak amplitude and the
root mean square (RMS) value. A high PAR indicates that there are high peaks in the output
compared to its average. Typically, high PAR implies that the probability for clipping of the
signal is higher and one should try to achieve a low PAR. The PAR is always higher than
unity.
DMT ADSL signal DMT ADSL signal
8192 −6
−24
Power [dBFS]
−100
−140
−8192
3 4 0 0.276 0.552 0.828 1.104
Time [ms] Frequency [MHz]
(a) (b)
Figure 1.10 Example of a multi-tone signal in the (a) time and (b) frequency domain
For a single-tone carrier with amplitude A , the PAR becomes

A
PAR = --------------- = 2 ≈ 1.41 . (1.21)
A⁄ 2
For a number of overlaid carriers (placed at multiples of the fundamental frequency) the RMS
value is independent of the phase differences and given by
1
RMS = --- ⋅ ∑ A k2 , (1.22)
2
since all carriers are mutually orthogonal. However, the peak amplitude is not as easy to
describe with an analytical expression. It can be shown [2] that the PAR for a DMT signal is
equal to a scaling constant times the sum of the individual PAR of each carrier:
16 Introduction
K
1
PAR D = -------- ⋅ ∑ PAR k . (1.23)
K k=1
If all carriers have the same PAR k = PAR 0 (which practically is the case for equal sinusoi-
dals) we have that
PAR D = K ⋅ PAR 0 . (1.24)
However, the PAR may differ from carrier to carrier dependent on the number of bits that are
modulated onto the carrier. Consider a QAM constellation as the one in Fig. 1.4. Assume that
we in the general case have a b -bit QAM and that the “distance” between adjacent symbols in
terms of power is ∆P . The maximum amplitude is found at the corner points, hence we have
∆P ∆P
P pk = [ ( 2 ⋅ 2 b / 2 – 2 b / 2 – 1 ) 2 + ( 2 ⋅ 2 b / 2 – 2 b / 2 – 1 ) 2 ] ⋅ ------- = ------- ⋅ ( 2 b / 2 – 1 ) 2 . (1.25)
4 2
Further, assume that each point in the constellation is sent with equal probability
p = 2 –b = 1 ⁄ M , the average symbol power, P avg , can be calculated
2b / 2 2b / 2
∆P
P avg = p ⋅ ------- ⋅
4 ∑ ∑ [ ( 2q – 2 b / 2 – 1 ) 2 + ( 2i – 2 b / 2 – 1 ) 2 ] = …
q = 1i = 1
∆P 1 ∆P 1
… = 2 –b ⋅ ------- ⋅ --- ⋅ 2 b + 1 ⋅ ( 2 b – 1 ) = ------- ⋅ --- ⋅ ( 2 b – 1 ) . (1.26)
4 3 2 3
Using (1.25) and (1.26) we have the PAR for the constellation as
∆P
------- ⋅ ( 2 b / 2 – 1 ) 2
P pk 2 3 ⋅ ( 2b / 2 – 1 ) M–1
PAR S = ---------- = --------------------------------------- = ------------------------------
- = 3 ⋅ ------------------ . (1.27)
P avg ∆P 1 2b / 2 + 1 M+1
------- ⋅ --- ⋅ ( 2 b – 1 )
2 3
Hence, the more bits we assign to a carrier, the higher PAR. If the codes are modulated on a
carrier with PAR C we will have a total PAR of
PAR = PAR S ⋅ PAR C . (1.28)
If the carrier is a sinusoid, we have PAR C = 2 . Hence the PAR for QAM on a single sinu-
soidal carrier will go towards 6 with increasing M or number of bits. For a K -tone DMT
with equal number of bits on each carrier, we get
M–1
PAR = K ⋅ 2 ⋅ 3 ⋅ ------------------ . (1.29)
M+1
With the maximum number of tones (256) and largest constallation ( M = 1024 ) we get a
ratio of approximately PAR ≈ 38 . This is a very large value and expresses the worst-case situ-
ation.
In Fig. 1.11 we show two examples of multi-tone signals with (a) high and (b) low PAR. The
number of tones is 46 and the frequency spacing is 17.25 kHz. All carriers have the same –30-
dBFS power (same amplitude), but the phases have been randomly selected (uniform distribu-
tion). The standard deviation of the phases in Fig. 1.11 (a) was chosen to be much smaller
than the one for the phases of the case in (b). We see that in any of the two cases, although we
see the periodicity of the signal, has a resemblance to white noise, hence the signal’s power is
spread equally throughout the frequency range, as also is illustrated by the spectrum in Fig.
1.10 (b). This is also one of the properties required to reach a high data rate. The signal shown
in Fig. 1.12 (a) is even clipping and will give a distorted output.
DMT ADSL signal with high PAR DMT ADSL signal with low PAR
8192 8192
0 0
−8192 −8192
2 3 4 2 3 4
Time [ms] Time [ms]
(a) (b)
Figure 1.11 Example of a multi-tone signal with (a) high and (b) low PAR.
When the signal is “similar” to white noise, its amplitude levels become Gaussian distributed.
In Fig. 1.12, we show the histograms of the amplitude levels of the signals in Fig. 1.11 (a) and
(b), respectively. Notice the different scales for the probability axes in (a) and (b). We see that
the distribution of the amplitude levels or codes is similar to that of a Gaussian distribution,
which is desired.
However, the standard deviation of the signal, i.e., the signal power, is approximately equal
for both cases. In Fig. 1.13 we have plotted the relative histogram width within which a total
of 60% of all codes are likely to occur. Hence, we find plot the percentage value of W ⁄ 2 N
from the following relation
W
P( X < W ) = ∫ f (x) dx = 0.6 , (1.30)
–W
where X is the amplitude level. Each one of 64 carriers has random phase that is dependent
on the QAM code. The amplitude is held constant at –24 dBFS. We find that for a higher PAR
the width of the histogram is shrinking. We can extend this discussion. The signal is bound
by an upper and lower limit since we cannot transmit with an infinite signal power and we
have a limited resolution in the data converters and the limited word length in the DSPs. As
can be understood from the results shown in Fig. 1.11, the clipping probability is dependent
on the PAR, the higher PAR the higher probability for clipping. Clipping will give rise to
missing codes and further, with a high clipping probability we get higher distortion and a
18 Introduction
Code distribution of high−PAR signal Code distribution of low−PAR signal
1.5
Probability [promille]
Probability [promille]
3 1
0.5
−4096 0 4096 −4096 0 4096

Code Code
(a) (b)
Figure 1.12 Illustration of Gaussian distributed amplitude levels of (a) high- and (b) low-PAR DMT
signals.
Relative 60−% density of histogram vs. PAR
37
Relative density [%]
25
12
2 3 4 5.3
PAR
Figure 1.13 Standard deviation of amplitude distribution as function of PAR for a multi-tone signal.
higher bit error rate (BER) [1, 2]. If the amplitude levels are Gaussian distributed, the proba-
bility for clipping is (compare with (1.30))
p c = P ( X > PAR ⋅ RMS ) , (1.31)
where X is the signal that has a Gaussian amplitude distribution of N (0, σ) and σ = RMS is
the standard deviation. This gives the probability for clipping as
∞ a2 ∞ a2
2 – --------- 2 – -----
p c = ------------------ ⋅ ∫ --- ⋅ ∫
2σ 2
e da = e 2 da . (1.32)
2π ⋅ σ π
PAR ⋅ σ PAR
In Fig. 1.14 we show the clipping probability as function of the PAR. It is remarkable that
Clipping probability vs. PAR

0
10
−3
10
Clipping probability
−7
10
−9
10
−12
10
1 1.4 2.5 5.3 8

PAR
Figure 1.14 Clipping probability as function of the PAR.
with higher PAR the clipping probability is decreasing. This is since we relate the distribution
to the possible achievable maximum (FS) and for higher PARs the amplitude distribution will
be more dense around the DC level.
Frames and cyclic prefix

Normally, the data, the symbol that has been modulated onto a number of carriers, is sent in
batches [1, 2]. That is, for a certain time interval, the data of one symbol is modulated onto a
number of carriers. During next time interval the next symbol and batch of data is sent. The
data will also be assigned to different time frames where we have for example synchroniza-
tion blocks, equalization blocks, etc. Due to the frames and batches, we get transients between
each new symbol being applied. To decrease the influence of the transients a certain time slot
is used for a so called prefix. This time slot must be long enough to guarantee that the tran-
sients have settled. It is advantageous to use a cyclic prefix due to the nature of convolution.
This is also referred to as frequency-domain equalization.
In Fig. 1.15 we show the concept of the cyclic prefix. If the symbol consists of K samples, the
L last samples are added at the beginning of the symbol. Hence a symbol of K + L samples is
sent instead. For example in DMT-ADSL we have K = 512 and L = 32 in the downstream
direction [3].
n-th data batch (n+1)-th data batch
Figure 1.15 Use of cyclic prefix in transmission in batches.

20 Introduction
1.3.3 Spectral Requirements for ADSL and VDSL

The ADSL standards allow a maximum data rate of approximately 8 Mbit/s [3]. As was
shown in Table 1.2 the transmission is asymmetric, hence from CO to CPE (downstream) the
transmission rate is about 1 to 8 Mbit/s and from the CPE to CO (upstream) it is 0.1 to
0.8 Mbit/s. In the frequency domain the upstream signal is limited to the frequency band from
4 to 132 kHz and for the downlink from 136 kHz to 1.104 MHz. The standard allows full-
duplex mode through both FDM and TDM. 256 tones (carriers) are used at multiples of the
fundamental frequency of 4.3125 kHz. The lowest possible update frequency is 2.208 MHz
according to the sampling theorem. The carriers are allowed to fluctuate by 3.5 dB within the
passband [3]. In Fig. 1.16 we show the bounds on transmitted signal power on the line as
function of the frequency according to the standard for both upstream (CPE) and downstream
(CO). Above the 2.208 MHz frequency range, the signal is not allowed to peak more than –90
dBm/Hz within a 10 kHz window. Typical spectral requirements [3] are summarized in
Table 1.3.
ADSL CO transmit PSD specification ADSL CP transmit PSD specification
−36 −34
PSD [dBm/Hz]
PSD [dBm/Hz]
2208
−90 −90
−97 −97
4872 4872
1 4 25.875 1104 3660 11040 1 4 25.875 138 685 11040

Frequency [kHz] Frequency [kHz]
(a) (b)
Figure 1.16 Transmitted power spectral density specifications on (a) CO and (b) CPE side for ADSL.
The VDSL standards are still (Dec. 2000) not completely set, but it is aimed to allow a maxi-
mum data rate of approximately 25 Mbit/s. The transmission can be both symmetric and
asymmetric. As was shown in Table 1.2 the down- and upstream transmission rates are about
25 Mbit/s. In the frequency domain the signal is limited to a frequency band from approxi-
mately 40 kHz up to 11.04 MHz. As for ADSL, full duplex is used through FDM and TDM.
The number of tones are also not specified, but something in the order of 1024 or 2048 is dis-
cussed. A multi-tone transmission method referred to as Zipper can be used [19]. This method
originally let the CO use every second tone and the CPE every other second tone (throughout
the frequency-domain) for transmission. This will however become expensive in terms of cir-
cuit complexity and instead an approach with a number (more than one) of consecutive tones
is preferred [20].
1.3.4 The Twisted-Pair Channel

Typical limitations on achievable data rate are the quality of the analog components in the
AFE and the twisted-pair cables [1, 2]. We may for example not have too long cables since the
attenuation of the cable becomes higher with longer cables [1, 2]. The quality of the wire is
Frequency CO peak PSD Frequency CPE peak PSD

[kHz] [dBm/Hz] [kHz] [dBm/Hz]
0 to 4 – 97.5 0 to 4 – 97.5
4 to log10 ( f ⁄ 4 ) 4 to log10 ( f ⁄ 4 )
– 92.5 + 21 ⋅ --------------------------
- – 92.5 + 21.5 ⋅ --------------------------
-
25.875 log10 2 25.875 log10 2
25.875 25.875
– 36.5 – 34.5
to 138 to 138
1104 to log10 ( f ⁄ 1104 ) 138 log10 ( f ⁄ 138 )

– 36.5 – 36 ⋅ -----------------------------------
- – 34.5 – 24 ⋅ --------------------------------
-
2208 log10 2 to 685 log10 2
2208 to log10 ( f ⁄ 2208 ) 685 to

– 72.5 – 24 ⋅ -----------------------------------
- – 90
3360 log10 2 11040
3360 to
– 90
11040
< –40 dBm power within > 915 < –40 dBm power within
> 4872
1-MHz sliding window 1-MHz sliding window
Table 1.3. Spectral requirements on transmitted signal for ADSL at both CO and CPE sides.
not only dependent on the wire length, its characteristic impedance is frequency-dependent as
well. The cable may be modeled as a distributed RLCG network where almost all parameters
are frequency-dependent. We have the approximations found through measurement studies [2]
as
l 0 + l ∞ ⋅  ------
f b
4
 f m
R( f ) = 4 R oc + a c ⋅ f 2 , L( f ) = ----------------------------------b- , G( f ) = g 0 ⋅ f ge , and C( f ) = c ∞ ,(1.33)
1 + l ∞ ⋅  ------
f
 f m
where f is the frequency and the other parameters are dependent on cable dimensions and
other physical constants. Using the parameters above we can find the line input impedance as
[2]
Z L + Z o ⋅ tanh ( γ ⋅ l )
Z in = Z 0 ⋅ ------------------------------------------------ , (1.34)
Z 0 + Z L ⋅ tanh ( γ ⋅ l )
where l is the wire line, Z 0 is the characteristic impedance and γ is the propagation constant.
We have
R + sL
γ = ( R + sL ) ⋅ ( G + sC ) and Z 0 = ----------------- , (1.35)
G + sC
hence both γ and Z 0 are frequency dependent. In Fig. 1.17 we show how the signal frequency
affects the input impedance of different cables. In the simulation we have considered the 26-
and 24-gauge cables as well as indoor wired twisted-pair cables. All cables are 3 km long.
22 Introduction
The input impedance is the load impedance for the AFE, and the value is crucial for imped-
ance adjustment and the design of the line drivers in the AFE. We want the line driver to
deliver maximum power to the line. Therefore, the linedriver needs to adjust its output imped-
ance in a similar way as shown in the figure. We see that for higher frequencies the absolute
impedance becomes approximately constant. The impedance becomes approximately resistive
for higher frequencies.
Input line impedance vs. frequency
26−Gauge
24−Gauge
Indoor wiring
500
Absolute impedance [Ω]
400
300
210
170
150
4 136 1104 11040

Frequency [kHz]
Figure 1.17 Input impedance of a twisted-pair cable as function of frequency and length.
Crosstalk
Another limitation is the crosstalk from other DSL users. Crosstalk arises since there are sev-
eral twisted pairs in the same bundles. The crosstalk can be divided into near-end and far-end
(NEXT and FEXT). The NEXT is determined by how much the CPE is disturbed by other
CPE’s, hence how much of other users transmission is received. The FEXT is how much of
other users transmission that the CO receives. Typically, the NEXT and FEXT are considered
to be white noise. In xDSL the crosstalk is one of the largest error sources, but there is also
additional noise coming from radio signals, since especially air-bound twisted-pair cables
more or less function as antennas as well [1, 2].
1.4 Requirements on D/A Converters for xDSL

In this thesis we focus on the D/A converters in the DSL systems. It is therefore interesting to
see what requirements that are put on the D/A converters for DMT-ADSL. We found in the
previous sections that the SNR (or SQNR) can be written as a function of the number of bits
and the peak-to-average ratio (PAR). Further, the PAR is dependent on the number of bits
modulated onto the carrier ((1.27) and (1.28)). From (1.26) we have the average signal power
for a b -bit QAM ( 2 b -QAM) as
∆P 1
P avg = ------- ⋅ --- ⋅ ( 2 b – 1 ) , (1.36)
2 3
where ∆P is the “power distance” between two adjacent codes. Further, we have that the
noise power, P n , can be written as
Data Converter Applications 23
2 2
P n = σ n = -------------------------
- (1.37)
[ Q ( p ε) ] 2
– 1
where σ n2 is the noise variance, p ε is the error probability, and Q –1 is the inverse error func-
tion. We may now find the SNR as
P avg 2b – 1
SNR = ---------- = ∆P ⋅ -------------- ⋅ [ Q –1( p ε) ] 2 . (1.38)
Pn 12
From (1.38) we can now derive the effective number of bits. To cover for the influence of the
quantization noise, some additional bits should be added to get the required number of bits in
the DAC. Typical number of bits are in the order of 10 to 12 [1, 2]. This is of course depen-
dent on the noise on the specific wires, wire length, transmitted power, etc. We should also
choose a design margin and hence we end up in specifications around 12 to 14 bits. This is
also at which we aim throughout the thesis.
1.5 Data Converter Applications

As mentioned in the previous sections, there are of course different application fields for the
data converters. We can roughly divide them into audio, video, sensor, instrumentation, and
communication converters. In Fig. 1.18 we show an overview of application areas vs. the sam-
ple frequency and resolution of data converters. The comparison is found by studying all the
references in the end of the thesis. A compilation of some of these references are also pre-
sented in Figure 3.22 on page 78 and Table 3.3 on page 79. The thick, dashed line indicates a
typical trade-off between bandwidth and resolution. Comparing the measured (and published)
results from several data converters we find the slope of this line to be approximately 18 dB/
decade. This is further discussed in Sec. 3.7.
20
16
Resolution
12 DSL
Audio Video
8
4 Sensor
kHz MHz GHz Sample frequency
Figure 1.18 Overview of application areas as function of resolution and sample frequency.
Audio converters are characterized by a very high resolution and a rather low bandwidth [9,
72]. With a low bandwidth we refer to the kHz range, which is the limitation for the percep-
tion of the human ear. For these applications, the oversampled converters are widely used,
since we can allow a very high oversampling ratio which reduces the complexity within ana-
log design and increases accuracy. Typical acronyms, such as 1-bit DACs, MASH, etc., have
24 Introduction
become a kind of commercial tag displayed on several CD players.
The video converters require a higher bandwidth [53, 54, 56, 63]. Video converters have also
been applicable in the telecommunications applications, but nowadays we must have convert-
ers with even higher performance for communications. In communications, we want to
replace the analog circuits with as digital circuits as much possible. This implies that we will
push the interface closer and closer to the channel. For radio applications we want to modulate
the signal in the digital domain as is done for the DSL applications.
Instrumentation converters are used in measurement equipment and for signal generation.
These converters are typically implemented in special, expensive technologies to provide a
very high linearity [114].
Sensor converters are very application specific and the common resolution and frequency
bandwidth vary between the extremes. We have for example image sensors in pixel arrays as
well as D/A converters controlling computer drives, etc.
2 Introduction to D/A
Conversion
2.1 Introduction
Throughout this chapter we present the basics of general digital-to-analog converters (DACs).
The DAC generates an analog output (signal) that represents the digital input (signal). The
analog output is a signal carrier representing the same signal as the digital input does. An
essential issue is that the input is digital, hence discrete-time and discrete-amplitude. There-
fore the output signal contains truncation noise.
A circuit implementation of a converter will suffer from a number of nonidealities, e.g., com-
ponent matching, limited output impedance, noise, etc. This causes the output to become dis-
torted and noise to be added to the signal. In this chapter we present a number of different
standard measures to characterize DACs and its performance. Especially, we describe some
typical performance measures for communications, such as signal-to-noise ratio (SNR), spuri-
ous-free dynamic range (SFDR), signal-to-noise-and-distortion ratio (SNDR), intermodula-
tion distortion (IMD), and multi-tone power ratio (MTPR), etc.
The behavior of errors due to circuit nonidealities, e.g., distortion and noise, can be of several
different types. One can distinct between static and dynamic properties of the errors. The
static properties are signal-independent (memory-less) and the dynamic properties are signal-
dependent. A typical static error is the deviation from the wanted straight-line input/output
DC transfer characteristics, such as gain error, offset, differential (DNL) and integral nonlin-
earity (INL), etc. The dynamic errors mostly become more obvious and dominating as the sig-
nal and clock frequencies increase, whereas the static errors are dominating at lower
frequencies. Dynamic performance is determined by signal-dependent errors such as slewing,
clock feedthrough (CFT), glitches, settling errors, etc. In some sense, the static errors deter-
mine the best-case performance of the converter.
The performance of the DAC can be determined using measures in both the time and fre-
quency domain. Although static errors are signal-independent, they may give rise to (linear)
25
distortion at frequencies that are multiples of the fundamental signal frequency. CFT in DACs
generates frequency components at multiples of the Nyquist frequency (half the sample fre-
quency) and glitches influence the higher frequency band, etc.
First, we outline the properties of the “ideal” D/A converter and different digital codes in Sec.
2.2. As “ideal” we understand a continuous-time, but discrete-amplitude output due to the
limited resolution (word length) at the input of the DAC. Due to the limited set of amplitude
levels, there will be quantization (or truncation) noise. In Sec. 2.3 and Sec. 2.4 we discuss the
properties of static and dynamic errors, respectively. Mostly the characterization of DACs for
telecommunications applications is done in the frequency domain. Some of the most impor-
tant measures are discussed in Sec. 2.5.
2.2 The Ideal D/A Converter

The purpose of the D/A converter (DAC) is to transform the digital representation (input
word) of a signal into its corresponding analog representation. This is illustrated by the black
box view of the DAC as shown in Fig. 2.1. The input is specified by the N -bit words and the
output, the analog representation, is typically generated by pulse-amplitude modulation
(PAM), where the amplitude level is determined by the digital input word. The digital input
has a limited amplitude resolution because of the limited word length or number of bits.
b1
X DAC A A
N DAC
bN
Figure 2.1 Alternative representations of ideal DACs.
Due to the discrete-amplitude there will be quantization noise in the output. According to
Poissons formula, the analog signal spectrum is
∞
1
A(ω) = --- ⋅
T ∑ A(ωT – k ⋅ 2π) ⋅ P(ωT ) (2.1)
k = –∞
where T = 1 ⁄ f u , A = F { a ( t ) } is the signal, and P(ω) = F { p(t) } is the PAM waveform.

For ideal reconstruction – in terms of time-domain properties and not considering the quanti-
zation noise – we would require that p(t) is a sinc according to
sin t
p(t) = --------- , ∀t . (2.2)
t
In the frequency domain this gives an ideal filtering function

 1 ω ≤ fu ⋅ π
P(ω) = F { p(t) } =  , (2.3)
 0 ω ≥ fu ⋅ π

which cuts out the desired part of the spectrum. This is of course not possible to realize in
The Ideal D/A Converter 27
practice and we may instead choose p(t) to be a rectangular pulse instead as
 0≤t<T .
p(t) =  1 (2.4)
 0 else
The output becomes sampled-and-hold (S/H) during one update period. In the frequency
domain this corresponds to a sinc as
sin ωT
P(ω) = F { p(t) } = ---------------- . (2.5)
ωT
This implies that the signal will not be completely filtered out at frequencies above f u ⁄ 2 .
Therefore, a so called image-rejection filter is needed at the output of the DAC in order to
attenuate the images. A low pass filter, as is illustrated in Fig. 2.2, is used to do this operation.
DAC LP
Figure 2.2 Image-rejection filter (LP) is used at the output of the DAC to reconstruct the signal.
In Fig. 2.3 (a) we illustrate how the signal spectrum is repeated and weighted as given by
Poisson’s formula in (2.1) for a DAC with sample-and-hold function. The solid line indicates
the characteristics of the sinc in the frequency domain. The dash-dotted line indicates the
desired filtering function of an ideal LP filter. In Fig. 2.3 (b) we show the signal spectrum as it
has been weighted by the sinc function. Within the signal band (in this case it is from f = 0
to f = f u ⁄ 2 ) we see that the signal spectrum is attenuated, especially at the higher frequen-
cies. In Chapter 3 we will further discuss the influence of the sinc weighting.
Signal frequency spectrum Signal frequency spectrum

Amplitude V/sqrt(Hz)
0.5 1 2 3 0.5 1 2
Normalized frequency Normalized frequency
(a) (b)
Figure 2.3 Output signal spectrum with images at centers of the update frequency.
2.2.1 Ideal Transfer Function

The static, ideal DC transfer function of a DAC is given by a mapping of a set of input codes
onto a set of output amplitude levels. This is illustrated for a linear DAC in Fig. 2.4. Depen-
dent on the DAC architecture the choice of the code set varies. In the static case the output
amplitude (current, voltage, etc.) of the DAC can be written
M
A out = ∑ wm ⋅ bm (2.6)
m=1
where w m is the corresponding weight for the m -th bit b m , and M is the number of bits. The
output amplitude is generated by weighting the input bits, where the weights are implemented
with analog components. The input code is
X = ( b M , b M – 1, …, b 1 ) (2.7)
where b M is referred to as the most significant bit (MSB) and b 1 as the least significant bit
(LSB). It is clear that for a binary code, with M = N bits, we have 2 N differerent codes.
DAC DC transfer characteristics
6
Output amplitude level
0 1 2 3 4 5 6 7
Input value
Figure 2.4 Output amplitude levels as function of the input digital codes.
The set of output amplitude levels is given by

A min, A min + ∆, …, A max – ∆, A max (2.8)
where ∆ is the amplitude level corresponding to one LSB. Sometimes, we also refer to this
amplitude level as simply “one LSB”. The full-scale output amplitude is given by
FS = A max – A min . The output LSB step compared to the full-scale output is referred to as
the converter’s resolution
FS
R = ------ . (2.9)
∆
The resolution can also be expressed in bits as
The Ideal D/A Converter 29
FS
R = log2 ------ (2.10)
∆
and with a binary code, we have
2N ⋅ ∆
R = log2 -------------- = N . (2.11)
∆
2.2.2 Codes for D/A Conversion

In DACs it is common to use redundant codes, i.e., M > N , although the number of output
amplitude levels is not more than 2 N . A nonredundant code would have M = N . Some dif-
ferent codes [21] that can be used for D/A conversion are shown in Table 2.1 and briefly
described in the following. Notice that, although the input code may be given by a thermome-
ter code where the number of bits is higher than for a binary code, we still refer to the resolu-
tion as an N -bit resolution according to (2.10).
Nonredundant codes, M = 3 Redundant codes, M > N

Decimal
number 2’s Offset Signed- “Walking Thermometer Linear
complement binary digit one” M = 7 M = 4
+7 111 1000000 11111111 1100

+6 110 0100000 0111111 1010
+5 101 0010000 0011111 1001
+4 100 0001000 0001111 100
+3 011 011 011 0000100 0000111 0100
+2 010 010 010 0000010 0000011 0010
+1 001 001 001 0000001 0000001 0001
+0 000 000 100, 000 0000000 0000000 0000
-1 111 101
-2 110 110
-3 101 111
-4 100
Table 2.1. Some digital codes used for D/A conversion.
2’s complement
The 2’s complement is nonredundant and the output amplitude is given by a one-to-one map-
ping of the input signal, i.e., M = N . The weights are given by
w m = 2 m – 1 for m = 1, …, N – 1 and w N = – 2 N – 1 . (2.12)
Both negative and positive numbers can be converted with the 2’s complement-coded DAC.
Offset binary
The binary offset is nonredundant as well and the output is given by a one-to-one mapping of
the input, i.e., M = N . The weights are given by
w m = 2 m – 1 for m = 1, …, N . (2.13)
Only positive numbers can be realized with the offset binary coded DAC. Since it is easier to
implement positive weights only due to matching reasons, the binary offset code is widely
used, and throughout the thesis, when illustrating the operation of the DAC, we will mostly
use the binary offset code.
Signed-digit
The signed-digit code is nonredundant and the output, except for the zero value, is given by a
one-to-one mapping of the input value. The zero can be represented by either 100...000 or
000...000. We have M = N where the weights are given by
w m = ( – 1 ) w N ⋅ 2 m – 1 for m = 1, …, N – 1 . (2.14)
Both negative and positive numbers are represented with the signed-digit code.
“Walking one”
The “walking one” code is nonredundant, i.e., every word corresponds to one and only one
output analog value. The weights are given by
w m = 2 m – 1 for m = 1, …, M , (2.15)
where M = 2 N – 1 is the number of bits and weights. The walking-one code is similar to the
thermometer code and is mostly used for weight selection in for example a resistor-string D/A
converter (see Sec. 3.5.3).
Thermometer code
The thermometer code is redundant and hence several different input codes can generate the
same output signal. All weights are equally large and given by
w m = 1 for m = 1, …, M . (2.16)
This implies that in a thermometer code the number of bits is given by
M = 2N – 1 . (2.17)
For higher resolutions we have that 2 N » N and hence there are many codes generating the
same output. For example, the codes 1000000, 0100000, 0010000, 0001000, 0000100,
0000010, and 0000001, all give the same output corresponding to the decimal value; 1. In
fact, there are
 M =  2 N – 1 , m = 0, …, 2 N – 1 (2.18)
 m  m 
different codes corresponding to the same analog output corresponding to the decimal value
m . This redundant property is very advantegous in some implementations, and it should be
used in order to manipulate the digital input to gain a higher DAC performance. This is also
Static Performance 31
discussed in Chapter 7.
The thermometer code is widely used in D/A converters since a number of weights are equal
and hence they can be laid out with special techniques to achieve a good device matching.
With a thermometer coded input, unwanted glitches can be minimized.
Linear code
The linear code is also redundant, but the weights are given by
w m = m , for m = 1, …, M . (2.19)
The required number of bits (and weights), M , is found by comparing the total sum of
weights as
M N
∑ ∑
m–1
m = 2 = 2N – 1 , (2.20)
m=1 m=1
giving
M ⋅ (M + 1)
----------------------------- = 2 N – 1 . (2.21)
2
To find the best integer value on M we have the upper bound as
M = 1 + 8 ⋅ (2N – 1) – 1
-------------------------------------------------- . (2.22)
2
For high resolutions, i.e., N is large, we have that
N+1
-------------
M≈ 2 2 . (2.23)
The code is redundant and, for example, the codes 1000 and 0101 give the same output cor-
responding to the decimal value 4. The linear code is a code in-between the two extremes of
the binary and thermometer code. The advantages and disadvantages of using the linear code
in D/A conversion is discussed in Chapter 7.
2.3 Static Performance

Dependent on application, different performance measures are used to characterize the quality
and performance of a D/A converter. In many telecommunication applications, multi-tone sig-
nalling is used and in those cases (or in general), static measures or even single-tone measure-
ments will not give all the necessary information to fully characterize the DAC.
In this section we outline some of the most common static performance measures, such as the
quantization noise, gain and offset error, differential nonlinearity (DNL), and integral nonlin-
earity (INL).
2.3.1 Quantization or Truncation Noise

Dependent on one’s view, the DAC does not perform any quantization or truncation as long as
the resolution of the converter is as high (or higher) as the input word length. Eventhough, we
will compare the “true” output of the DAC with a corresponding “wanted” analog signal. We
refer to the difference between them as the quantization (or truncation) error. Previously, we
only plotted the output values at discrete points as shown in Fig. 2.4, to make the figures sim-
pler to interpret, we will in the following plot the continuous-time output when increasing the
digital input slowly. We assume that the update period is very long and we will therefore not
“see” the settling. When applying a ramp at the input of a 3-bit offset-binary coded DAC we
get the actual output (solid) as illustrated in Fig. 2.5 (a) The dashed line indicates the ideal
behavior if we would have an infinite number of bits. The input codes are 000, 001, ..., 110,
111 and the converter performs a uniform quantization, i.e., for all codes the changes in out-
put amplitude are equally large between two consecutive codes (assuming an ordered set).
DAC DC transfer characteristics DAC truncation error characteristics
8
7
Error signal [LSB]

1
5
4
3
0
2
1
0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
Input value / Time Input value / Time
(a) (b)
Figure 2.5 Transfer function (a) and quantization error (b) for a 3-bit DAC when ramping the input.
Solid lines illustrate the actual behavior and dashed lines the ideal behavior.
Concludingly, throughout the thesis we refer to an ideal DAC as a DAC where the output is
sampled-and-held, hence the output is piecewise linear. Hence the DAC modulates the input
signal with a square pulse function, p T (t) , of duration T and the output for the general case of
N bits is given by a staircase function as
2N – 1 2N – 1
A(t) = ∑ X (k) ⋅ ∆ ⋅ p T (t – kT ) = ∆ ⋅ ∑ k ⋅ p T (t – kT ) for 0 ≤ t ≤ 2 N ⋅ T (2.24)
k=0 k=0
where
 0≤t≤T .
p T (t ) =  1 (2.25)
 0 else
For the static case, we assume that the time interval, T , is large enough to guarantee settling
with an insignificant small settling error. The wanted output (dashed in Fig. 2.5 (a)) is
∆
Â(t) = t ⋅ --- for 0 ≤ t ≤ 2 N ⋅ T . (2.26)
T
We have the difference signal, the quantization error, as
ε(t) = Â(t) – A(t) . (2.27)
This is illustrated in Fig. 2.5 (b). We see that with this definition (2.27), there is an offset level
of ε os = ∆ ⁄ 2 , but this will not be considered as a quantization error. Neglecting this offset,
we can find the RMS value of the error. It is obvious that the RMS value of ε over the whole
ramp is the same as during one time period T . We have
T T
 dt –  ∆ ∆2
1 t 2 2
1
= --- ∫ ε 2(t) dt – ε os  = -----
T ∫ T 
P q = ε RMS
2 2 = --- --- ⋅ ∆ --
- - (2.28)
T  2 12
0 0
and
∆
ε RMS = P q = ---------- . (2.29)
2 3
If the resolution of the data converter is reasonably high (higher than 4 or 5 bits) the error can
be regarded as white noise [9], otherwise if the number of bits is low, distortion components
are also found in the output spectrum. If the conversion error is treated as white noise, the
power spectral density (PSD) will be uniformly distributed over the frequency range. We have
that
Pq ε RMS
2
∆2
S q( f ) = ------------ = ------------ = ------------- , (2.30)
fu ⁄ 2 fu ⁄ 2 6 ⋅ fu
where f u is the update frequency of the DAC.

Sinusoidal signals are often used to characterize a data converter and it is therefore interesting
to calulate the ideal signal-to-noise ratio (SNR) with such an input signal. The maximum
(AC) amplitude without causing saturation of a sinusoidal input signal is approximately
∆ ⋅ 2 N – 1 and the average power of the sine wave becomes
( ∆ ⋅ 2 N – 1 )2
P s = ----------------------------- . (2.31)
2
The SNR of an ideal converter with a sinusoidal input signal is found by combining (2.28)
and (2.31)
P ( ∆ ⋅ 2 N – 1 )2 ⁄ 2 3 2N
SNR = -----s- = -----------------------------------
- = --- ⋅ 2 , (2.32)
Pq ∆ 2 ⁄ 12 2
which is more conveniently expressed in decibel by the well-known formula

SNR = 10 ⋅ log10 ( P s ⁄ P q ) ≈ 6.02 ⋅ N + 1.76 dB. (2.33)
The SNR is increased by approximately 6 dB for each additional bit in the converter. It should
be noted that (2.33) holds if the input is a full-scale sine wave. The effect of having other
types of input signals is discussed in Sec. 2.5.10. Sometimes the SNR with respect to the
quantization noise is referred to as signal-to-quantization noise ratio and denoted SQNR.
In the previous we have assumed that there are no errors in the DAC and the actual (or true)
output, A , is equal to the expected output, Ã . If there would be errors in the converter, we
would not get the uniform staircase output when ramping the input. In Fig. 2.6 we compare
the actual output, A , (with errors) with the expected output, Ã . The error signal, ε , will
change as well, but the DAC errors will introduce components that are not to be considered as
white noise. These components can be extracted as offset and gain errors. Further the gain
errors can be divided into linear and nonlinear gain errors. We have an error signal consisting
of the quantization error and errors due to the nonideal DAC transfer function.
DAC DC transfer with errors
7
0 1 2 3 4 5 6 7 8
Input value / Time
Figure 2.6 Output amplitude levels as function of the input digital codes with (dashed) and without
(solid) errors for a 3-bit DAC.
2.3.2 Offset Error

The output offset, A os , can be found by minimizing the expression
Ã k – A k – A os , k = 0, …, 2 N – 1 , (2.34)
with the least-square method. The output value, A k , is the mapping of the input code X k , and
since we consider the static transfer function, we have X k = k yielding Ã k = k ⋅ ∆ . To per-
form the least-square method, we first find where the derivative of the summed squares with
respect to A os is zero, i.e.
2N – 1
∂
∂ A os ∑ ( Ã k – A k – A os ) 2 = 0 , (2.35)
k=0
which gives
2N – 1
∑ Ã k – A k – A os = 0 (2.36)
k=0
and further we have

2N – 1
1
A os = -----N- ⋅
2 ∑ ( Ã k – A k ) . (2.37)
k=0
We see that the offset, A os , corresponds to the average of all the errors in the converter.
2.3.3 Gain Error

The static, large-signal gain can be of two kinds: linear and nonlinear, as sketched in Fig. 2.7.
Compared to the ideal straight line (dashed), the actual output (solid) has a different slope as
in the linear case (a) or in the nonlinear case (b).
Linear gain error characteristics Nonlinear gain error characteristics

Output amplitude
Output amplitude
Input value Input value
(a) (b)
Figure 2.7 Characteristics of (a) linear and (b) nonlinear DAC gain error.
Linear gain error does not introduce extra distortion as long as the signal is not clipping. The
actual output with linear gain and offset errors can be written as
A = a ⋅ Ã + A os = a ⋅ ( ∆ ⋅ X ) + A os , (2.38)
where Ã = ∆ ⋅ X is the ideal output and a ⋅ ∆ is the actual gain. The actual output for a non-
linear gain can in a simple form be expressed as
A = a ⋅ Ã + b ⋅ Ã 2 + c ⋅ Ã 3 + … + A os , (2.39)
where we have assumed signal-independet parameters for the static case. Nonlinear gain
errors introduce distortion. Assume that we have a second order nonlinear gain error with zero
offset as
A = a ⋅ Ã + b ⋅ Ã 2 . (2.40)
Since we are using offset binary code, a full-scale sinusoidal input signal to an N -bit DAC
would approximately be given by
X = 2 N – 1 ⋅ ( 1 + sin ω 0 T ) . (2.41)
Applying this signal on the DAC described by the nonlinearity in (2.40) gives the actual out-
put
A = a ⋅ ∆ ⋅ 2 N – 1 + b ⋅ ∆ 2 ⋅ 2 2N – 2 +
+ ( a ⋅ ∆ + b ⋅ ∆ 2 ⋅ 2 2N – 1 ) ⋅ sin ω 0 T + b ⋅ ∆ 2 ⋅ 2 2N – 2 ⋅ sin2 ω 0 T =
= a ⋅ ∆ ⋅ 2 N – 1 + 3b ⋅ ∆ 2 ⋅ 2 2N – 3 +
+ ( a ⋅ ∆ + b ⋅ ∆ 2 ⋅ 2 2N – 1 ) ⋅ sin ω 0 T – b ⋅ ∆ 2 ⋅ 2 2N – 3 ⋅ cos ( 2ω 0 T ) . (2.42)
From (2.42) we can for example find the harmonic distortion (HD) as the ratio between the
power of the tone at ω 0 T (the fundamental or first harmonic) and the second harmonic at
2ω 0 T
( – b ⋅ ∆ 2 ⋅ 2 2N – 3 ) 2
--------------------------------------------
2 b 2 ⋅ 2 2 ( 2N – 3 )
HD = ----------------------------------------------------------- = ----------------------------------------------- . (2.43)
( a ⋅ ∆ + b ⋅ ∆ 2 ⋅ 2 2N – 1 ) 2 ( a ⁄ ∆ + b ⋅ 2 2N – 1 ) 2
-----------------------------------------------------------
2
As mentioned previously, offset and linear gain errors may be accepted in some applications
since they do not necessarily degrade the performance (unless the signal is clipping due to too
large errors). Therefore, in order to find the actual nonlinearity measures it is common to com-
pensate the output values for the offset and nonlinear gain errors. This can be done in two
ways, either by letting the straight line between the start and end output values to be the
wanted transfer or by using a best-fit straight line which minimizes the total error. We focus
on the latter approach.
The gain and offset errors, a and A os , are found with the least-square method. We first find
where the derivatives with respect to a and A os are zero, i.e.,
2N – 1 2N – 1
∂
∂a ∑ [ Ã k – ( A os + a ⋅ A k ) ] = – 2 2
∑ [ Ã k – ( A os + a ⋅ A k ) ] ⋅ A k = 0 (2.44)
k=0 k=0
and
2N – 1 2N – 1
∂
∂ A os ∑ [ Ã k – ( A os + a ⋅ A k ) ] 2 = – 2 ∑ Ã k – ( A os + a ⋅ A k ) = 0 . (2.45)
k=0 k=0
We have that the wanted output is given by A˜k = k ⋅ ∆ and (2.44) and (2.45) become
2N – 1 2N – 1 2N – 1
∑ ∑ ∑
2
∆⋅ k ⋅ A k – A os ⋅ Ak – a ⋅ Ak = 0 (2.46)
k=0 k=0 k=0
and
2N – 1 2N – 1
∆⋅ ∑ k–a⋅ ∑ A k – A os ⋅ 2 N = 0 . (2.47)
k=0 k=0
We may also write the gain and offset as

Ã k ⋅ A k – Ã k ⋅ A k
a = ---------------------------------------
- (2.48)
2 2
Ak – Ak
and
A os = Ã k – a ⋅ A k , (2.49)
where the mean values are found over all k , e.g.,

2N – 1 2N – 1
1 ∆ 2N ⋅ (2N – 1)
Ã k = -----N-
2 ∑ Ã k = -----N-
2 ∑ -∆ ≈ 2 N – 1 ⋅ ∆ .
k = ------------------------------
2 ⋅ 2N
(2.50)
k=0 k=0
These parameters should then be used for extracting for example the differential and integral
nonlinearities as described in the next section.
2.3.4 Differential (DNL) and Integral Nonlinearity (INL)

To find the nonlinear behavior of the DC transfer function we use the differential nonlinearity
(DNL) and the integral nonlinearity (INL) [7, 9]. In Fig. 2.8 (a) we show a part of the DC
characteristics for the same DAC as in Fig. 2.6 and we illustrate how the DNL and INL can be
found. The DNL and INL expresses the deviation from the straight line as shown in Fig. 2.5.
DNL expresses how much the difference in output level between two adjacent codes deviates
from the ideal LSB step ∆
DNL k = A k – A k – 1 – ∆ . (2.51)
DAC DC transfer with errors DAC compensated DC transfer characteristics

6
0.5
5
4
DNL5 0
3 INL
3
−0.5
3 4 5 0 1 2 3 4 5 6 7 8
Input value / Time Input value / Time
(a) (b)
Figure 2.8 (a) Nonideal transfer characteristics illustrating INL and DNL errors in a 3-bit DAC and
(b) compensated transfer characteristics.
Actually, the linear gain and offset are not of interest and therefore the measured/actual output
amplitude levels should be compensated for using the amplitude levels given by the best-fit
straight line parameters from (2.48) and (2.49). The best-fit line is given by
A bf = a ⋅ Ã + A os (2.52)
and we have the compensated output values as
A cmp = A – A bf = A – a ⋅ Ã – A os . (2.53)
The compensated transfer function for the case in Fig. 2.8 (a) is shown in Fig. 2.8 (b) and we
have derived a = 0.9452 and A os = 0.2667 .
Using (2.53) in (2.51) we have that
DNL k = A cmp, k + a ⋅ Ã k + A os – ( A cmp, k – 1 + a ⋅ Ã k – 1 + A os ) – ∆ = …

… = A cmp, k – A cmp, k – 1 + a ⋅ ( Ã k – Ã k – 1 ) – ∆ = …
… = A cmp, k – A cmp, k – 1 + ( a – 1 ) ⋅ ∆ . (2.54)
An adjusted DNL value is found if the step changes are compared to the corresponding best-
fit LSB step, a ⋅ ∆ , which gives
DNL k = A k – A k – 1 – a ⋅ ∆ = A cmp, k – A cmp, k – 1 . (2.55)
INL expresses the total deviation of an analog value from the ideal value as
INL k = A k – Ã k = A cmp, k + ( a – 1 ) ⋅ Ã k + A os . (2.56)
Defining INL using the best-fit straight line approach, we have that it is given by
INL k = A k – A bf = A k – ( a ⋅ Ã k + A os ) = …
… = A cmp, k + a ⋅ Ã k + A os – ( a ⋅ Ã k + A os ) = A cmp, k . (2.57)
Hence, the compensated DC transfer characteristics (as examplified in Fig. 2.8 (b)) is equal to
the INL. Usually, the DNL and INL are expressed in the unit of one LSB, and we have that
(2.55) and (2.57) become
A cmp, k – A cmp, k – 1 A cmp, k
DNL k = --------------------------------------------- and INL k = ---------------- . (2.58)
a⋅∆ a⋅∆
In Fig. 2.9 we show the DNL and INL for the corresponding transfer function shown in Fig.
2.8. Although the DNL and INL are defined for all k , it is common to use the worst-case
DNL and INL to express the quality of the converter. In this case we identify them as
DNL = max DNL k ≈ 0.55 and INL = max INL k ≈ 0.34 . (2.59)
k k
From (2.58) we also find that
DNL k = INL k – INL k – 1 (2.60)
which gives the inverse

k
INL k = INL 0 + ∑ DNLi . (2.61)
i=1
The INL and DNL are good measures for identifying which bits that contain the largest error,
since they then show typical behavior. They are also useful to identify the occurance of graded
matching errors.
Compensated DNL Compensated INL
0.5 0.5
DNL [LSB]
INL [LSB]
0 0
−0.5 −0.5
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
Input value Input value
(a) (b)
Figure 2.9 (a) DNL and (b) INL for the transfer function shown in Fig. 2.8.
2.3.5 Monotonic Behavior

If the output is steady increasing with an increasing input, we refer to this behavior as mono-
tonicity [9]. Consider the example of a code transition as illustrated in Fig. 2.10 where the
solid line is the nonideal characteristics and the dotted line is the ideal. We see that between
the code 4 and 5 the output amplitude level is decreasing and hence it describes a nonmono-
tonic behavior, since there will be two input codes (4 and 5) generating the “same” output val-
ues. With same output values, we understand that they are within the same ± ∆ ⁄ 2 decision
range. A nonmonotonic behavior is ususally found at the MSB transitions in binary-wieghted
DACs.
Monotonicity is guaranteed if the deviation from the best-fit straight line is less than half an
LSB, i.e.,
INL k ≤ 0.5 LSB, k = 0, …, 2 N – 1 . (2.62)
(2.62) implies that the DNL error must be less than one LSB [9], i.e.
DNL k ≤ 1 LSB, k = 0, …, 2 N – 1 . (2.63)
The relations above are sufficient to guarantee monotonicity, but the opposite does not hold. A
converter may very well be monotonic although (2.62) and (2.63) are not met. There are some
data converter architectures that are monotonic by design, e.g., thermometer-coded DACs.
Monotonic and non−monotonic behavior

5
3 4 5 6 7
Input value / Time
Figure 2.10 Example of a transfer function of a nonmonotonic DAC.
2.3.6 Nonuniform Quantization

Mostly the quantization is uniform, i.e., the quantization step between two codes is chosen to
be equal for the whole range of the converter. Previously, we have actually assumed that the
input signal is statistically equally distributed over the whole amplitude range, and then the
uniform quantization provides a minimum quantization error. However, when the signal’s
amplitude levels are not equally distributed (which is the case for a sinusoid) it may be more
useful to use a nonuniform quantization [22]. This implies that the quantization step is not
equal for all codes. Instead a finer resolution is used for those ranges where the amplitude lev-
els are concentrated. Normally, this would be for small input signal levels (or arond the DC
level). The DC transfer characteristics of a typical nonuniform quantization is shown in Fig.
2.11. As we see, some amplitude levels are quantized with larger errors, but statistically a
minimum quantization noise is achieved since the probability for these amplitude levels is
lower.
Non−linear gain error characteristics

Output amplitude
Input value
Figure 2.11 DC transfer characteristics of a DAC with nonuniform quantization.

Typically, we have that
2N – 1
∑
2
Pq = ε RMS(k) ⋅ p c(k) (2.64)
k=0
where p c(k) is the probability for the k -th code to occur and
2
ε RMS(k) = ∆ k2 ⁄ 12 (2.65)
is the RMS quantization error and ∆ k is the quantization step for the k -th code. Typically, we
would for uniform quantization require an equal probability, p c(k) = 2 – N , and quantization
step, ∆ k = ∆ , for all codes. We end up with the same result as in (2.28)
2N – 1
∆2 ∆2
Pq = ∑ ------ ⋅ 2 – N = ------ .
12 12
(2.66)
k=0
As a notice, if the input signal is Gaussian distributed, hence the probability for the amplitude
level x to occur is approximately
( x – µ )2
– -------------------
1 2σ 2
p c(x) ≈ -------------- ⋅ e (2.67)
σ 2π
where µ is the mean amplitude value (DC level) and σ is the standard deviation. The mini-
mum error power is
2N – 1 (k + 1) ⋅ ∆
Pq = ∑ ∫ [ x – q k ] 2 ⋅ p c( x ) d x (2.68)
k=0 k⋅∆
where q k is the quantization level for the k -th code. We want to find the q s that satisfy the
following equation
dP q
--------- = 0 , ∀q j , (2.69)
dq j
which implies that

( j + 1) ⋅ ∆
∫ x ⋅ p c(x) dx
j⋅∆
q j = --------------------------------------------
( j + 1) ⋅ ∆
-. (2.70)
∫ p c(x) dx
j⋅∆
(2.70) cannot be solved analytically and instead an approximation has to be done. (2.70) basi-
cally expresses an inverse description of the Gaussian distribution. We can compare this result
with the case of uniformly distributed input signal, where we have p c(x) = 1 ⁄ 2 N for all x .
Inserting this probability in (2.70) gives the desired result
1
-----N- ⋅ [ ( j + 1 ) 2 – j 2 ] ⋅ ∆ 2
q j = --------------------------------------------------------- =  j + --- ⋅ ∆ .
2 1
(2.71)
∆  2
-----N-
2
The gain in performance of using the nonuniform quantization is mostly quite small for our
applications. Simulations show that an improvement in SNR is approximately 4 dB (or half a
bit) for a 256-tone DMT signal with a PAR of approximately 4 if the quantization levels are
distributed as an inverse Gaussian distribution instead of the uniform quantization.
On the A/D-side of course the inverse truncation must of course be applied. Therefore, this
method is not very advantageous in the DSL applications since the distribution of the quanti-
zation levels is heavily dependent on the distribution of the signal. The half-bit gain is not
attractive enough although it is an interesting fundamental result.
2.4 Dynamic Performance

In the previous sections the DAC has been regarded as a discrete-time circuit, hence the ana-
log output levels are only valid at discrete time instants, i.e., the static, settled values. To find
the true performance we must consider the entire shape of the analog output waveform. Typi-
cally, we have transients due to switching of analog elements. These transients are signal-
dependent and hence of dynamic nature [9]. Due to the finite update period, there will be set-
tling errors which may be of both linear and nonlinear character. Other phenomena, such as
glitches and clock feedthrough (CFT) also count as dynamic errors. The dynamic error
sources will have a large impact on the DAC performance and it will become even more dom-
inating for higher signal levels and higher signal and clock frequencies.
Consider the example in Fig. 2.12 showing the “ideal” DAC output (dashed) and the actual
DAC output (solid). When the input of the DAC is changed, the analog output should ideally
change from the ideal start value, Ã k , and settle towards the end value, Ã k + 1 . In the previous
case, we have assumed that the update time T u is infinite. In reality, the DAC cannot change
its output value instantaneously, the limited update time will cause a settling error and hence
the start value, Ã k , would be incorrect, since it should be modified by the settling error from
the previous settling phase. The settling in Fig. 2.12 is given by a two-pole system.
To simplify the presentation we use a single-pole, linear system instead. The output amplitude
would in this case be
t – kT
 – ----------------u-
A(t) = A k + ( Ã k + 1 – A k ) ⋅  1 – e τ  for t > kT u , (2.72)
 
where A k = A(kT u) is the initial value at t = kT u and τ is the time constant of the DAC.
The settling error is found at the switching time instant, t = kT u + T u ,
ε s, k + 1 = ε s(kT u + T u) = A k + 1 – Ã k + 1 = A(kT u + T u) – Ã k + 1 = …
–T ⁄ τ –T ⁄ τ
… = A k + ( Ã k + 1 – A k ) ⋅ ( 1 – e u ) – Ã k + 1 = ( A k – Ã k + 1 ) ⋅ e u . (2.73)
Further, we have that settling error at the previous time instant is given by
Dynamic Performance 43
Output settling behavior
Amplitude level
Time
Figure 2.12 Actual output signal and ideal output signal (dashed) of a DAC.
ε s, k = A k – Ã k . (2.74)
Combining (2.73) and (2.74) gives that
ε s, k + 1 = [ ε s, k – ( Ã k + 1 – Ã k ) ] ⋅ e –T u ⁄ τ (2.75)
or
ε s, k + 1 – ε s, k ⋅ e –T u ⁄ τ = – ( Ã k + 1 – Ã k ) ⋅ e –T u ⁄ τ . (2.76)
Applying the z-transform on the equation above gives
- ⋅ e –T u ⁄ τ ⋅ Ã(z) .
z–1
ε s(z) = – ----------------------
–T u ⁄ τ
(2.77)
z–e
Hence, with the ideal output, Ã , the settling error is found as the output from a linear system
with the transfer function
- ⋅ e –T u ⁄ τ .
z–1
H s(z) = – ----------------------
–T u ⁄ τ
(2.78)
z–e
Therefore, we refer to this type of settling error as linear, since the T u is a parameter chosen
to be fix during operation. We see that for DC input,
z = e j ⋅ 0 ⋅ Tu = 1 (2.79)
and we have that

H s(z) ≈ 0 , (2.80)
hence there is no linear settling error present. At frequencies near the Nyquist frequency,
z = e j ⋅ π ⋅ T u = –1 , (2.81)
we have the maximum value given by
- ⋅ e –T u ⁄ τ .
2
H s(z) = – -----------------------
–T u ⁄ τ
(2.82)
1+e
These issues are also further discussed in Sec. 4.3.1.
In reality, the actual start and final values, A k and A k + 1 , will not only be modified by the lin-
ear settling errors. They will also be influenced by circuit imperfections, glitches, signal-
dependent time constants τ = τ(t) , etc.
The required settling time is usually larger for larger output steps. The reason for this is that
the settling usually can be divided into two phases, a nonlinear slewing phase and a linear set-
tling phase. The slewing phase should be as small as possible since it both increases the set-
tling time and introduces distortion in the analog waveform. The slewing is normally caused
by a too small bias current in the circuit driving the output, e.g., output voltage buffers, and is
therefore higher for large steps since more current is needed. Distortion is introduced and it is
therefore important to try to keep the nonlinear portion of the settling as small as possible.
This is further discussed in Sec. 2.4.1.
There are additional dynamic error sources that can both change the final value and the shape
of the settling waveform, as for instance glitches and clock feedthrough (CFT) [7]. Glitches
depend on how the internal switches are individually skewed in time and CFT arises due to
the capacitive coupling between the digital switching signal and the analog output signal.
Another dynamic error is the sampling-time uncertainty, which can be considered to be a sig-
nal-dependent settling error.
2.4.1 Nonlinear Settling

For example, the current-steering DAC without output buffers (Sec. 3.6.1) does not suffer
from slew rate limiting, but on the other hand it is much more sensitive to the variations in the
output impedance. Using output buffers in this DAC architecture makes the converter less sen-
sitive to limited output impedance, but on the other hand, we now have the problem with SR
limiting and the increased circuit complexity.
Typically, the SR is limited by the achievable, maximum slope of the output. Assuming that
the output is described by a voltage level, we have that
dV out(t) i out(t) 1 I out, max

SR = max ------------------- - = ------
- = max ------------- ⋅ max i out(t) = ------------------
-, (2.83)
t dt t CL CL t CL
where I out, max is the maximum current that can be directed to the output and C L is the
capacitive load associated with the output. For linear settling, we must guarantee that the time
constant of the system is signal-independent and that the SR is not limiting the slope of the
output signal. For a linear, single-pole system, (2.72), the largest slope is given by the deriva-
tive of the output signal at the initial time instant, hence
dV out(t) Ã k + 1 – A k 1
max ------------------- - = --- ⋅ max Ã k + 1 – A k .
- = max --------------------------- (2.84)
t dt t τ τ t
Although it might not be likely for low signal-to-clock frequency ratios, the maximum change
of amplitude could be rail-to-rail, and we would get
dV out(t) 1 N
- ≈ --τ- ⋅ 2 ⋅ ∆ .
max ------------------- (2.85)
t dt
We should for worst-case settling require that
1
SR ≥ --- ⋅ 2 N ⋅ ∆ . (2.86)
τ
Using (2.83) in (2.86) gives
I out, max 1
- ≥ --- ⋅ 2 N ⋅ ∆ .
------------------ (2.87)
CL τ
For the current-steering DAC architecture without buffers, we have that
I out, max
∆ = ------------------
- ⋅ RL . (2.88)
2N
The time constant is likely to be determined by the load impedance and hence given by
τ = RL ⋅ C L . (2.89)
The comparison in (2.87) becomes for the current-steering DAC

I out, max 1 I out, max I out, max
- ≥ ----------------- ⋅ 2 N ⋅ ------------------
------------------ - ⋅ R = ------------------
- (2.90)
CL RL ⋅ C L 2N L CL
which states that there is no slew-rate limiting for this architecture.
2.4.2 Glitches
Glitches occur when the switching time instants of different bits in a DAC are unmatched.
This can depend on matching errors in switches and driver circuits, time skew between
switching signals, voltage-dependent CMOS switches, etc. For a short period of time a false
code could appear at the output. For example, in a binary-weighted DAC, if the code transi-
tion is
0111…111 → 1000…000
and the MSB is switching faster than the LSBs, the code 11…111 may be present for a short
period of time. This is a major code transition and the DAC will represent the maximum out-
put value and hence a large glitch will appear at the output. The glitch adds a signal-depen-
dent error to the output signal, that degrades the performance. The impact on the output signal
can be characterized by the average energy or power of the glitches.
In Fig. 2.13 we illustrate the typical glitch behavior at the DAC output. The dotted line indi-
cates the ideal transfer and the solid line the actual behavior. The glitch is modeled as a pulse
as dashed in the figure. This pulse has an amplitude of A g, k and a time-duration, T g, k . The
glitch energy during the time interval kT u ≤ t ≤ ( k + 1 )T u is given by
E g, k = A g2, k ⋅ T g, k . (2.91)
Example of glitch behavior
Output amplitude
Ag
Tg
Time
Figure 2.13 Glitch modeled as a pulse with height Xg and duration Tg.
To simplify the model, we may fix T g, k to an average glitch duration, T g , and then slightly
modify the glitch amplitudes A g, k . Assume that the input signal is periodic with time period
T s = K ⋅ T u . The average glitch power will become
K K
1 Tg
P g = ----- ⋅
Ts ∑ E g, k = ------ ⋅
Ts ∑ Ag2, k . (2.92)
k=1 k=1
However, it should be mentioned that the glitches are very hard to model, both the amplitude,
A g, k , and the time periods, T g, k , are nearly impossible to predict. The glitch errors vary more
or less randomly when code transitions are not periodically repeated. Although the error is
signal-dependent, the power of the glitch typically spread over the frequency range as noise,
dependent on the probability for a certain code transition to occur. For example, the MSB
glitch is the largest, but we also have to consider the probability for the MSB to switch, etc.
Typically, the glitch is dependent on the number of bits that are switching between two con-
secutive input values. This also implies that the glitches are dependent on the signal fre-
quency, since with higher signal-to-update frequency ratio (SUFR) the switching activity is
higher.
One way to characterize the impact of the glitch is to compare its energy with the energy of 1/
2 LSB. To guarantee that the induced energy is not large enough to degrade the SNR. We con-
sider the worst-case that occurs during the major code transitions, and A g, max = 2 N – 1 ⋅ ∆ .
The energy is
E g, max = A g2, max ⋅ T g = 2 2N – 2 ⋅ ∆ 2 ⋅ T g . (2.93)
This energy can be compared to the LSB energy during one update period
E LSB = ∆ 2 ⋅ T u . (2.94)
We have that
E g, max < E LSB ⁄ 2 , (2.95)
which gives the upper bound on the glitch duration
Tu
T g < --------------- . (2.96)
2 2N – 1
Hence we need to design for very low glitches as the resolution of the converter increases. If
we have an update frequency of 2.208 MHz and a 14-bit DAC, the glitch duration must be less
than 3.4 fs. This is with today’s technologies nearly impossible to achieve.
With specific de-glitching circuits, the glitches are attenuated and in practice these circuits are
low pass (LP) filters [9]. However, they increase the complexity of the circuit. Another way to
relax the upper bound (2.96) is to use thermometer coding or segmentation (Sec. 3.5.2 and
Sec. 3.5.5) of the input data. In that case, the bound on the glitch duration becomes
Tu Tu
T g < -----------------------------
- = --------------- ⋅ 2 2M – 2 , (2.97)
2 ⋅ ( 2 N – M )2 2 2N – 1
where 1 ≤ M < N is the number of segmented bits. Hence, we relax the bound by a factor of
2 2 ( M – 1 ) compared to the result in (2.96). For a 14-bit DAC with 6-bit segmentation and an
update frequency of 2.208 MHz, we have that the glitch duration must be less than 3.5 ps.
This is still a tough specification. One can still argue if the model is valid and as mentioned,
one should consider the probability for the glitches to occur. It is also rather unlikely that the
glitch amplitude at MSB transitions is as large as A g, max = 2 N – 1 ⋅ ∆ .
Another model is to consider the glitch area [9], i.e., amplitude times time duration,
α g = T g ⋅ A g , and compare it to half the LSB area, i.e., α LSB = ∆ ⋅ T u ⁄ 2 . If the glitch area
is less than the LSB area, α g, max < α LSB , the performance is not degraded. If we once again
consider the MSB glitch, we have that
∆ ⋅ Tu Tu
T g ⋅ 2 N – 1 ⋅ ∆ < -------------- or T g < -----N- . (2.98)
2 2
With segmentation of the MSBs, 1 ≤ M < N , we have
∆ ⋅ Tu Tu Tu
T g ⋅ 2 N – M ⋅ ∆ < -------------- or T g < ---------------------
- = - ⋅ 2M – 2 .
------------ (2.99)
2 2N – M + 1 2N – 1
Using this model, the glitch impulse is specified with the unit [ pV ⋅ s ] .
2.4.3 Clock Feedthrough (CFT)

The concept of clock feedthrough (CFT) can be illustrated by studying the MOS switch in
Fig. 2.14 (a). There is a capacitance, C gs or C gd , between the digital switching signal and the
sensitive analog signal. Due to this capacitive coupling, or the Miller effect, in the switches,
the clock (or digital switching signals) will affect the analog output signal. The CFT arises at
both rising and falling edge of the switching signal [7]. We have examplified the impact of
this on the output voltage by the circuit-level simulation result in Fig. 2.14 (b). In the fre-
quency domain there will be a frequency component at the Nyquist frequency, f u ⁄ 2 , since
CFT occurs twice every update period [23].
Vsw
Cgs
Vin Vout
CL
Vsw
Vin Vout
Qch/2 Qch/2
(a) (b)
Figure 2.14 Illustration of the effect of clock feedthrough on MOS switches. (a) MOS switch and (b)
typical output signal.
In for example current-steering DACs (Sec. 3.6.1) the CFT error can be viewed in a similar
way as glitches, while in e.g. switched-capacitor DACs (SC DACs, Sec. 3.6.2) the CFT will
give an error in the final value [7]. The CFT is reduced when reducing the capacitive coupling
and therefore the switch transistor sizes should be reduced to decrease the size of the parasitic
capacitances [7]. However, with a smaller transistor the on-resistance increases, which may
degrade the performance due to an increased settling time.
2.5 Frequency-Domain Measures

For telecommunication DACs, measures such as INL and DNL, settling time, etc., are not suf-
ficient to characterize performance [23]. It is more convenient to characterize the performance
by using frequency domain measures, such as the SNR and SFDR. The dynamic performance
is usually determined by measuring the performance when applying several single-tone sinu-
soidal inputs at different frequencies. Sometimes multi-tone measurements are more informa-
tive, since the signal is more realistically distributed throughout the amplitude domain [24].
Several standards for telecommunication applications use multi-tone signals, e.g., OFDM [25]
and DMT [3]. Basically, the frequency-domain measures are divided into single-, dual-, and
multi-tone measures. The single-tone measures may not be sufficient to characterize convert-
ers for multi-tone applications [24].
In Fig. 2.15 we show the output spectrum, a fast Fourier transform (FFT) of the simulated out-
put signal from a nonlinear DAC. The input is a full-scale (FS) sinusoid, the resolution is 14
bits, and the SUFR is approximately 1/6. Due to quantization there is a noise floor and due to
nonlinearities there is distortion. The spectrum is normalized with respect to the power of the
fundamental (i.e., first harmonic) and the DC term is not shown in the figure. We find the sec-
ond harmonic at approximately –92 dBFS, the third at –96 dBFS, etc. dBFS denotes the dis-
tance in terms of power to the FS signal power. Also illustrated in the figure is the spurious-
free dynamic range (SFDR = 92 dB), which in this case is determined by the second har-
monic.
Frequency-Domain Measures 49
Negative DAC Output
fundamental SFDR
−36
Power [dBFS] 2nd harm

−72
3rd harm
noise floor
−118
0.125 0.25 0.375 0.5

Normalized frequency
Figure 2.15 Frequency spectrum of a single-tone output signal from a nonlinear DAC with typical fre-
quency-domain measures.
In Fig. 2.16 we show the spectra of the output signals from the same DAC as was used for the
simulation resulting in Fig. 2.15. We have applied a (a) dual-tone signal and (b) multi-tone
signal. For the dual-tone signal, we have used signal frequencies that are relatively prime to
eachother and the update frequency. In the multi-tone signal, the tones’ frequencies are at
multiples of the same frequency. Illustrated in the figures are for example the intermodulation
distortion (IMD) and the multi-tone power ratio (MTPR). We show in Fig. 2.16 the IMD 2, –1
and IMD 2, 1 . This notation is explained in Sec. 2.5.8.
Negative DAC Output Negative DAC Output

0 0
−36 −36
MTPR
Power [dBFS]
Power [dBFS]
IMD3,1
IMD2,-1
−72 −72
−118 −118
0.125 0.25 0.375 0.5 0.125 0.25 0.375 0.5

(a) (b)
Figure 2.16 Frequency spectrum of a (a) dual-tone and (b) multi-tone output signal from a nonlinear
DAC with typical frequency-domain measures.
In the following we discuss some other frequency-domain measures.

2.5.1 Harmonic Distortion (HDk)

The harmonic distortion with respect to the k -th harmonic, HD k , is the power ratio between
the k -th harmonic and the fundamental
Pk
HD k = 10 ⋅ log10 ------ (2.100)
P1
where P 1 is the power of the fundamental (typically the signal, P s = P 1 , for a sinusoid
input). P k is the power of the k -th harmonic. For example, we have that HD 2 ≈ 92 dB and
HD 3 ≈ 96 dB for the signal in Fig. 2.15.
2.5.2 Total Harmonic Distortion (THD)

The total harmonic distortion (THD) is the ratio of the total harmonic distortion power and the
power of the fundamental in a certain frequency band, i.e.,
∞
∑k = 2 P k ∞
P
THD = 10 ⋅ log10 ----------------------- = 10 ⋅ log10
P1 ∑ -----k-
P1
(2.101)
k=2
where P 1 is the power of the fundamental (typically the signal, P s = P 1 , for a sinusoid
input). P k is the power of the k -th harmonic. Since there is an infinite number of harmonics
the THD is usually calculated using the first 10–20 harmonics or until the harmonics no
longer can be distinguished from the noise floor [26]. The THD for the signal in Fig. 2.15 is
approximately 89 dB.
2.5.3 Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio of the power of the fundamental and the total
noise power within a certain frequency band, excluding the harmonic components, i.e.,
Ps
SNR = 10 ⋅ log10 ------ (2.102)
Pn
where P s is the signal power and P n is the noise power. The SNR is sometimes also
expressed in dBFS to relate the noise level to the full-scale input power.
2.5.4 Signal-to-Noise and Distortion Ratio (SNDR)

The signal-to-noise-and-distortion ratio (SNDR) is the ratio of the power of the fundamental
and the total noise and distortion power within a certain frequency band, i.e.,
Ps
SNDR = 10 ⋅ log10 ----------------------------------
∞
- (2.103)
Pn + ∑ Pk
k=2
The SNDR is also sometimes expressed in dBFS. Expressing (2.101), (2.102), and (2.103) in
a linear scale gives the obvious relation
SNDR = SNR + THD . (2.104)
The SNDR of the signal in Fig. 2.15 is approximately 85 dB.

2.5.5 Spurious-Free Dynamic Range (SFDR)

The spurious-free dynamic range (SFDR) is the ratio of the power of the signal and the power
of the largest spurious (unwanted) tone within a certain frequency band. SFDR is usually
expressed in dB as
Ps
SFDR = 10 ⋅ log10 ------ , (2.105)
PX
where P s is the power of the signal and P X is the power of the spurious. Notice that the spu-
rious need not to be a harmonic. The SFDR can also be expressed with the full-scale input
(dBFS) as reference rather than the input signal power.
If the spurious is a harmonic tone and if the next spurious tone is several dBs below that level,
we have that (expressed in a linear scale) the total harmonic distortion is approximately equal
to the inverse of SFDR
1
THD ≈ --------------- . (2.106)
SFDR
Typically, if the nonlinearity is of intermediate proportion the SFDR will also determine the
SNDR and give a picture of the overall performance of the DAC. The SFDR of the signal in
Fig. 2.15 is approximately 92 dB.
2.5.6 Effective Number Of Bits (ENOB)

The effective number of bits (ENOB) is mostly used for characterizing A/D converters [9], but
in some cases it is used for DACs for convenience. Using the result in (2.33), we find the cer-
tain number of bits that a measured SNDR corresponds to. The ENOB is determined by
SNDR – 1.76
ENOB = -------------------------------- . (2.107)
6.02
The effective number of bits for the signal in Fig. 2.15 is approximately 13.7.
2.5.7 Multi-Tone Power Ratio (MTPR)

For multi-tone transmission schemes it is hard to identify the distortion terms, since the signal
frequencies are at multiples of a fundamental frequency that is a fraction of the update fre-
quency. Therefore distortion terms, harmonics, are added to the signal tones and cannot easily
be detected. One method to find out the distortion is to apply a number of tones (at multiples
of the fundamental frequency, ω 0 ), all with the same amplitude, A . Some tones are intention-
ally left out, and the distortion terms that occur at these positions determine the multi-tone
power ratio (MTPR). The MTPR is defined as
PT
MTPR = ---------------
-, (2.108)
max P k
k
where P T = A 2 ⁄ 2 is the power of one tone or the average tone power and P k is the power of
the tones found at the left-out positions. This is also depicted in Fig. 2.16 (b), where 25 tones
have been applied. At two frequencies tones have been excluded. The nonlinearity of the con-
verter introduces harmonics at these positions, and MTPR can be determined by the power of
these harmonics. We find the MTPR to be approximately 80 dB.
There are also variations on the definition of MTPR. We can for example plot MTPR as a
function of the left-out frequencies or plot MTPR as a function of the peak-to-average ratio
(PAR) [24], etc.
2.5.8 Intermodulation Distortion (IMD)

Intermodulation distortion (IMD) appears when the input is a dual- or multi-tone signal.
Assume that two tones with the frequencies f 1 and f 2 are applied to the converter with sam-
pling rate f u . Intermodulation distortion will appear at the frequencies
k ⋅ f1 + m ⋅ f2 (2.109)
where k and m are integer numbers, and further k ≠ 0 , m ≠ 0 , and f 1 ≠ f 2 . If the sum in
(2.109) becomes larger than f u ⁄ 2 it will fold back into the Nyquist range. The intermodula-
tion distortion is calculated as
IMD k, m = P k, m ⁄ P 1 . (2.110)
where P 1 is the amplitude of the fundamental and P k, m is the power of the tones at the fre-
quencies given by (2.109). For some multi-tone applications the tone frequencies are multi-
ples of a specific fundamental frequency and hence the intermodulation terms will interfere
with other tones, see Sec. 2.5.7. Some IMDs for the signal in Fig. 2.16 (a) are
IMD 2, –1 ≈ 90 dB, IMD 3, 1 ≈ 90 dB.
The IMD is also a useful measure to characterize the linearity of the converter near the speci-
fied bandwidth frequency. Since higher-order harmonics then will be filtered out by the
image-rejection filters, we can instead measure the mixed products to extract information on
the linearity.
2.5.9 Linearity as Function of Amplitude and Frequency

All measures above are in reality both frequency and signal amplitude dependent. With higher
amplitude levels and higher signal and clock frequencies the nonlinearities usually increase.
We may for example plot the simulated SNDR and SFDR as functions of the input amplitude
as illustrated in Fig. 2.17. Typically, the SNDR is increasing with with higher signal ampli-
tudes, since the signal power is increasing. On the other hand, in a real implementation the
SFDR tend to decrease with higher amplitude levels. This is further discussed in Chapter 4
and Chapter 5. Therefore, the peak SNDR (the maximal achievable SNDR) is usually located
below the full-scale input (0 dBFS) [9].
Dynamic range (DR)

Considering the amplitude levels, we define the dynamic range (DR) as [9]
P peak P peak ⁄ P q
DR = 10 ⋅ log10 ------------- ≈ 10 ⋅ log10 ----------------------- (2.111)
P min P min ⁄ P q
where P peak is the signal power giving the peak SNDR and P min is the smallest “reasonable”
signal power where SNDR = 0 dB. Notice that the dynamic range is also dependent on fre-
quency, the higher signal frequency, the lower P peak , etc. For the example shown in Fig. 2.17
we have a dynamic range that is simply determined by the whole range;
SFDR and SNDR vs. amplitude level
84
SFDR
SNDR, SFDR [dB]

72
SNDR
60
48
−24 −18 −12 −6 −3 0

Amplitude level [dBFS]
Figure 2.17 Typical SNDR and SFDR vs. amplitude level for a 14-bit DAC.
6.02 ⋅ N + 1.76 ≈ 86 dB.
Effective resolution bandwidth (ERB)

Since the measures are frequency-dependent we must also be careful to specify the frequency
range in which for example a certain SFDR can be guaranteed. It is common to plot the
SFDR, SNDR, or SNR as function of the SUFR and update frequency. In Fig. 2.18 we show
the measured SFDR for a 14-bit current-steering DAC as function of the update frequency for
two SUFR, 0.03 and 0.06. The effective resolution bandwidth (ERB) is mostly used for char-
acterization of A/D converters and is defined as the input frequency where the SNDR is
reduced by 3 dB (or ENOB by half a bit) [9].
The slope of the curves are also interesting since they describe how the performance degrades.
In the figure this slope is approximately 17 dB per decade.
Measured SFDR vs. update frequency. DAC A and C.

SUFR = 0.03
SUFR = 0.06
70
SFDR [dB]
60
50
5 12.5 25 50 100
Update frequency [MHz]
Figure 2.18 Measured SFDR as function of update and signal frequencies.

2.5.10 Peak-to-Average Ratio (PAR)

For multi-tone transmission we use the peak-to-average ratio (PAR) or crest factor as an addi-
tional signal characterization [23, 24]. In Sec. 1.3.2 we discussed the PAR for DMT signals.
With the PAR value we get additional information on how the amplitude levels of the signal
are distributed. Low PAR indicates a more uniform distribution, which in most cases is advan-
tageous. The PAR is defined as
P peak 1/2
PAR = ------------- , (2.112)
Ps
where P peak is the peak signal power and P s is the average signal power. For a sine wave we
have
A2 1/2
PAR = ------------
- = 2. (2.113)
A2 ⁄ 2
Typically, a sine wave input signal is used for testing converters, but in most practical commu-
nications applications more than one tone are used in the signals. In those cases, we use the
PAR to calculate the SNR. Assuming that the peak signal is FS, the PAR for an N -bit con-
verter is
P peak 1/2
( ∆ ⋅ 2 N – 1 )2 1/2
PAR = ------------- ≈ ----------------------------- . (2.114)
Ps Ps
From (2.114) the average signal power, P s , is
∆ ⋅ 2N – 1 2
P s = --------------------- . (2.115)
PAR
Further, the SNR (with respect to the quantization noise) is given by (2.33) and inserting
(2.115) gives
∆ ⋅ 2N – 1 2
---------------------
Ps PAR
SNR = 10 ⋅ log10 ------ = 10 ⋅ log10 ----------------------------- ≈
Pq ∆ 2 ⁄ 12
≈ 6.02 ⋅ N – 20 ⋅ log10 PAR + 4.77 dB. (2.116)
We see from (2.116) that a small PAR is preferable since it maximizes the SNR.
3 D/A Converter
Architectures
3.1 Introduction
In the previous chapter we outlined a number of measures to characterize and find the perfor-
mance of digital-to-analog converters (DACs). In this chapter we discuss different DAC archi-
tectures and we highlight advantages and disadvantages of the different types.
As was discussed in Chapter 1, DACs can be divided into different groups. Dependent on how
the frequency space is utilized in the conversion, we have the Nyquist-rate, interpolating, and
oversampling converters. First, Nyquist-rate converters (Sec. 3.2) use the whole frequency
range from DC up to half the update frequency which is the maximum frequency for recon-
struction according to the sampling theorem. However, due to the discrete-time properties,
images of the signal appear at multiples of the update frequency and therefore an image-rejec-
tion filter with very narrow transition band is required. This implies a high analog filter order
and circuit complexity. Therefore, it is common to increase the update frequency over the sig-
nal frequency. This is done through interpolation and hence we have the interpolating DACs
(Sec. 3.3). With this approach, the required width of the analog filter’s transition band can be
made much wider and the filter complexity becomes lower. At the same time we have a large
“unused” frequency space where there is no signal power. This can be used for spectral noise
shaping and with modulators the quantization noise can be spectrally moved to higher fre-
quencies where there is no signal. Thereby, we may use a lower-resolution (in terms of num-
ber of bits, not in terms of accuracy) DAC to reach a higher resolution. We refer to DACs with
noise shaping loops (and interpolation) as oversampling DACs (OSDACs) (Sec. 3.4).
Dependent on resolution, application, and technology, one should choose different DAC archi-
tectures. For example, for a low-bandwidth, high-resolution application an oversampling DAC
implemented with the switched-capacitor technique (SC) is a suitable candidate. For high-
speed, medium-resolution application a current-steering DAC using MOS transistors as cur-
rent sources and switches is suitable. Different common DAC architectures are discussed in
55
Sec. 3.5 and in Sec. 3.6 circuit implementations are discussed.
In Sec. 3.7 we give a summary of reported DAC performance throughout the litterature and in
data sheets from vendors.
3.2 Nyquist-Rate D/A Converters

In Nyquist-rate DACs the input signal bandwidth is equal to the Nyquist frequency,
f N = f u ⁄ 2 , where f u is the update or sample frequency. The whole available frequency
range that still guarantees no aliasing according to the sampling theorem is used. This is illus-
trated in Fig. 3.1 (a), where a signal power spectrum is shown (shaded).
Signal frequency spectrum

fu fN
X(n) A(t)
DAC LP
0.5 1 2
(a) (b)
Figure 3.1 (a) Output spectrum from a Nyquist-rate DAC. The images are centered at multiples of the
update frequency. (b) DAC with an image-rejection filter (LP).
Since the output from the DAC is pulse amplitude modulated (PAM) with (mostly) rectangu-
lar pulses, the spectrum is repeated and centered at multiples of the update frequency and
attenuated by a sinc function. This result of the sinc weighting is illustrated by the solid line
and we see that signal is attenuated within the Nyquist range. In Fig. 3.2 we show the sinc sig-
nal power attenuation (in dB) throughout the frequency range. The power attenuation is given
by
π f sig 2 fu π f sig 2
A sinc( f sig ⁄ f u) = – 10 ⋅ log10 sinc ------------- = – 10 ⋅ log10 ------------- ⋅ sin ------------
- . (3.1)
fs π f sig fu
At the Nyquist frequency, f sig = f N = f u ⁄ 2 , the attenuation according to (3.1) is found to

be approximately 3.9 dB.
As sketched in Fig. 3.1 (b) an analog low pass (LP) filter with cut-off frequency f N is used to
attenuate the images (image-rejection filter) and it can also be designed to reduce the effect of
the sinc attenuation within the signal band by amplifying the spectrum at the pass band edge,
i.e., an anti-sinc filter. The filter order becomes high if the attenuation of images must be high
and/or the transition band needs to be narrow. Therefore, it is more common to increase the
Interpolating D/A Converters 57
Attenuation of spectrum due to sinc weighting
Power attenuation [dB]

20.8
17.8
13.3
3.9
0 0.5 1 2 3
fsig / fu
Figure 3.2 Sinc attenuation of the output signal as function of the signal to sampling frequency ratio.
update frequency over the signal frequency to relax the requirements on the analog filters. In
general the Nyquist-rate converter is required for extreme wideband applications where over-
sampling (and interpolation) techniques are impossible due to the high clocking frequencies,
hence basically never used.
Since the digital input signal is of limited resolution, hence the number of bits N , a quantiza-
tion noise is introduced. For higher resolutions this noise is considered to be white and is
equally distributed over all frequencies, i.e., the noise power spectral density (PSD) is con-
stant, S q( f ) = P q ⁄ f N . P q is the total noise power over the whole Nyquist range. The influ-
ence of the DAC output pole, i.e., the bandwidth, will attenuate the noise at higher
frequencies. The signal-to-noise ratio (SNR) with respect to the quantization noise is given by
Ps Ps
SNR = 10 ⋅ log10 ---------------------------
fN
- = 10 ⋅ log10 -----
- dB, (3.2)
Pq
∫ S q( f ) d f 0
where P s is the signal power. For an full-scale single-tone signal, the SNR is found to be
(Sec. 2.3.1)
SNR ≈ 6.02 ⋅ N + 1.76 dB (3.3)
where N is the nominal number of bits in the converter. For lower-resolution DACs the quan-
tization error becomes correlated with the signal which introduces distortion and the noise can
no longer be considered to be white [9].
3.3 Interpolating D/A Converters

To reduce the design effort on the analog filters we use interpolation to increase the update
frequency compared to the signal frequency. The complexity of the digital circuits preceding
the DAC is increased, giving a higher power dissipation and increased chip area. However,
this can be worth the effort, since it simplifies the required analog circuitry become. In Fig.
3.3 we show the symbols of an interpolator (a) and an interpolator combined with filter (IPF).
x(n) y(n) x(n) y(n)

M IPF
(a) (b)
Figure 3.3 Interpolator without (a) and with (b) filters (interpolation filters).
The input signal of the interpolator is padded with zeros which corresponds to the operation

y(n) =  x(n ⁄ M ) n = m⋅M , (3.4)
 0 n≠m⋅M
where M is the rate (or order) of the interpolation and m is an integer. Typically, the interpo-
lation is done in a multi-stage configuration, hence several cascaded interpolators are used.
We will refer to the total interpolation rate as the oversampling ratio (OSR). The new update
frequency of the DAC is denoted f O, u = f u ⋅ OSR and the corresponding Nyquist frequency
is f O, N = OSR ⋅ f N . Notice, that the Nyquist-rate DAC is defined to have OSR = 1. In the
frequency domain, the operation in (3.4) corresponds to
Y ( z) = X ( z M ) , (3.5)
hence, the spectrum will repeat itself M – 1 times in the frequency range up to f O, u . Con-
sider the example in Fig. 3.4 where an interpolation of order 4 is illustrated. In (a) we show
the original signal spectrum and (b) illustrates how the signal spectrum is repeated within the
frequency range. These images are attenuated by the digital filters. The dashed line in Fig. 3.4
(b) shows the corresponding ideal filtering function. In Fig. 3.4 (c) we find the final interpo-
lated signal and the dotted line in the figure illustrates the transition band of the required ana-
log filters at the output. The transition band is now in the order of ( OSR – 1 ) ⋅ f u .
The specification on the interpolation filters is given by the required attenuation of out-of-
band signals. As an example, we assume that a ripple of 1 dB within the passband up to
1.104 MHz is allowed and a attenuation of 60 dB for frequencies above 2.208 MHz. With an
oversampling ratio of 1, this specification must be met with analog filters only. However, for
OSR > 2 we use the digital interpolation filters to relax the design of the analog components.
Using the specification above and applying it on the digital domain, we have (for OSR > 2 )
that 1.104 MHz corresponds to the normalized angular frequency π ⁄ OSR and 2.208 MHz to
2π ⁄ OSR . In Table 3.1 we show some different required filter orders for different oversam-
pling ratios and filter structures.
The infinite-length impulse response (IIR) filters have a lower filter order than the finite-
length impulse response (FIR) filters. However, the design of the IIR filters is more complex,
since a larger effort has to be put on designing them for stability, round-off noise, etc.
For high oversampling ratios, the interpolation filters must be designed for a narrow transition
band. In a single-stage interpolator, this will often require a high filter order and long filter
coefficients. With halfband filters the number of nonzero coefficients can be reduced to the
half. The drawback with halfband filters, though, is that the attenuation at the passband edge
is 3 dB. Some special frequency masking techniques with for example interpolated FIR (IFIR)
filters or similar are also applicable to reduce the overall complexity. More on interpolation
PSD
f
fN
PSD
f
fN fO,N
PSD
f
fN fO,N
Figure 3.4 Illustration of interpolation of order 4. The original spectrum, the interpolated spectrum
with filtering (dashed), and the final interpolated signal are shown.
IIR
FIR
OSR
(Remez) Chebyshev and
Butterworth Cauer (elliptic)
inverse Chebyshev
4 13 12 7 5
8 28 13 8 6
16 57 13 8 6
32 115 13 8 6
Table 3.1. Different digital interpolation filter orders for attenuation of images by more than 60 dB.
filters is discussed in Chapter 6.

Still we need to attenuate the images occuring at multiples of the sample frequency. To illus-
trate the impact on the complexity of analog circuits we once again assume that the attenua-
tion of images must be at least 60 dB. In Table 3.2 we show a comparison of different
required orders for Butterworth, Cauer (elliptic), Chebyshev and inverse Chebyshev approxi-
mations of continuous-time filters. We have not included the influence of the sinc weighting.
By doing that, we can slightly relax the requirement on the attenuation above 2.208 MHz.
Compare with Fig. 3.2 where we see that the minimum sinc attenuation at frequencies above
2.208 MHz is approximately 13.3 dB. This will reduce the filter orders slightly for lower
interpolation ratios.
For most common wideband applications, the interpolating DAC is used.
Chebyshev and Cauer

OSR Butterworth
inverse Chebyshev (elliptic)
1 11 7 5
2 6 5 4
4 4 3 3
8 3 3 3
16 3 2 2
32 2 2 2
Table 3.2. Different continuous-time image-rejection filter orders for stop-band attenuation of 60 dB.
3.3.1 Gain in Resolution Using Interpolation

The interpolation “compresses” the signal spectrum and the signal and quantization noise
power is kept constant within the frequency range from DC to f N . The quantization noise is
determined by the resolution at the input of the interpolator, hence the data word length. How-
ever, now we can utilize the extra frequency range that we gained from the interpolation.
Assume that we use the DAC and interpolator as shown in Fig. 3.5. We have that the resolu-
tion of the input to the interpolator is N bits. The SNR within the Nyquist range for both the
input and output of the interpolator is given by
SNR = 6.02 ⋅ N + 1.76 dB. (3.6)
We use a (sub-)DAC with a lower nominal resolution M , i.e., we through away N – M LSBs.
Thereby the signal becomes truncated and there will be a higher quantization/truncation noise
compared to the original N -bit resolution. The “new” noise is spread evenly throughout – if
M is not too small so that correlation and distortion occur – the frequency range from DC up
to f O, N . As long as we can guarantee that the “new” noise power within the original Nyquist
band, f N , is lower than the “old” noise power we do not loose in performance. The truncation
in combination with an ideal LP filter, will function as a pulse amplitude modulation (PAM)
of the signal.
N M
x(n)
IPF M-bit A(t)
DAC
Figure 3.5 Interpolation together with lower-resolution DAC where the N-M LSBs are discarded.
Consider the definition of SNR in (3.2) applied for the M -bit DAC
Ps Ps
 ----------------------------- fN 
SNR M = 10 ⋅ log10 ----------------------------------
- = 10 ⋅ log - ⋅ -----------
- =
S q( M )( f ) ⋅ f O, N
10
 S ( M )( f ) ⋅ f f O, N 
q N
Ps fN
= 10 ⋅ log10 -----------------------------
- – 10 ⋅ log -----------
- =
S q( M )( f ) ⋅ f N
10
f O, N
Ps
= 10 ⋅ log10 -----------------------------
- – 10 ⋅ log10 OSR dB, (3.7)
S q( M )( f ) ⋅ f N
where S q( M )( f ) is the noise power spectral density. If we assume an ideal LP filter (as shown
in Fig. 3.4 (b)) with cut-off frequency at f N , we only have to consider the SNR within this
frequency range, which is expressed by the first term in (3.7). Hence, we have
SNR = SNR M + 10 ⋅ log10 OSR dB. (3.8)
From (3.8) we can draw the intuitive conclusion that the narrower signal bandwidth compared
to the update frequency (higher OSR), the higher SNR. (3.8) can be written as
SNR = 6.02 ⋅ M + 1.76 + 10 ⋅ log10 OSR dB. (3.9)
From (3.8) and (3.9) we find that for each doubling of the OSR, the effective number of bits is
increased by half a bit. To guarantee that we do not loose in resolution we need to compare
(3.9) with (3.6) and we have
6.02 ⋅ M + 1.76 + 10 ⋅ log10 OSR > 6.02 ⋅ N + 1.76 (3.10)
or
log10 OSR
M > N – ----------------------- ≈ N – 1.66 ⋅ log10 OSR . (3.11)
log10 4
For example, if N = 14 and OSR = 32 , we can use a 12-bit (11.5-bit) DAC. Another
advantage of using a smaller bandwidth is the lower sinc attenuation of signal at the passband
edge (see Fig. 3.2 for f sig ⁄ f u < 0.5 ). The attenuation of the signal at the original Nyquist fre-
quency is given by
πfN 2
π⁄2
A sinc( f N ) = – 10 ⋅ log10 sinc ----------- = – 20 ⋅ log10 sinc ----------- . (3.12)
f O, u OSR
If, for example, OSR = 16 , we have an approximate attenuation of only 0.1 dB.
It becomes obvious from the previous discussion that a high OSR is a good approach to reach
high performance. The advantages are that we may relax the analog image-rejection filters
significantly, we may use a DAC with a lower nominal resolution, and the sinc attenuation of
the signal is lower. Notice, that the linearity of the DAC must still meet the N -bit specifica-
tion. The disadvantages with oversampling are that there is an increased complexity of digital
circuits and the clock frequency, chip area, and power consumption is increased. However,
since the analog filter has a lower order, it will consume less power and occupy less chip area.
3.4 Oversampling D/A Converters (OSDACs)

The strategy with interpolation can be extended. We found in the previous chapter that high
resolutions can be obtained with a low-resolution DAC by using oversampling. The noise
introduced by the lower-bit DAC is spread throughout the frequency domain as white noise.
Using a filter the noise power can be moved out of the signal band, to higher frequencies. We
say that the noise is spectrally shaped or modulated to higher frequencies.
In Fig. 3.6 we show the concept of the oversampling DAC (OSDAC) containing a noise shap-
ing loop (modulator). The input signal is interpolated and hence the update frequency is
increased by a factor of OSR. The modulator reduces the number of bits representing the sig-
nal. Instead of throwing away the LSBs they are now fed back internally. As previously, a
DAC and an image-rejection filter (LP) are used. The LP filter may have to be a higher-order
filter in order to attenuate the out-of-band noise. The analog filter have to be designed with
respect to the modulation and increased noise power at higher frequencies. Typically, the
width of the transition band needs to be narrower and the out-of-band attenuation needs to be
higher.
Typically, the oversampling D/A converter (OSDAC) is preferred in audio applications.
x(n) A(t)
IPF SD DAC LP
N M
Figure 3.6 OSDAC including interpolation, modulation, and filtering.
3.4.1 Noise-Shaping Modulators

The modulator is designed to perform filtering functions [27]. In the simplest case, the input
signal should be low-pass filtered through the modulator. The larger quantization noise power
that is introduced by the modulator should be high-pass filtered. In some designs, variations
such as all-pass and/or band-pass filtering functions, are used instead. Some of these varia-
tions are discussed in Sec. 6.2.2. In Fig. 3.7 we show the schematic views of two different
modulator structures; the signal-feedback (a) and error-feedback (b) modulators. There is a
feedforward filter, H (z) , and a feedback filter, G(z) . The output of the signal-feedback modu-
lator becomes
H (z) 1
Y (z) = ----------------------------------- ⋅ X (z) + ----------------------------------- ⋅ Q(z) . (3.13)
1 + H (z) ⋅ G(z) 1 + H (z) ⋅ G(z)
From (3.13) we identify the signal transfer function (STF) and noise transfer function (NTF)
of the modulator:
H ( z) 1
STF(z) = ----------------------------------- and NTF(z) = ----------------------------------- . (3.14)
1 + H (z) ⋅ G(z) 1 + H (z) ⋅ G(z)
Hence, we should design the filters H (z) and G(z) so that STF becomes an LP or AP filtering
function and the NTF becomes a HP or BP filtering function. From (3.14) we see that
Oversampling D/A Converters (OSDACs) 63
H(z)
H(z) X(z) Y(z)
X(z) Y(z)
G(z)
G(z)
(a) (b)
Q(z)
Q(z)
H(z)
H(z) X(z) Y(z)
X(z) Y(z)
G(z) Q(z)
G(z)
(c) (d)
Figure 3.7 Different sigma-delta modulators. (a) Signal feedback and (b) error feedback. In (c) and
(d) we find the respective noise models for the quantization error in (a) and (b), respec-
tively.
STF(z) NTF(z) – 1
H (z) = ------------------------------------------------- and G(z) = -------------------------- . (3.15)
1 + STF(z) – NTF(z) STF(z)
The output of the error-feedback modulator is given by
Y (z) = H (z) ⋅ X (z) – H (z) ⋅ G(z) ⋅ Q(z) (3.16)
and we identify STF and NTF as

STF(z) = H (z) and NTF(z) = – H (z) ⋅ G(z) . (3.17)
Comparing with (3.15), we have
NTF(z)
H (z) = STF(z) and G(z) = – ----------------- . (3.18)
STF(z)
For the signal-feedback modulator the design of the filtering functions is not as separable as it
is for the error-feedback modulator, where we are able to design H (z) as an AP filter and
G(z) as an HP filter. The filters can be implemented with both inifinite- and finite-length
impulse response (IIR or FIR) filters. The order of the modulators is determined by the order
of the filters, or actually by the order of the NTF. Assume that we want to create a first-order
modulator as described by (3.13). We want
STF(z) = 1 and NTF(z) = 1 – z –1 . (3.19)
This gives for the signal-feedback modulator
1
- and G(z) = z –1 .
H (z) = --------------- (3.20)
1 – z –1
Hence an accumulator (IIR filter) and a delay element (FIR filter). For the error-feedback
modulator we will for the same STF and NTF get
H (z) = 1 and G(z) = – ( 1 – z –1 ) . (3.21)
Hence in the feedback loop we use a HP FIR filter. In Fig. 3.8 we show the corresponding
implementations of the first-order modulators described by (3.19) through (3.21). For a sec-
ond-order modulator we would require STF(z) = 1 and NTF(z) = ( 1 – z –1 ) 2 . For the sig-
nal-feedback modulator we now get
1
- and G(z) = z –2 – 2z –1 ,
H (z) = -------------------------------- (3.22)
1 + 2z –1 – z –2
(IIR and FIR) and for the error-feedback modulator
H (z) = 1 and G(z) = – ( 1 – z –1 ) 2 . (3.23)
Still the feedback filter can be realized with an FIR filter.
Q(z)
z -1 Q(z)
X(z) Y(z)
X(z) Y(z)
z-1
z-1
(a) (b)
Figure 3.8 First-order modulators using (a) signal- and (b) error-feedback.
In Fig. 3.9 the PSD for the 1st-, 2nd-, and 3rd-order modulators are shown. We see that for
lower frequencies the attenuation of the noise is higher for higher modulator orders. There is a
breakpoint where all modulators have equal attenuation. This is at the normalized angular fre-
quency π ⁄ 3 , or at the normalized frequency 1 ⁄ 6 . Typically, the OSR should be high enough
to guarantee that the signal is at lower frequencies than this breakpoint. However, this is
achieved already for OSR = 4 .
Dependent on the number of bits in the output of the modulator they can be divided into
multi-bit and one-bit modulators [27]. For a one-bit (or lower-bit) modulator we have to be
careful with the design of the filtering functions. Since the gain in the feedback loop is high,
the modulator becomes sensitive to stability issues. Especially, for higher-order, lower-bit
modulators, we need to add poles and zeros ( z i ≠ 1 ) to control the cutoff frequency of the
NTF as well as the gain of the feedback.
The modulators are also referred to as sigma-delta modulators, Σ∆ , since they accumulate
(summation – sigma) the difference signal (delta) that is fed back.
Oversampling D/A Converters (OSDACs) 65
Power spectral density of truncation noise
18 3rd
12 2nd
Truncation noise power density [dB]

6 1st
0
0.03125 0.0625 0.125 0.25 0.5

Figure 3.9 Power spectral density for 1st-, 2nd-, and 3rd-order modulators.
Interpolative or multiple-feedback modulator

A popular architecture is the so called interpolative or multiple-feedback (MF) modulator as
illustrated in Fig. 3.10. A number of signal feedback paths and accumulators are used. The
discrete-time accumulators, A(z) , have the transfer function
z –1
A(z) = ---------------
-. (3.24)
1 – z –1
Implemented using a 2’s-complement representation, the accumulators show good noise prop-
erties, since there is no accumulation of round-off noise [28]. The implementation of the mod-
ulator becomes less complex (in terms of number of gates) than for a corresponding
implementation with straight forward filters as shown in Fig. 3.7 (c) and (d). However,
through manipulations of the signal paths, the architecture in Fig. 3.7 can be transformed into
an architecture similar to those shown in Fig. 3.10.
aN-1 a1
A(z) A(z) A(z)

X(z) Y(z)
bN bN-1 b1
Figure 3.10 Interpolative or multiple-feedback modulator structure.
A generalized MF modulator also contains feedforward paths [29]. The output is weighted
and added to all the summation nodes. This gives an additional set of coefficients and
increased freedom to place poles and zeros of the transfer functions.
3.4.2 Improvement in Resolution Using Noise-Shaping

To find how much we gain in SNR by using noise-shaping modulators we investigate the ideal
case with an arbitrary modulator of order L where STF(z) = 1 and NTF(z) = ( 1 – z –1 ) L .
(As mentioned, this is not a practical assumption, since for higher-order modulators we need
to move multiple zeros away from z = 1 to guarantee stability). However, consider the mag-
nitude function of the NTF on the unity circle ( z = e jωT ) :
jωT jωT 2L
----------- – -----------
e 2 – e 2 ωT
NTF(e jωT ) 2 = 1 – e – jωT 2L = ------------------------------- ⋅ 2 j = 2 2L ⋅ sin2L -------- . (3.25)
2j 2
T is equal to the oversampling update period, i.e., T = T u ⁄ OSR = 1 ⁄ ( OSR ⋅ 2 f N ) and
ωT is the normalized signal angular frequency. We identify that f N corresponds to the nor-
malized angular frequency
2π ⋅ f N π
2π ⋅ f N ⋅ T = -------------------------
- = ----------- . (3.26)
OSR ⋅ 2 f N OSR
We want to find out how much noise power there is in the frequency range from DC up to f N .
This is given by
π ⁄ OSR π ⁄ OSR
ωT
P q( L, sb
) = ∫ NTF(e jωT ) 2 dωT = 2 2L ⋅ ∫ sin2L -------- dωT .
2
(3.27)
0 0
Assume that the oversampling ratio is high and for small values of x we have sin x ≈ x .
Hence (3.27) may be written
π
-----------
ωT 2L + 1 OSR π 2L + 1
- ⋅  -------- = ---------------- ⋅  -----------
2 1
P q( L, sb
) ≈ 2 2L ⋅ --------------- . (3.28)
2L + 1  2  0 2L + 1  OSR
The total truncation noise power (from DC up to f O, N ) introduced by the modulator is given
by
SNR = 6.02 ⋅ M + 1.76 dB, (3.29)
where M is the number of bits at the output of the modulator. Within the original Nyquist
band the noise power is found by combining (3.28) and (3.29), hence
SNR = 6.02 ⋅ M + 1.76 – 10 ⋅ log10 P q( L, sb

) = …
π 2L + 1
… = 6.02 ⋅ M + 1.76 + ( 20 ⋅ L + 10 ) ⋅ log10 OSR – 10 ⋅ log10 ---------------- dB. (3.30)
2L + 1
From (3.30) we see that for each doubling of the OSR, we approximately gain ( L + 1 ⁄ 2 ) bits
in resolution. Notice that (see Sec. 8.2) the approximation in (3.28) can be written (3.27) as an
iterative function:
) (OSR) =  4 – ---------
1  22( L – 1) π π
P q( L, sb - ⋅ P q( L, sb– 1 )(OSR) – ------------------ ⋅ sin2 ( L – 1 )  --------------- ⋅ sin ----------- .
 L ⁄ 2 L⁄2  2OSR OSR
(3.31)
DAC Architectures 67
The equation above helps us understand how much the system improves by increasing the
parameters OSR and L . In Fig. 3.11 we have plotted the achievable effective number of bits
(ENOB) when using a sub-DAC with a 6-bit nominal resolution ( M = 6 ) and the modulator
order, L , is varied. The ENOB has been found using the iterative formula in (3.31) and hence
no approximations have been done. We see that there is a clear trade-off between modulator
order and oversampling ratio. If we for example want to reach a 14-bit resolution (i.e., gain 8
bits of resolution), we need a second-order modulator and OSR ≥ 32 , or a third-order modu-
lator and OSR ≥ 16 , etc. Once again, for higher-order modulators the achievable ENOB will
not be as high as found in the figure, since we have added poles and zeros to the noise transfer
function.
Achievable resolution in an L−th order 6−bit modulator

36
OSR = 64
Effective number of bits
OSR = 32
24
OSR = 16
OSR = 8
14
OSR = 4
8
6
0 1 2 3 4 5
Modulator order
Figure 3.11 Simulated achievable ENOB as function of the modulator order and oversampling ratio.
3.5 DAC Architectures

Since the Nyquist-rate converter also is used in OSDACs (but then with a limited input signal
normalized frequency band) we first present some common Nyquist-rate DAC architectures.
We discuss the application areas and highlight some of the advantages and disadvantages with
the different types. As was discussed in Chapter 2 the DAC should (at the static sampling
instants) generate the output amplitude levels as
M
A out = ∑ wm ⋅ bm , (3.32)
m=1
where A out is the output amplitude (voltage, current, or charge), w m is the weight corre-
sponding to bit b m , and M is the number of bits. Given a set of weights, w m , and the binary-
weighted input x , a generalized pseudo-code algorithm that finds the bits b m is given in Fig.
3.12. This algorithm can now be used to find the weights of special D/A architectures with
arbitrary weights.
We divide the DAC architectures into flash and algorithmic. The flash converters take a paral-
lel input code to instantenously control a number of switches in parallel that select a number
set r = x
for m = M downto 1 do
if ( r < w(m) ) then
b(m) = 0
else
b(m) = 1
r = r – w(m)
end if
end for
Figure 3.12 General algorithm for converting codes.
of weights that should be summed. The algorithmic converters take a serial input to control
weights whose contributions are accumulated to generate the output amplitude level after a
certain number of clock cylces. Circuit implementations of the different DACs are briefly dis-
cussed throughout the chapter, but a more thorough discussion is given in Chapter 5 and
Chapter 6. Typically, the flash converters are fast but occupies large chip area. The algorithmic
converters requires smaller area, but unless they are pipelined, the throughput is lower. Pipe-
lining will however increase the chip area.
3.5.1 Binary-Weighted DAC Architecture

The binary-weighted (or binary-encoded or binary-scaled) DAC utilizes a number of elements
(current sources, resistors, or capacitors) that are binary weighted. In the static case, the DAC
output at the time instant nT is
N
∑
m–1
A(nT ) = A os + A 0 ⋅ 2 ⋅ b m(nT ) , (3.33)
m=1
where A 0 is a common gain reference, A os is an offset reference,

b m(nT ) ∈ { 0, 1 }, 1 ≤ m ≤ N , are the input bits, and T is the update period of the DAC. In
Fig. 3.13 (a) we show the concept of the binary weighted DACs. Some techniques to realize
the circuit elements for multiplication and addition operations are discussed later in this chap-
ter (Sec. 3.6). One of the drawbacks with the binary-weighted architecture is that for a larger
number of bits, the difference between the MSB and LSB weights is large and the DAC
becomes sensitive to mismatch errors and glitches [9]. If the matching errors are too large,
monotonicity cannot be guaranteed. A solution to minimize the influence of these problems is
to encode the binary code into a thermometer code (see Sec. 3.5.2). The advantage with the
binary-weighted DAC is that the number of switches and digital encoding circuits is kept at a
minimum.
3.5.2 Thermometer-Coded DAC Architecture

The thermometer-coded DAC architecture utilizes a number of equal-size elements. The
binary input code is encoded into a thermometer code. Generally, with N binary bits, we have
M = 2 N – 1 thermometer bits. The output value is given by
M
A(nT ) = A os + A 0 ⋅ ∑ c m(nT ) , (3.34)
m=1
where c m(nT ) ∈ { 0, 1 }, 1 ≤ m ≤ M are the thermometer-coded bits as examplified in Table

2.1 on page 29. The architecture of the thermometer-coded DAC is shown in Fig. 3.13 (b).
The reference elements are all of equal size and component matching becomes much simpler
than for the binary case.
Considering the transfer function, the thermometer-coded converter is monotonic by design
since when the input value is increasing the bits are turning from 0 to 1 only. The require-
ments on element matching is also relaxed. In fact, as long as the matching error is within a
50-% margin, monotonicity can be guaranteed. Compared to the binary architecture, the
glitching is reduced, since for increasing/decreasing signal value bits are only turned on/off.
Typically, the thermometer-coded DAC architecture is used for low resolutions, say N ≤ 8 ,
since otherwise the encoding circuits becomes too large. For a larger number of bits, the digi-
tal circuits converting the binary code into thermometer code and the number of interconnect-
ing wires grow exponentially. This implies a more complex circuit layout strategy. Instead of
directly realizing the algorithm in Fig. 3.12 tree structures are preferred and these issues are
further discussed in Chapter 5 Chapter 7.
3.5.3 Direct Encoded DAC Architecture

Instead of creating the weights themselves, we could generate the different amplitude levels
directly. The data bits control which level that should be represented at the DAC output. This
is a direct-encoded DAC architecture and it is illustrated in Fig. 3.13 (c).
b1 20 c1 1 d1 1
b2 21 c2 1 d2 2
bN 2N-1 cM 1 dM 2N-1
A0 A0 A0
Aos Aos Aos
A(nT) A(nT) A(nT)
(a) (b) (c)

Figure 3.13 Illustrations of the (a) binary-weighted, (b) thermometer-coded, and (c) direct encoded
DAC architectures.
The DAC output value is given by

M
A(nT ) = A os + A 0 ⋅ ∑ m ⋅ d m(nT ) , (3.35)
m=1
where d m(nT ) ∈ { 0, 1 }, 1 ≤ m ≤ M are bits given by a “walking-one” code as examplified in

Table 2.1 on page 29. For an N -bit DAC we need M = 2 N – 1 . Encoders converting the
binary code into the “walking-one” code have the same complexity as the the ones for the
thermometer-coded DAC. In fact, the two DAC architectures are basically similar. Routing
and occupied chip area become large and complex due to the large number of components. In
terms of propagation time, the encoding circuits can be pipelined and the propagation through
the encoder becomes a minor problem.
The drawback is that we need a large number of elements, since one element and one switch
is needed for each conversion level. A typical implementation using this architecture is the
resistor-string DAC (Sec. 3.6.4) where 2 N – 1 resistors are used to divide a reference voltage
into the different conversion voltage levels. With such an approach, monotonicity can be guar-
anteed.
3.5.4 Linear-Coded DAC Architecture

Between the two extremes; binary-weighted and thermometer-coded, we put the proposed lin-
ear-coded DAC [32, 33, 34, 35]. The architecture is similar to that of Fig. 3.13 where the
weights are linearly increasing. The output level is given by the same expression as for the
direct encoded DAC (3.35) as
M
A(nT ) = A os + A 0 ⋅ ∑ m ⋅ e m(nT ) , (3.36)
m=1
where e m(nT ) ∈ { 0, 1 }, 1 ≤ m ≤ M . However, unlike the direct encoded DAC we allow sev-
eral bits to be 1 at the same time. The number of bits of the linear code is given by
M = 2N + 3 – 7 + 1
------------------------------------ . (3.37)
2
The binary-to-linear encoder becomes complex. The linear DAC shows to have some advan-
tages in terms of linearity and glitch performance over the regular converter architectures as
described above. The properties of linear-coded DACs are further discussed in Chapter 7.
3.5.5 Hybrid DAC Architectures

As has been briefly issued above, the DAC architectures have different advantages and disad-
vantages. Therefore the combination of different techniques can be used to improve perfor-
mance. This is illustrated by the hybrid converter in Fig. 3.14 where the different
subconverters, DAC i , can be of various types. One popular hybrid is the so called segmented
architecture [9, 30]. The more significant bits are encoded into a thermometer code and the
less significant bits are binary weighted. One of the key issues in this kind of hybrid is to find
the optimum number of bits to encode into thermometer code. The increase of digital circuits,
noise, chip area, vs. performance, etc., thereby have to be taken into account.
DAC1
bN DAC2 A(t)
b1
DACL
Figure 3.14 Hybrid DACs use a combination of a number of different types of DACs.
3.5.6 Algorithmic DAC Architecture

The architecture of the algorithmic (or cyclic) DAC differs from the ones mentioned previ-
ously since there is no weight directly associated with a specific bit and a serial input data is
used to control the weights. In Fig. 3.15 we show an algorithmic DAC architecture [30, 31]. It
requires a parallel-to-serial interface where the serial values are stored in a register operating
at a higher speed, T alg , feeding the MSB out first. The amplitudes values of the bits (0 or 1)
are fed into an accumulator, where the input signal is added to the output signal, which is fed
back and amplified by a factor two. The output signal is held by an analog memory cell
(sample & hold). When each word has been processed, the memory is reset to zero or the cor-
responding DC value and the procedure is repeated for the next word. An external S/H holds
the output value until next value in the loop is valid.
reset fu
X bi 1 A0 A(t)
Talg S/H
Parallel-to-serial Aos
2
Figure 3.15 Schematic view of an algorithmic DAC.
The accumulator can also be fed with the LSB first and the gain in the feedback becomes 1/2.
This can be better in terms of noise and error accumulation in the loop.
The algorithmic DAC requires a higher operational speed since the output signal has to be cal-
culated within one update period and we have that T ≥ N ⋅ T alg where N is the number of
bits and T alg is the clock period of the internal S/H. With some modifications the conversion
speed could be increased by only converting the difference signal between two consecutive
words of the input signal. This is similar to the operation of the delta modulator [29]. It should
be noted that the update time must still be N ⋅ T alg to cover the worst case amplitude change
(from maximum to minimum). But for slow varying signals, the settling time becomes lower.
The advantage of the algorithmic DAC is the low number of circuit components: adder, sam-
ple-and-hold, amplifier, and a simple digital register. Typically, the S/H and the feedback gain
can be accomplished with a single SC accumulator [30]. Hence, this architecture can be
designed to have a small chip area. The accuracy of the converter is limited by the accuracy of
the circuit elements (S/H and feedback gain).
Pipelined algorithmic DAC

To increase speed of the algorithmic DAC, the recursive loop can be unfolded and the result-
ing structure can be pipelined [30]. We interconnect N stages and the S/H can work at the
lower T = T u speed. In Fig. 3.16 we show the concept of the pipelined algorithmic DAC.
The design becomes modular and by extending the number of stages the resolution of the
DAC is increased. Each stage has to be designed so that the accuracy of the accumulator
meets the N -bit resolution.
bN bN-1 b1
1 1 1
1/2 1/2 A0 A(t)
Tu Tu Tu
Aos
Figure 3.16 Pipelined algorithmic DAC.
3.6 Common DAC Circuit Implementations

Since we are focusing on DACs for communication applications, we focus on candidates suit-
able for high-speed and high-resolution. Basically, we imply three modes of circuit technol-
ogy; voltage-mode, current-mode, and charge-redistribution mode, although charge-
redistribution can be considered as voltage-mode as well. We will however associate voltage-
mode with a DAC where the element values (and the signal carrier) are given by voltage levels
as for example in a resistor-string that divides a voltage reference into a number different volt-
age levels. With current-mode we let the DAC elements (and the signal carrier) be given by
currents, as for example switched current sources or resistors dividing a major current into
weighted subcurrents. Finally, with charge-redistribution we associate elements that are given
by capacitor values, and the operation of the DAC is given by a switched-capacitor technique
(SC). Since the focus is set on high-speed applications, the current-mode DACs gets much
attention throughout the thesis.
To illustrate the functionality most of the converters in this section are presented as single-
ended. In reality differential output signals are used to improve the SNDR. Further, we con-
sider positive output signals, i.e., binary-offset coded inputs. In order to represent negative
inputs, the converter architectures can be relatively easily modified.
In Chapter 5 we take a closer look at the design and implementation of Nyquist-rate CMOS
DACs and in Chapter 6 the oversampling DACs. In Chapter 7 we consider some special DAC
structures for high performance.
Common DAC Circuit Implementations 73
3.6.1 Current-Steering DAC

A switched-current (SI) approach [36, 37] is a natural choice in CMOS, since the reference
and sum elements as well as switches are relatively simple to implement. The reference ele-
ments are current sources, the sum elements only wire connections, and the switches are MOS
transistors or transmission gates. A generalized binary-weighted current-steering DAC is
shown in Fig. 3.17.
2N-1ILSB 2N-2ILSB ILSB
R
bN bN-1 b1
Iout(t)
A(t)
Figure 3.17 An N-bit binary-weighted current-steering DAC with output buffer.
The switches are controlled by the input bits, b m , where m = 1, 2, …, N , and N is the num-
ber of bits. The output buffer increases the driving capability and can also be designed for
image rejection. b 1 is the LSB and the corresponding current source has the DC value I LSB .
The source controlled by bit b m , i.e., the m -th LSB current source, is preferrably formed by
connecting 2 m – 1 LSB current sources (unit current sources) in parallel, hence the MSB cur-
rent source has the DC value I MSB = 2 N – 1 ⋅ I LSB . The use of unit element sources allows
layout techniques to improve the matching of the sources and hence improved performance.
The output current, I out , indicateed in Fig. 3.17 is given by
I out ( X ) = 2 N – 1 I LSB ⋅ b N + … + 2I LSB ⋅ b 2 + I LSB ⋅ b 1 = I LSB ⋅ X , (3.38)
where X is the digital input given by

N
X = 2 N – 1 ⋅ b N + 2 ⋅ b2 + … + b1 = ∑ 2 m – 1 ⋅ bm . (3.39)
m=0
The current-steering DAC has the advantages of being small for resolutions below ten bits and
it can be very fast. As we will see in Chapter 4 the major disadvantages are its sensitivity to
device mismatch and limited current source output impedance. Another advantage is that it
has a very high power efficiency since almost all power is directed to the output. The current-
steering is suitable for high-speed wideband applications when special care is taken to
improve the matching and output impedance of the converter.
To guarantee monotonicity and reduce the influence of glitches, as well as reducing the sensi-
tivity to matching errors, the DAC could (should) be segmented into a coarse and a fine part.
The coarse part (MSBs) is thermometer coded and the fine part (LSBs) is kept binary
weighted.
The current sources are typically implemented with cascoded NMOS or PMOS transistors.
The designs of several CMOS current-steering DACs are discussed in Chapter 5.
3.6.2 Charge-Redistribution DAC

The charge-redistribution DAC is a switched-capacitor (SC) DAC, where the charge stored on
a number of scaled capacitors is used to perform the conversion [30]. See Fig. 3.18 for an
example of an N -bit converter [7]. The MSB capacitor, C N , is 2 N – 1 times larger than the
LSB capacitor, C 1 .
C0
2N-1CLSB 2N-2CLSB CLSB

A(t)
bN bN-1 b1
VREF
Figure 3.18 Example of an N-bit charge-redistribution DAC without reset phase.
In the figure we only display the circuit in one of the clock phases to illustrate the operation of
the DAC. In reality, we have to use two nonoverlapping clock phases, φ 1 and φ 2 .
It is clear that the limitations of the converter is given by a number of factors: the matching of
the capacitors, the switch on-resistance, and the finite bandwidth of the amplifier limit the per-
formance of the overall DAC. Noise is basically given by the kT ⁄ C noise and the influence
of the 1 ⁄ f noise and CFT can be decreased using correlated switching The opamp limita-
tions mostly let the charge-redistribution DAC to be used in high-resolution appliciations in
intermediate bandwidths.
3.6.3 R-2R Ladder DAC

The R-2R ladder architecture provides an architecture suitable for processes capable of imple-
menting highly linear resistors [38, 39]. The R-2R ladder architecture is shown in Fig. 3.19.
The current sources are all equally large, I 0 , and the switches are controlled by the digital
input, X = ( x N – 1, …, x 0 ) , where N is the number of bits and x N – 1 is the MSB. Since we
have slices consisting of a current source, a switch, a 2R resistor, and an R resistor, we can
make a modular layout and match the components well. Since the current sources are all
equally large, we can apply special current source trimming techniques.
Looking from the output (from the left to the right in the figure) the input impedance is always
2R . At the leftmost slice the impedance is given by two resistors in series and the input
impedance is 2R . At the next section the same applies since we have a 2R resistance in par-
allel with the two series R resistances. The current sources are assumed to have infinite output
impedance. Finally, the output impedance of the total DAC is 2R .
The resistors are, however, often nonlinear and contains signal-dependent capacitances, which
Common DAC Circuit Implementations 75
I0 I0 I0
Iout(t)
R
bN bN-1 b1
R R
2R 2R 2R A(t)
Figure 3.19 An N-bit R-2R ladder DAC.
yield distortion [7]. The time-delay between the switches of the MSB and LSB generates
glitches also for this architecture. In the R-2R ladder architecture shown in Fig. 3.19, there is
the same amount of current through all switches, which makes the design of the switches sim-
pler, however, the internal voltage nodes are varying with time and therefore the current
sources will have varying terminal voltages, hence resulting in nonlinearity and distortion.
3.6.4 Resistor-String DAC

The resistor string DAC as illustrated in Fig. 3.20 is a voltage-mode direct-encoded DAC
architecture, as presented in Sec. 3.5.3. Variations on the architecture are for example found in
[40, 41]. In the typical DAC shown in the figure, we use M switches, one for each code, and
hence the input code, { d m } , is a “walking-one” code and therefore M = 2 N – 1 . The
weighting elements are given by resistors. The reference voltage V ref is feeding the resistor
string and from voltage division, we have that the voltage level V m is given by
m⋅R m
V m = ------------ ⋅ V ref = --------------
N
- ⋅ V ref . (3.40)
R tot 2 –1
The switches, implemented with for example NMOS transistors or transmission gates, direct
the voltage to the buffer, giving the output current. It is seen that the number of elements
becomes large when the number of bits increases. The design of the operational amplifier may
become difficult for wideband applications. The matching of the resistors in the resistor string
is crucial for the overall accuracy. The RC-timing through the switches and the capacitive load
at the input of the OP limit the bandwidth.
The size of the encoding circuits can be reduced by using a tree selection architecture [7]. The
disadvantage of such an architecture is the additional delay through the increased number of
switches and switch layers.
3.6.5 Switched-Current Algorithmic DAC

Algorithmic DAC architectures have been successfully implemented in the SC and SI tech-
niques [42, 43, 44, 45]. Both techniques can be used in a standard digital CMOS process.
With the switched-current (SI) technique though, there is no need for linear resistors or capac-
itors. It should also be noted that for high-accuracy capacitors a special process may be
VREF R R R
R
bN bN-1 b1
R
2R A(t)
Figure 3.20 An N-bit resistor string DAC where M=2N-1.
rewuired. As was realized previously, the algorithmic DAC is not suitable for high-speed,
since an accumulation of the N -bit word is needed.
A signal-flow graph of the algorithmic DAC was shown in Fig. 3.15 and in Fig. 3.21 we show
a transistor implementation of an SI algorithmic DAC 44. This converter utilizes a feedback
factor of 1/2 instead of a factor 2 as was used in Fig. 3.15 and hence the digital input is fed
with the LSB first. The converter needs three equal subcircuits that are interconnected. Tran-
sistor M2 is biased with I 0 ⁄ 2 and therefore its size aspect ratio should be half the size of M1
and M3.
IREF I0 I0/2 I0
bi(f1) f3
f4
f2
Iout(t) f1 f2
M1 M2 M3
Figure 3.21 A switched-current (SI) implementation of an algorithmic DAC.
The operation of the circuit is controlled by four different switching signals, φ 1 to φ 4 , which
are slightly overlapping. On phase φ 1 the current input bit b i is determining if the current
I bit should be added to the accumulator. The I bit current is equal to the maximum current for
all bits i . This current is added to the intermediate accumulator output current from memory
cell M3. The sum is stored in the memory cell M1. This sum is then divided by two in the M2
transistor during phase φ 2 . Finally, on phase φ 4 the stored accumulated current in M3 is
switched to the output of the DAC. The switching phase φ 3 is used to restore the accumulator
and hence it should be opened when the first bit of a new word should be fed to the DAC.
To reach a high resolution of the converter the bias currents will become large and the transis-
tors (M1 through M3) and switches have to be designed carefully.
DAC Comparison 77
3.7 DAC Comparison

In this section we conclude the properties of the DAC architectures discussed througout the
chapter. We compile in tables and figures the properties of different DAC types and architec-
tures as well as reported performance in literature.
In Fig. 3.22 we compile the measured and reported performance from literature as well as
information from commercial manufacturers. As we underlined in Chapter 2 there are several
different means of performance and resolution. Although the true performance of the con-
verter is not determined by only few measured SFDR or SNDR, we have chosen to present the
performance by using the SFDR and sample frequency in (a) and the SFDR and signal fre-
quency in (b). For example, with reported performance of 70 dB SFDR at 125 MHz (signal
frequency), the measured and reported SFDR is considered to be 70 dB or more up to the
specified frequency for the specific update frequency. Also notice that we have chosen to use a
logarithmic scale for the signal frequency in Fig. 3.22 (b).
For some of the reported Nyquist-rate converters, the useable signal bandwidth is not equal to
half the update frequency, hence interpolation DACs, and naturally, this is also the case for the
OSDACs. A better view would be to consider SFDR/SNDR for both signal and update fre-
quencies, hence each point in Fig. 3.22 should be determiend by the three values. However, a
three-dimensional plot is not easily interpreted. Therefore, in Table 3.3. we also give a list of
the DACs used in the summary together with a description of the DAC architecture, circuit
technique, etc.
To conclude the reported performance shown in Fig. 3.22 and Table 3.3 we have also consid-
ered a best-fit line to the sampled data. This line is given by a slope of -16 dB/decade. This
figure was briefly mentioned in the previous chapter and we will also touch upon this in the
next two chapters as well.
From the figures and table we find different design limitations for different architectures in
terms of speed, resolution, dominating limitations, complexity, and chip area. The table can be
used as a quick reference guide for proper choice of converter architecture for the designer’s
specific application.
Reported SFDR and SNDR vs. update frequency

90
21
85 7
80 11 24
22 13 18
75 1 19
23 25
SNDR / SFDR [dB]

70
65 4
10 16 14
60 15
2
55 3 20
8 17 5
50
6 12
45
40
9
35 1 2
10 10
Frequency [MHz]
(a)
Reported SFDR and SNDR vs. signal frequency
90 21
85 7
80 11 24
22 13
18
75 19 1
23 25
SNDR / SFDR [dB]
70
10 4
65 14
16 15
60 2
20 3
55 8 5 17
50 6
12
45
40 9
35 −1 0 1
10 10 10
Frequency [MHz]
(b)
Figure 3.22 Reported measured performance of different DAC types. In (a) the performance vs. the
update frequency and in (b) vs. the signal frequency (bandwidth).
DAC Comparison 79
SFDR, SNDR
Update freq.
Signal freq.
Reference
Number
voltage
Supply
of bits
[MSps]
[MHz]
[dB]
No Architecture Process
Current-steering.
1 [46] 14 5 CMOS 5.01 32 77
Interpolation ratio of 4.
2 [47] Current-steering. Segmented. 10 3.3 CMOS 0.3 10 60
Current-steering.
3 [48] 10 5 CMOS 4.43 40 57
Binary weighted.
4 [49] Current-steering. Segmented. 10 3.3 CMOS 20 250 68
Hybrid current-steering.
5 [50] 10 5 CMOS 3.9 125 56
Thermometer coded.
Current-steering.
6 [51] 10 5 BiCMOS 10 100 50
Thermometer coded.
Hybrid current-steering
5/
7 [38] and R-2R ladder. 14 BiCMOS 2.03 10 87
-5.2
Thermometer coded MSBs
9 [53] Current-steering. Segmented. 8 5 CMOS 13.5 105 41
Hybrid current-steering
11 [55] and R-2R ladder. 16 5 BiCMOS 1.23 10 82
Thermometer coded MSBs
Oversampling.
12 [56] 8 3.3 CMOS 5 216 49
Noise shaping.
Current-steering.
15 [59] 12 3.3 CMOS 10 300 62
Multi-segmented.
16 [60] Current-steering. Segmented. 14 2.7 CMOS 3 150 64.5
Hybrid.
17 [39] 12 -5.2 Bipolar 10 72 55
Segmented R-2R ladder.
Oversampling.
18 [61] 14 2.5 CMOS 1 120 80
Noise shaping.
Table 3.3. Reported performance of mainly telecommunication DACs.
SFDR, SNDR
Update freq.
Signal freq.
Reference
Number
voltage
Supply
of bits
[MSps]
[MHz]
[dB]
No Architecture Process
Current-steering. Hybrid
20 [63] 10 5 CMOS 0.5 75 58
with array and binary.
Current-steering with buffer.
21 [64] X 3.4 CMOS 0.02 4.2 90
Oversampling. Calibration.
Current-steering. Trimming.
22 [65] 14 ±5 BiCMOS 1.23 10 80
Special switching.
Switched-capacitor
23 [66] 15 5 CMOS 0.044 5.6 74
algorithmic DAC.
24 Current-steering with 2.5 30 82
[67] 14 5 CMOS
25 buffer. Return to zero. 44 5.6 74
Table 3.3. Reported performance of mainly telecommunication DACs.
4 Behavioral-Level Models
for Current-Steering,
Nyquist-Rate D/A Converters
4.1 Introduction
In this chapter we present proposed models and methodology to predict the performance of
unbuffered current-steering DACs. We show how the distortion and noise relate to parameters,
such as the output impedance, matching error, and circuit noise. The work results in a number
of compact formulas that can be used to relatively quick estimate the performance of a manu-
factured chip. The proposed formulas also give us a design guide for finding proper parame-
ters during the design phase.
The design of high-accuracy integrated circuits highly depends on the models used for transis-
tors and other comonents. Characterization of semi-conductors is a complex and time-con-
suming work. For small-dimension transistors complex short-channel effects are influencing
the results more and more. The models must be able to handle three-dimensional properties of
the layout. For the transistors, for example, the BSIM level 3 models are now well-estab-
lished, but the work to refine and improve the model is continuous.
In general, in terms of abstraction, there are several levels of modeling of the circuits. We
have for example in descending order from high level of abstraction:
• behavioral level: simulation with AHDL, Matlab, C, etc.
• circuit or transistor level: simulation with Spice, Spectre, etc.
• layout level: simulation with Spice or Spectre of the extracted layout
view, including parasitic components from nonideal interconnection wires
The lower level of abstraction, the more parameters we include in the models. Due to the high
complexity of a D/A converter or in general, a mixed-signal circuit, it is important not only to
81
82 Behavioral-Level Models for Current-Steering, Nyquist-Rate D/A Converters
have good, accurate models. For the designer, they should also be understandable, i.e., we
want to relatively easy be able to extract fundamental design parameters from the model and
understand how these limit the performance. For this purpose, the circuit and layout levels are
much to detailed. We want to be able to work with models where we can add sufficient infor-
mation to be able to extract for example the influence of noise, nonlinearity, and other circuit
imperfections. It is important to know in advance how the converter will react on circuit non-
idealities, to be able to avoid these errors during the design and layout phases. We must also
know if the errors will give rise to additional noise or cause a nonlinear transfer function, e.g.,
distortion? The models also help us to identify bottle-necks and how to find possible improve-
ment techniques. Using for example Matlab or C we also have a flexible tools where genera-
tion of new architectures, stimuli, etc., becomes fairly easy. The models are continuously
verified and refined using the results from measurements and simulations.
We present an overview of some different models of Nyquist-rate DACs. Especially, we dis-
cuss how specific circuit errors such as for example device matching errors, finite output
impedance, settling errors, etc., affect the performance of the converter. As was mentioned in
Chapter 2, most of the characterization of the performance of converters is done in the fre-
quency domain. Therefore, these models also result in frequency-domain measures, such as
the SNDR, SNR, and SFDR. However, the impact of typical DAC errors on DNL and INL is
also briefly discussed in the chapter. Previously reported models of DAC errors have more
been focused on INL and DNL requirements, and only few of them have thoroughly discussed
the impact of DAC errors on the frequency-domain and dynamic parameters.
The models can, as well as the performance characterization, be divided into static and
dynamic error models. Roughly, the static models describe the settled output values, (which
often are too optimistic and do not determine the true performance), and the dynamic are
given by the signal-dependent transition between two states, hence the slewing, glitches, time
skew, etc. In communications and wideband applications it is mostly the dynamic perfor-
mance that determines the overall quality of the converter. But generally, the static properties
set the best-case performance and, naturally, to achieve a good dynamic performance we must
also guarantee a good static performance.
Since the current-steering DAC structure, as presented in Sec. 3.6.1 and repictured in Fig. 4.1,
is a suitable candidate for high-speed applications, the models proposed in this chapter
describe the operation of this type of DAC. However, some of the models can be generalized
to cover other architectures as well. Process variations and other parasitics will influence the
matching between current sources and will introduce noise and distortion. The output imped-
ance is depedendent on the number of current sources connected to the output and is therefore
it becomes signal-dependent. In Fig. 4.1 we show a typical current-steering DAC.
Briefly, we repeat the operation of the current-steering DAC as illustrated in by the N -bit off-
set binary-weighted DAC in Fig. 4.1. The output current is given by
I out ( X ) = 2 N – 1 I LSB ⋅ b N + … + 2I LSB ⋅ b 2 + I LSB ⋅ b 1 = I LSB ⋅ X , (4.1)
where X is the digital input given by

N
X = 2N – 1 ⋅ b N + 2 ⋅ b2 + … + b1 = ∑ 2 m – 1 ⋅ bm (4.2)
m=0
Introduction 83
bN bN-1 b1
Iout(t)
RL
Figure 4.1 An N-bit binary weighted current-steering DAC. The output is terminated over a 50-Ω
load.
and b m are the bits controlling the switches. We assume that all current sources are con-
structed by using unit current sources. Since the DAC is binary weighted, we have that the m -
th bit is represented by a current source of 2 m – 1 unit current source and its nominal output
current is I m = 2 m – 1 ⋅ I LSB .
Although the list is not complete, we highlight some important error sources that limit the per-
formance of the current-steering DAC (or in mixed-signal circuits in general) [7, 9, 13]:
• Finite output resistance. The influence of a finite output impedance of the DAC, or in gen-
eral; a finite output over termination impedance ratio strongly affects the linearity of the
converter. This is primarily since the output impedance of an unbuffered converter is sig-
nal-dependent.
• Matching errors. Since variations in the process force the oxide thickness, threshold volt-
age, transistor widths, etc., to vary over the chip area, the weighted sources become
unmatched, which affects the linearity. The matching errors are of both of random and lin-
ear nature.
• Circuit noise. Another limit on achievable resolution is given by circuit noise, e.g., thermal
noise, flicker noise, etc. We have to guarantee that this noise is lower the quantization
noise.
• Settling errors. The conversion value is found at the sampling (update) instant. A limited
settling time will therefore cause a settling error which can be signal dependent and hence
introduce distortion. The settling errors arise due to the parasitic capacitances within the
current sources, in interconnection wires, current switches, and at the output of the con-
verter.
• Glitches. Due to the nonideal switches and different capacitive load on different bits,
matching errors, there will be a time skew between the bits. This introduces current or volt-
age steps, referred to as a glitches.
• Clock feedthrough (CFT). Due to the capacitive coupling in the current switches between
the switching signals and the current output, currents or charge will be induced in the out-
put nodes.
The dynamic errors are of more high-frequency behavior, but in a 14-bit DAC the dynamic
errors may be detectable at rather low frequencies within the Nyquist frequency range. In the
following we will discuss each one of these error sources and how they influence typical per-
formance measures.
In Sec. 4.2 we discuss the concept of using the unit-element approach for constructing
weights in a DAC and how this apply to e.g. matching errors. In Sec. 4.3 we show how a finite
output resistance influences the performance and in Sec. 4.5 we discuss matching errors. The
circuit noise, discussed in Sec. 4.4, and especially thermal noise, is limiting the resolution. In
Sec. 4.6 we also discuss and model the influence of errors in the time-domain as well as
dynamic properties such as nonlinear slewing, bit skew, and glitches.
In Chapter 5 we present the design of a current-steering wideband CMOS DAC for telecom-
munication applications. The models presented in this chapter can be applied to this design,
and therefore, we show in Sec. 5.5 chip measurements to illustrate the correlation between
calculated, simulated, and measured results of the DACs.
4.2 Unit-Element Approach

When good element matching is required to reach high performance, which basically always
is the case in analog design, a layout strategy with unit elements is often used [7, 8, 13]. With
unit elements, we understand that we try to create larger weights by combining a number of
equally large elements. For example, if we want to implement two capacitors with the capaci-
tance values of 6 and 9 pF (Fig. 4.2 (a)), we could use five 3-pF capacitors and interconnect
them so that we get the desired capacitances (b). With this approach we can also lay them out
so that graded mismatch errors are spread out. In the example in Fig. 4.2 (c) we have not con-
sidered these matching aspects. Instead the two capacitors have been laid out without using
unit elements. In (d), however, we show a typical interdigitized layout of unit elements.
C1 = 6 pF C2 = 9 pF 3 pF 3 pF 3 pF 3 pF 3 pF
(a) (b)
C1 C2
C2 C1 C2 C1 C2
(c) (d)
Figure 4.2 (a) Symbols for two capacitors. (b) Unit element capacitors. (c) Individual layout. (d) Even
distribution of unit element capacitors.
Unit-Element Approach 85
Graded matching errors are typically, e.g., temperature deviation, variation of the oxide thick-
ness, threshold voltage variations [8, 68, 69, 71, 70]. Typically, in a small, local area, these
deviations can be modelled as linear planes or perhaps second order functions [53, 69, 72] .
Consider the example in Fig. 4.3 where we have illustrated that for the whole wafer or larger
chips the oxide thickness may vary significantly, but for each chip (if they are small enough)
the deviation can be approximated by a plane. For example, we could let the the oxide thick-
ness, t , be given by the equation
t ox = t̃ ox + ∆t x ⋅ x + ∆t y ⋅ y , (4.3)
where t̃ ox is the desired oxide thickness at x = y = 0 , ∆t x, ∆t y are the gradients in the x, y -

directions. The same considerations also hold for current sources that can be divided into a
number of unit current sources and then interconnect in parallel.
The size of the unit element is given by a common divider, but mostly we cannot choose the
minimum size component, since then the interconnection wires will become too long and
complex, hence introducing parasitic components that are too large. Hence there is an opti-
mum unit size to be identified. This size can also be determined by using statistical methods.
More on this is discussed in Sec. 5.2.1. As mentioned previously, there are several other
sources to matching errors that will further influence the stochastic and graded errors.
Figure 4.3 Variation of oxide thickness over the wafer and the individual chips. The thickness may
vary significantly over the wafer, but may be approximated by a plane for small dimen-
sions.
4.2.1 Matching Errors of Unit Current Sources

In Fig. 4.4 we show the typical transistor-level implementation of a unit current source using
cascoded PMOS transistors. The size aspect ratio of the source transistor M1 is W ⁄ L . The
gate voltages are generated with a bias network. Assuming that the cascode transistor has a
high gain, the current through the source is approximately [7, 8]
βu
I u = ----- ⋅ ( V SG – V T ) 2 , (4.4)
2
where β u is the transconductance parameter, V SG is the source-gate voltage on transistor M1,
and V T is the threshold voltage.
Further on, we know that [7, 8]
VG1
M1
VG2
M2
Iout
Figure 4.4 PMOS implementation of a unit current source.
βu µ 0 C ox W
----- = --------------- ⋅ ----- , (4.5)
2 2 L
where µ 0 is the mobility and C ox = ε ox ⁄ t ox is the capacitance per unit gate area. Differenti-
ating (4.4) gives the absolute error current
∂I u ∂I u ∂I u
∆I u = ∆β u ⋅ -------- + ∆V eff ⋅ ------------- + ∆V T ⋅ ---------- = …
∂β u ∂V SG ∂V T
Iu 2I u
… = ∆β u ⋅ ----- + ( ∆V SG – ∆V T ) ⋅ ----------------------- (4.6)
βu V SG – V T
Combining the result in (4.6) with the current in (4.4) gives us the relative error
∆I ∆β ∆V SG – ∆V T
--------u = ---------u + 2 ⋅ ------------------------------- . (4.7)
Iu βu V SG – V T
Investigations show that [68] the variance of the stochastic relative matching errors can be
characterized by the area of the objects to the matching. For example
∆I A A VT 4 A VT 
σ 2(--------u) ≈ -------β- + -----------------------------2- ⋅ ---------- = -------- ⋅  A β + -----------------------------
4 1 1
- = -------- ⋅ α r , (4.8)
Iu WL ( V SG – V T ) WL WL  ( V SG – V T ) 2  WL
where A β and A VT are technology-dependent constants. The variance of the error is
Aβ 4 A VT Aβ A VT
σ 2(∆I u) ≈ -------- ⋅ I u2 + -----------------------------2- ⋅ ---------- ⋅ I u2 = -------- ⋅ I u2 + ---------- ⋅ β u2 = …
WL ( V SG – V T ) WL WL WL
β u2  A β  β u2
… = -------- ⋅ ------ ⋅ ( V SG – V T ) + A VT = -------- ⋅ α a .
2 (4.9)
WL  4  WL
Now, assume that we want to construct a current source that is M times stronger than the unit
current source. Hence, the transconductance parameter becomes M times larger,
β M = M ⋅ β u . Thereby, the relative matching error, according to (4.8), becomes M times
smaller
Limited Output Impedance 87
1 σ 2(∆I u ⁄ I u)
σ 2(∆I M ⁄ I M) ≈ ----------------------- ⋅ α r = --------------------------- (4.10)
( WL ) ⋅ M M
and the absolute error according to (4.9) becomes M times larger
βM 2 M ⋅ β u2
σ 2(∆I - ⋅ α = --------------- ⋅ α r = M ⋅ σ 2(∆I u) .
M ) ≈ ---------------------- (4.11)
( WL ) ⋅ M a ( WL )
If we would use unit elements instead, we should use M unit current sources. Assuming that
the stochastic matching errors, ∆I u, m , are individually independent, we may find the variance
M 2 M
  
E   ∑ ∆I u, m  = ∑
2
E { ∆I u, m } = M ⋅ σ 2(∆I u) . (4.12)
m = 1   m=1
Comparing the result in (4.12) with the one in (4.11) we see that considering stochastic
matching errors, we actually do not gain in matching by using the unit element approach.
There are however, advantages in terms of the possibilities to use special layout techniques
such as interdigitized or common-centroid. Thereby we can minimize the influence of the
graded matching errors. Secondly, we are also able to achieve a better edge matching using
unit elements and the distance between transistors that should be matched becomes shorter as
well. We can include this distance in the formulas above [68] and we get for example
β u2
σ 2(∆I u) = -------- ⋅ α a + β u2 ⋅ α d ⋅ D 2 , (4.13)
WL
where α d is a process- and bias-dependent constant and D is the distance between the tran-
sistors (or objects) to match. We see that with a larger distance between the transistors the
mismatch increases. Therefore, we should obviously try to keep this distance as small as pos-
sible. If we lay the transistors out as dense as possible, the distance D will also in some sense
determined by the transistor sizes. The larger transistors the larger distance, i.e.,
D ∼ a ⋅ W + b ⋅ L.
4.3 Limited Output Impedance

First, we consider a dual-output (differential) current-steering DAC. In Fig. 4.5 we show a
typical implementation, where the current sources typically are implemented by cascoded
transistors as in Fig. 4.4. The cascodes are used to increase the output impedance. The
switches are implemented with MOS transistors or transmission gates. The output currents,
+ and I – , are terminated by 50-Ω loads ( G ) . In some applications, the output currents
I out out L
are fed to an output buffer which provides the DAC with a virtual ground and hence a low-
impedance load. This significantly improves the linearity with respect to the limited output
impedance. However, the buffer itself may limit the performance instead.
The switch signals are slightly overlapping to guarantee that the current sources never are
completely turned off which would have given glitches and a slower startup phase as the cur-
rent sources are opened again. The transistors are dependent on the voltage applied across
them, i.e., the drain-source voltage, hence they will have a finite output impedance. Consider
the linearized model of the DAC shown in Fig. 4.6. We have the limited output conductance
of the current source as well as parasitic capacitance. The switch and interconnect wires have
bN bN bN-1 bN-1 b1 b1
Iout(t) Iout(t)
RL RL
Figure 4.5 Generalized view of a differential-mode current-steering DAC.
parasitic resistance and capacitance. The output also has a large capacitive load. Typically, the
output conductance of a unit current source is given by
G S ≈ g ds ⋅ A , (4.14)
where g ds is the output conductance of M1 and A is the gain of the cascode (compare with
Fig. 4.4). Typically, the output conductance is linearly dependent on the LSB DC current,
I LSB , [7, 8]
g ds ∼ I LSB . (4.15)
Further we have the output capacitance of the unit current source approximately given by
C S ≈ C gd + C bd , (4.16)
where C gd is the gate-drain capacitance (overlap capacitance) on the cascode transistor and
C bd is the bulk-drain capacitance on the cascode.
The switch on-conductance of an NMOS switch is given by [7, 8]
G on ≈ β ⋅ ( V φ – V T – V out ) , (4.17)
where β is the transconductance parameter, V φ is the switch on-voltage (typically equal to

the positive voltage supply), V T is the threshold voltage, and V out is the output voltage. It
should be noted that in some designs the switches are used in the saturation region and then
they also work as cascodes on the current source further increases the output resistance [7, 8].
This is further discussed in Chapter 5.
Since we are connecting a number of unit current sources in parallel to create a larger current
source, the output conductance of this larger current source will be different than the unit cur-
rent source. The output conductance will increase, hence the output resistance will decrease.
Studying (4.1) gives the intuitive conclusion that the total output conductance of the DAC is
linearly dependent on the signal, i.e.,
Iout Cout
Gout Iout Cout
Gout
Csw
Gon
Iload
CL
RL
CL
RL
(a) (b)
Figure 4.6 Linearized model of the unit current source (a) with and (b) without parasitics from
switches and interconnection wires.
G out(X ) = X ⋅ G S (4.18)
and the same holds for the capacitance

C out(X ) = X ⋅ C S . (4.19)
Now, assume that the input signal is changed and some current sources are switched to the
negative output instead of the positive and vice versa. In Fig. 4.7 (a) and (b) we illustrate this
situation with Laplace operators. In (a) we find the situation just before the switching instant.
In (b) we find the situation after some of the current sources have changed node to which they
are connected. To simplify the notation and the derivation, we have at this first stage neglected
the influence of the switches. We will get back to this matter. The currents through the load
resistor is assumed to be the actual, measured output current. The ideal output current is given
by the expression in (4.1).
We understand from the figures that there will be a loss of current through the output resis-
tance of the current source, and the parasitic capacitances will influence the settling time of
the system and cause signal-dependent settling errors. Assume that additional sources are con-
nected to the positive output between the update interval nT and ( n + 1 )T as illustrated in
Fig. 4.7 (b). Hence the input code is changing with
∆X = ∆X n = X n + 1 – X n (4.20)
and the change in current will be in the order of

∆I out = ∆X ⋅ I u = ∆X ⋅ I LSB . (4.21)
With the differential outputs, we have for the negative output the code X max – X n applied
instead. The settling behavior within this time period can be found by considering the sche-
matics in Fig. 4.7 and the two output currents become
(Xmax-X-DX).Iu (Xmax-X-DX).GS
X.Iu X.CS DX.Iu DX.CS
(Xmax-X-DX).CS
X.G S DX.G S
Iout Iout
CL CL
RL RL
(a)
(Xmax-X-DX).Iu (Xmax-X-DX).GS
X.Iu X.GS X.CS DX.Iu DX.GS DX.CS (Xmax-X-DX).CS
+0 -0 -0
Vout Vout Vout
s s s
Iout Iout
+0 -0
Vout Vout
s s
RL CL RL CL
(b)
Figure 4.7 Change of input signal causes additional sources to be connected to the output. We find the
situation before (a) and after (b) the switching instant.
+0 –0
+ I LSB ⋅ X n + 1 V out V out
I out(s) - + ---------- ⋅ s ( C L + C S ⋅ X n ) + ---------- ⋅ sC S ⋅ ∆X n ⋅
= ---------------------------
s s s
GL
⋅ ------------------------------------------------------------------------------------------ (4.22)
GL + GS ⋅ X n + 1 + s ( C L + X n + 1 ⋅ C S )
and
–0
– I LSB ⋅ ( X max – X n + 1 ) V out
I out(s) - + ---------- ⋅ s ( C L + C S ⋅ ( X max – X n + 1 ) ) ⋅
= ---------------------------------------------------
s s
GL
⋅ ----------------------------------------------------------------------------------------------------------------------------------------- , (4.23)
G L + G S ⋅ ( X max – X n + 1 ) + s ( C L + ( X max – X n + 1 ) ⋅ C S )
+0 and V –0 are the output voltage levels just before the switching instant, hence the
where V out out
initial values for the next settling period. We do not consider the contribution from the posi-
tive supply, since this will only give rise to a linear gain error [73]. Further, we have that
V out ⋅ G L = I out . (4.22) and (4.23) become
+ I LSB ⋅ X n + 1 + CL + CS ⋅ X n – CS
- + I out ⋅ ------------------------------- + I out ⋅ ------- ⋅ ∆X n ⋅
I out(s) = ---------------------------
s GL GL
1 CL + CS ⋅ X n + 1
⋅ --------------------------------------------- ⁄ 1 + s -------------------------------------- (4.24)
1 + GS ⁄ GL ⋅ X n + 1 GL + GS ⋅ X n + 1
and
– I LSB ( X max – X n + 1 ) – C L + C S ( X max – X n + 1 )

I out(s) = ----------------------------------------------- + I out ⋅ --------------------------------------------------------- ⋅
s GL
1 C L + C S ⋅ ( X max – X n + 1 )
⋅ -------------------------------------------------------------------- ⁄ 1 + s ------------------------------------------------------------- (4.25)
1 + G S ⁄ G L ⋅ ( X max – X n + 1 ) G L + G S ⋅ ( X max – X n + 1 )
+ +0 – –0
where I out = V out ⋅ G L and I out = V out ⋅ G L denote the output current values just before the
switching instant. In (4.24) and (4.25) we identify the load and unit current source time con-
stants
τ L = C L ⁄ G L and τ S = C S ⁄ G S . (4.26)
Notice that the settling time constant of the current sources is independent on the code applied
on the DAC. We have
X⋅C C
τ S(X ) = --------------S- = ------S = τ S . (4.27)
X ⋅ GS GS
The conductance and capacitance ratios are given by
ρ G = G S ⁄ G L and ρ C = C S ⁄ C L . (4.28)
We define the signal-dependent system time constant as
1 + ρC ⋅ X
τ σ(X ) = τ L ⋅ ------------------------ . (4.29)
1 + ρG ⋅ X
The output currents from (4.24) and (4.25) can now be written
+ I LSB ⋅ X n + 1 + –
- + I out ⋅ τ L ⋅ ( 1 + ρ C ⋅ X n ) + I out ⋅ τ L ⋅ ρ C ⋅ ∆X n ⋅
I out(s) = ---------------------------
s
1
⋅ ---------------------------------- ⁄ [ 1 + s ⋅ τ σ(X n + 1) ] (4.30)
1 + ρG ⋅ X n + 1
and
– I LSB ⋅ ( X max – X n + 1 ) –
- + I out ⋅ τ L ⋅ ( 1 + ρ C ( X max – X n + 1 ) ) ⋅
I out(s) = ---------------------------------------------------
s
1
⋅ --------------------------------------------------------- ⁄ [ 1 + s ⋅ τ σ(X max – X n + 1) ] (4.31)
1 + ρ G ⋅ ( X max – X n + 1 )
We find expressions on the currents in the time domain for t ≥ nT and we use the notation
X n + 1 = X DC + X̃ n + 1 (4.32)
and
X max – X n + 1 = X DC – X̃ n + 1 , (4.33)
where X DC = X max ⁄ 2 (typically for an N -bit converter this is chosen to be X DC ≈ 2 N – 1 ).

To simplify the notation, we assume that t starts from 0. The inverse Laplace transforms of
(4.30) and (4.31), L –1 { I out
+ (s) } and L – 1 { I – (s) } , become
out
–t
I LSB ⋅ ( X DC + X̃ n + 1 ) -----------------------------------------
= -------------------------------------------------------- ⋅ 1 – e τσ(X DC + X̃ n + 1) +
+
I out(t)
1 + ρ G ⋅ ( X DC + X̃ n + 1 )
+ –
I out ⋅ τ L ⋅ ( 1 + ρ C ⋅ ( X DC + X̃ n ) ) + I out ⋅ τ L ⋅ ρ C ⋅ ∆X n
+ -------------------------------------------------------------------------------------------------------------------------------- ⋅
1 + ρ G ⋅ ( X DC + X̃ n )
–t
-----------------------------------------
1 τ
⋅ ---------------------------------------- ⋅ e σ(X DC + X̃ n + 1) (4.34)
τ σ(X DC + X̃ n + 1)
and
–t
– I LSB ⋅ ( X DC – X̃ n + 1 ) ----------------------------------------
τ
I out(t) = -------------------------------------------------------- ⋅ 1 – e σ(X DC – X̃ n + 1) +
1 + ρ G ⋅ ( X DC – X̃ n + 1 )
– –t
I out ⋅ τ L ⋅ ( 1 + ρ C ( X DC – X̃ n + 1 ) ) 1
----------------------------------------
τ
+ -------------------------------------------------------------------------------- ⋅ ---------------------------------------- ⋅ e σ(X DC – X̃ n + 1) . (4.35)
1 + ρ G ⋅ ( X DC – X̃ n + 1 ) τ σ(X DC – X̃ n + 1)
To further simplify the notation, we adjust some of the parameters to the signal’s DC level
ρ G ⋅ X DC ρ C ⋅ X DC I LSB ⋅ X DC
ρ' G = ------------------------------
- , ρ' C = ------------------------------
- , and I DC = ------------------------------
-. (4.36)
1 + ρ G ⋅ X DC 1 + ρ C ⋅ X DC 1 + ρ G ⋅ X DC
We will also sometimes refer to the input’s AC over DC ratio
X̃ n
x̃ n = ---------- . (4.37)
X DC
Further, we get
∆X̃ ∆X
∆x̃ n = ----------n = ----------n . (4.38)
X DC X DC
The system time constant from (4.29) can be written
1 + ρ C ⋅ X DC 1 + ρ' C ⋅ x̃
τ σ(X DC + X̃ ) = τ L ⋅ ------------------------------- ⋅ ------------------------ . (4.39)
1 + ρ G ⋅ X DC 1 + ρ' G ⋅ x̃
We introduce a time ratio

t
ρ T (t, X̃ ) = ------------------------------- . (4.40)
τ σ(X DC + X̃ )
The dual output currents from (4.34) and (4.35) can be written
+ 1 + x̃ n + 1 – ρ (t, X̃ ) + – ρ (t, X̃ )
I out(t) = I DC ⋅ ---------------------------------- ⋅ [ 1 – e T n + 1 ] + I out ⋅ e T n + 1 +
1 + ρ' G ⋅ x̃ n + 1
ρ' C ⋅ ∆x̃ n
+ I out ⋅ -------------------------- ⋅ e –ρT (t, X̃ n + 1)
–
(4.41)
1 + ρ' C ⋅ x̃ n
and
1 – x̃ n + 1
I out(t) = I DC ⋅ --------------------------------- ⋅ [ 1 – e –ρT (t, – X̃ n + 1) ] + I out ⋅ e –ρT (t, – X̃ n + 1) .
– –
(4.42)
1 – ρ' G ⋅ x̃ n + 1
At the end of each sample period we have t = T and the sampled output currents at multiples
of the sample time period are determined by difference equations
1 + x̃ n + 1
I out(n + 1) = I DC ⋅ ---------------------------------- ⋅ [ 1 – e –ρT (T , X̃ n + 1) ] + I out(n) ⋅ e –ρT (T , X̃ n + 1) +
+ +
1 + ρ' G ⋅ x̃ n + 1
ρ' C ⋅ ∆x̃ n
+ I out(n) ⋅ -------------------------- ⋅ e –ρT (T , X̃ n + 1)
–
(4.43)
1 + ρ' C ⋅ x̃ n
and
1 – x̃ n + 1
I out(n + 1) = I DC ⋅ --------------------------------- ⋅ [ 1 – e –ρT (T , – X̃ n + 1) ] + I out(n) ⋅ e –ρT (T , – X̃ n + 1) .
– –
(4.44)
1 – ρ' G ⋅ x̃ n + 1
Now, notice that we have found an expression where the conductance and capacitance ratios
are parameters that let us understand how the performance. If these ratios are zero there will
not be any distortion. Therefore, one should try to drive the outputs of the current-steering
DAC to a low-impedance node, i.e., virtual ground.
We see from the equations above that the output current is dependent on previous values, e.g.
a memory function due to the capacitances associated with the nodes. We also have that the
input difference ∆X n influences the settling as well, i.e. the larger differences, the larger set-
tling errors will occur. Therefore, the error will in some sense be determined by the signal’s
derivative and hence determined by the signal frequency. The system time constant is signal
dependent and therefore, the settling time will depend on the input code unless the conduc-
tance ratio is equal to the capacitance ratio, ρ C = ρ G . In that case, the settling is fully deter-
mined by the signal-independent load capacitance and load resistance. If the input code
change is zero, i.e., ∆X n = 0 , the currents are given by
1 + x̃ n + 1 – ρ (T , X̃ n + 1)
] + I out(n) ⋅ e –ρT (T , X̃ n + 1)
+ +
I out(n + 1) = I DC ⋅ ---------------------------------- ⋅ [ 1 – e T (4.45)
1 + ρ' G ⋅ x̃ n + 1
and
1 – x̃ n + 1
I out(n + 1) = I DC ⋅ --------------------------------- ⋅ [ 1 – e –ρT (T , – X̃ n + 1) ] + I out(n) ⋅ e –ρT (T , – X̃ n + 1) .
– –
(4.46)
1 – ρ' G ⋅ x̃ n + 1
We see that the settling continues over a number of update periods. In Fig. 4.8 (a) we show a
simulated step response for a 14-bit DAC where the input changes from the DC level,
X = X DC ≈ 2 N – 1 , to X = X DC ⋅ 1.5 ≈ ( 3 ⁄ 2 ) ⋅ 2 N – 1 . Hence the positive output channel
aims for ( 3 ⁄ 2 ) ⋅ X DC and the negative output aims for ( 1 ⁄ 2 ) ⋅ X DC . The conductance ratio
is ρ G = 5 ⋅ 10 –9 and the capacitance ratio is ρ C = 2.4 ⋅ 10 –7 . We assume that the output
currents did settle before the input signal was changed. In Fig. 4.8 (b) we show the corre-
sponding settling errors as function of time, ∆I +(t) and ∆I –(t) , where
3 + 1 –
∆I +(t) = I LSB ⋅ --- ⋅ X DC – I out(t) and ∆I –(t) = I LSB ⋅ --- ⋅ X DC – I out(t) . (4.47)
2 2
Notice that we in Fig. 4.8 display the output amplitude levels at discrete-time instants and that
the sample-and-hold amplitude in-between.
DAC positive output Output error current

5
15
4
14
Amplitude [mA]
Amplitude [mA]
13 3
12 2
11
1
10
0
9
430 440 450 460 470 480 430 440 450 460 470 480
Time [us] Time [us]
(a) (b)
Figure 4.8 Output (a) step response for the positive output with ideal step shown (dashed) and (b) cor-
responding error current.
The influence of the signal-dependent settling error will of course also influence the result
throughout the frequency domain. We have that for higher frequency, i.e., larger ∆X n , the
nonlinearity becomes larger and hence higher distortion. In Fig. 4.9 we show the simulated
differential output current spectra for (a) a low-frequency and (b) high-frequency signal. We
see that the distortion terms increase for higher signal frequencies, the SFDR is decreasing
from 86 to 81 dB. The SNDR is decreasing from 84 to 79 dB. (Since the distortion terms are
so dominating, the SNDR is practially determined by the SFDR). The conductance and capac-
itance ratios are approximately ρ G = 10 –9 and ρ C = 2.5 ⋅ 10 –7 . These are rather extreme
values to illustrate the effects. The update or sample frequency is 2.208 MHz. Notice that in
the simulation we have taken into account the effect of negative code changes, ∆X n . Further
on in the thesis we want to get a better understanding of how the distortion terms are increas-
ing with frequency and circuit parameters. Consider the simulated SFDR as function of signal
frequency in Fig. 4.10. We have used the same DAC configuration as above, i.e., the sampling
frequency is 2.208 MHz. In the figure we have included a dashed line expresses the best-fit
line to the simulated SFDR. The slope of this line is approximately 20 dB/decade.
DAC differential output DAC differential output

0 0
−36 −36
Power [dB]
Power [dB]
−72 −72
−118 −118
0 0.552 1.104 0 0.552 1.104

Frequency [MHz] Frequency [MHz]
(a) (b)
Figure 4.9 Output spectra for (a) lower and (b) higher signal frequencies.
Simulated SFDR with best−fit line
85
80
SFDR [dB]
75
70
239 304 387 494 629

Signal frequency [kHz]
Figure 4.10 Simulated SFDR as function of signal frequency.
4.3.1 Settling-Time Error with Ideal Current Sources

Assume that ρ C and ρ G are very small or even zero. Then we have τ σ ≈ τ L and the settling
(and bandwidth) of the system is given by the load capacitance and resistance. In that case
(4.42) and (4.43) become
I out(n + 1) = I LSB ⋅ ( X DC + X̃ n + 1 ) ⋅ [ 1 – e –T ⁄ τ L ] + I out(n) ⋅ e –T ⁄ τ L

+ +
(4.48)
and
I out(n + 1) = I LSB ⋅ ( X DC – X̃ n + 1 ) ⋅ [ 1 – e –T ⁄ τ L ] + I out(n) ⋅ e –T ⁄ τ L .

– –
(4.49)
The currents are dependent on the current at the previous sampling instant, which is the nor-
mal operation of a system with an impedance containing both resistive and capacitive ele-
ments. This dependency is determining the bandwidth of the system. If we apply a step at the
input the output will settle as shown in Fig. 4.8. If we apply a ramp ( X = 0, 1, 2, … ) , the out-
put current at the sampling instants will be given by
n n–1
–T ⁄ τL –T ⁄ τL –T ⁄ τL
∑ (1 – e ∑e
+
I out(n) = I LSB ⋅ ) = n ⋅ I LSB – I LSB ⋅ e ⋅ =
k=1 k=0
– nT ⁄ τ L –T ⁄ τL
1–e e
= n ⋅ I LSB – I LSB ⋅ e –T ⁄ τ L ⋅ --------------------------
–T ⁄ τL
≈ n ⋅ I LSB – I LSB ⋅ -----------------------
-, (4.50)
1–e 1 – e –T ⁄ τL
where the latter approximation holds for larger n . We see from (4.50) that the settling error
will stabilize and become independent of n .
We get the differential output current as the difference between the dual outputs in (4.48) and
(4.49)
+ –
I diff (n + 1) = I out(n + 1) – I out(n + 1) . (4.51)
Using (4.48) and (4.49) in (4.51) gives
I diff (n + 1) = 2I LSB ⋅ X̃ n + 1 ⋅ [ 1 – e –T ⁄ τ L ] + I diff (n) ⋅ e –T ⁄ τ L . (4.52)
This expression is transformed into the z-domain and we get
1 – e –T ⁄ τL
I diff (z) = 2I LSB ⋅ -----------------------------------
- ⋅ X̃ (z) . (4.53)
1 – e –T ⁄ τL ⋅ z –1
The differential output current from (4.53) can be considered as the output from a linear sys-
tem to which the signal X̃ has been applied. This system function is identified as
1 – e –T ⁄ τL
H (z) = 2I LSB ⋅ -----------------------------------
-. (4.54)
1 – e –T ⁄ τL ⋅ z –1
On the unit circle, we have z = e jωT where ωT is the normalized angular frequency (or the
angle). We get
ωT
–T ⁄ τL 2I LSB ⁄ cosh -------- T
jω ---
1–e 2
H (z) = 2I LSB ⋅ ---------------------------------------
- = ----------------------------------------------------- ⋅ e 2 . (4.55)
– T ( jω + 1 ⁄ τ L ) ωT T
1–e 1 + j tanh -------- ⁄ tan --------
2 2τ L
If the input is a sinusoid, e.g. X̃ = X AC ⋅ sin ( ω 0 T ⋅ n ) , the signal is an eigenfunction of the

linear system and we have the output current given by
jω T jω T
I diff (nT ) = X AC ⋅ H (e 0 ) ⋅ sin ( ω 0 T ⋅ n + arg H (e 0 ) ) . (4.56)
Using (4.55) and (4.56) we can write the squared output current
ω0 T 2
2I LSB ⁄ cosh ----------
2 2 2
I diff (nT ) = X AC ⋅ ------------------------------------------------------------2- ⋅ sin2 ( ω 0 T ⋅ n + ϕ ) , (4.57)
ω0 T T
1 + tanh --------- - ⁄ tan --------
2 2τ L
where ϕ is the corresponding phase at the frequency (angle) ωT . The ideal output current
would be given by
2 2 2
Ĩ diff (nT ) = 4I LSB ⋅ X AC ⋅ sin2 ( ω 0 T ⋅ n ) . (4.58)
We find the power ratio (PR) between the amplitudes of the currents in (4.58) and (4.57),
hence
 ω0 T 
2 ---------
2
⋅
2
ω0 T  tanh -
4I LSB X AC 2 
PR = ---------------------------------------------------------------------------
- = cosh - ⋅  1 + ------------------------ .
2 --------- (4.59)
ω0 T 2 2 
tan2 -------- 
T
2I LSB ⁄ cosh ----------  2τ L 
2 2
X AC ⋅ ------------------------------------------------------------2-
ω0 T T
1 + tanh --------- - ⁄ tan --------
2 2τ L
The worst-case PR is found at the Nyquist frequency, i.e., ω 0 T = π , where it is given by
T
PR = cosh2 -------- . (4.60)
2τ L
We may for example want that this power ratio should meet an N -bit specification and in that
case we require that the power ratio should be larger than the SQNR, hence
T 3
cosh2 -------- ≥ --- ⋅ 2 2N , (4.61)
2τ L 2
which gives
T T
-------- – --------
2τ L 2τ L
e +e ≥ 6 ⋅ 2N . (4.62)
We find that for large N (4.62) becomes approximately

T
--------
2τ L
e ≥ 6 ⋅ 2N , (4.63)
which further yields that
T ≥ τ L ⋅ ln ( 6 ⋅ 2 2N ) ≈ τ L ⋅ ( 1.39 ⋅ N + 1.79 ) . (4.64)
From (4.64) we draw the conclusion that the larger number of bits, the higher update period is
required. For example, with N = 14 , R L = 50 Ω , C L = 1 nF, we have that T ≥ 1.06 µs or
in terms of frequency, we require that f u < 940 kHz.
4.3.2 Static Error Current

In the static case we assume that the sampling time period goes towards infinity. Therefore,
we do not consider capacitive elements. When the current sources are switched to or from the
outputs, the total output resistance is changed and the currents through the loads can be found
as
+ I LSB ⋅ ( X DC + X̃ n ) 1 + x̃ n
- = I DC ⋅ ---------------------------
I out(nT ) = ------------------------------------------------ (4.65)
1 + ρ G ⋅ ( X DC + X̃ n ) 1 + ρ' G ⋅ x̃ n
and
– I LSB ⋅ ( X DC – X̃ n ) 1 – x̃ n
- = I DC ⋅ -------------------------- .
I out(nT ) = ------------------------------------------------ (4.66)
1 + ρ G ⋅ ( X DC – X̃ n ) 1 – ρ' G ⋅ x̃ n
We see that the output currents are not linearly dependent on the input x̃ . Instead we have a
nonlinear behavior and there will be distortion in the output. In Fig. 4.11 (a) we show the sim-
ulated static nonlinear effect on the positive output current of a 14-bit DAC. The input signal
is a single-tone full-scale sinusoid. The load resistance is 50 Ω and the output resistance of the
unit current source is 5 GΩ and hence the conductance ratio is ρ G = 10 –8 . The simulated
SFDR is approximately 88 dB. In terms of linearity this corresponds to an approximate 14-bit
resolution. The differential output current, shown in Fig. 4.11 (b), gives a much better result,
since then the even order harmonics are cancelled. The distortion terms are hidden below the
noise floor, and instead we use the SNDR which is approximately 86 dB and corresponds to a
14-bit resolution.
DAC positive output DAC differential output

0 0
−36 −36
Power [dB]
Power [dB]
−72 −72
−118 −118
0 0.55 1.1 0 0.552 1.104

(a) (b)
Figure 4.11 (a) Single-ended and (b) differential output spectra with a conductance ratio of 10–8.
We get back to the discussion on sinusoid inputs in Sec. 4.3.4 and Sec. 4.3.5. First, we ellabo-
rate on the static DNL and INL measures.
4.3.3 DNL and INL as Function of the Output Resistance

There is an obvious inhereted nonlinearity given by (4.65) and (4.66) and we show how this
affects the differential and integral nonlinearities (DNL and INL). The definitions of DNL and
INL were given in Chapter 2 and for a ramped offset-binary input, X = k ,
k = 0, …, 2 N – 1 , they apply as
I out(k) – I out(k – 1)
DNL k = ---------------------------------------------
- – 1 LSB (4.67)
I LSB
and
k
I out(k) – I out(0)
INL k = INL 0 + ∑ DNLi = ------------------------------------
I LSB
- – k LSB. (4.68)
i=1
In the static case (Sec. 4.3.2) we do not consider the capacitive elements and the settled values
are used. No best-fit line compensation has been applied to the definitions above. For the posi-
tive output current we find the DNL by inserting (4.65) in (4.67) and (4.68)
k k–1
DNL k = ----------------------- – ------------------------------------- – 1 =
1 + ρG ⋅ k 1 + ρG ⋅ ( k – 1 )
1 1
= -------------------------------------------------------------------------- – 1 ≈ ------------------------------2 – 1 (4.69)
( 1 + ρG ⋅ k ) ⋅ ( 1 + ρG ⋅ ( k – 1 ) ) ( 1 + ρG ⋅ k )
and
k ρG ⋅ k 2
INL k = ----------------------- – 0 – k = – ----------------------- . (4.70)
1 + ρG ⋅ k 1 + ρG ⋅ k
The best-fit line can of course be derived as a function of the conductance parameter, but since
the DNL and INL are of minor interest for our applications we leave this as a remark for
future work. We find in (4.69) that the DNL is a decreasing monotonic function, since the
term
1
------------------------------2 (4.71)
( 1 + ρG ⋅ k )
is positive and decreasing towards zero for increasing X = k . This implies that DNL is
always larger than -1 LSB and less than 0 LSB. Therefore, with respect to finite output resis-
tance the DAC is always monotonic.
In Fig. 4.12 we illustrate the DNL and INL for the single-ended output of a 14-bit DAC with a
conductance ratio of ρ G = 10 –8 as the case in Sec. 4.3.2. In the figure we show the DNL and
INL associated with the best-fit line approach. The best-fit offset and gradient values were
found to be approximately
I LSB ⋅ 0.999836 and I LSB ⋅ 0.447223 . (4.72)
Same DAC that was used for the simulation result shown in Fig. 4.11 (a) were used to find the
INL and DNL as plotted in Fig. 4.12. We identify the nonlinearity parameter c from the
assumption that the output current can be written
I out = a + b ⋅ X + c ⋅ X 2 + O(X ) , (4.73)

where O(X ) contains higher-order terms that are neglected. By using the least-square method
we get for the chosen N -bit DAC example ( ρ G = 10 –8 ) that
–5 –6 2
a ≈ 2.2 ×10 ⋅ I LSB , b ≈ I LSB , and c ≈ – 8.2 ×10 ⋅ I LSB . (4.74)
Notice that for this conductance ratio we would get an SFDR of 88 dB (Fig. 4.11). Since the
88 dB is larger than the 86 dB corresponding to 14-bits, the INL will also be less than half an
LSB. Applying a FS sinusoid to the function in (4.73) and using the result from (2.43) gives
the harmonic distortion (HD)
c2 ⋅ 22( N – 1) ⁄ 4
HD = -------------------------------------------- ⇒ HD = 88 dB. (4.75)
( b + 2 ⋅ c ⋅ 2 N – 1 )2
In the single-ended case, the HD also determines the SFDR and we find it to be approximately
equal to what we found in the previous section. However, it is a tedious work using this
approach and in the following we use some other approaches to find the SNDR and SFDR.
Secondly, we are not able to extract parameters such as the conductance ratio from (4.75) in a
very convenient way.
−4 Simulated DNL using best−fit line Simulated INL using best−fit line
x 10
2
0.3
1
DNL [LSB]
INL [LSB]
0 0
−1
−0.3
−2
4096 8192 12288 4096 8192 12288
Input code Input code
(a) (b)
Figure 4.12 Simulated DNL and INL as a function of input code for a resistance ratio of 108.
4.3.4 SNDR as Function of the Output Resistance

The error current, ∆I ( X ) , is the difference between the expected current and the degraded
output current. For the single-ended case we get
I LSB ⋅ X ρG ⋅ X 2
- = I LSB ⋅ ------------------------ =
∆I (X ) = Ĩ out ( X ) – I out ( X ) = I LSB ⋅ X – -----------------------
1 + ρG ⋅ X 1 + ρG ⋅ X
ρ G ⋅ ( X DC + X̃ ) 2 ρ' G ⋅ ( 1 + x̃ ) 2
= I LSB ⋅ ----------------------------------------------- = I LSB ⋅ X DC ⋅ -------------------------------- . (4.76)
1 + ρ G ⋅ ( X DC + X̃ ) 1 + ρ' G ⋅ x̃
From Chapter 2 we remember the discussion on quantization or truncation noise. The expres-
sion in (4.76) was compared to an ideal continuous-time current, which is given by a ramped
input. The error power, P e , is given by the difference between the continuous-time current
and the piece-wise linear output current and hence the error power is also dependent on the
code applied to the converter
T ⁄2 2
2 – I LSB ∆I (X ) t 3 T ⁄2
∆I (X ) –  --- ⋅ I LSB dt = ------------- ⋅  -------------- – ---
1 t
P e(X ) = ---
T ∫ T  3  I LSB T  –T ⁄ 2
=
–T ⁄ 2
2
I LSB
= ---------- + [ ∆I (X ) ] 2 , (4.77)
12
where T is the update period. From (4.77) we identify the quantization noise power
2
I LSB
P q = ---------
-. (4.78)
12
We find the time-average error power (the expected output power) to be
P e( X ) = P e = P q + P ε , (4.79)
where P ε is the time-averaged power of the error current introduced by the degraded con-
verter is denoted
P ε = [ ∆I ( X ) ] 2 . (4.80)
Let the input signal be a sinusoid
X (n) = X DC + X AC ⋅ sin ( ωT ⋅ n ) + ν , (4.81)
where X DC is the DC level of the signal, X AC is the amplitude of the sinusoid, ωT is the
normalized angular frequency, n is the sequence index, and ν corresponds to the quantization
error which is considered to be white for higher-resolution converters. The AC power of the
sinusoid at the output is given by
2
X AC 2
P s = ---------- ⋅ I LSB . (4.82)
2
Due to the nonlinearity, there will be distortion terms folded back onto the signal tone as well.
The extraction of an exact formula can become somewhat tedious and the results are not easy
to interpret (Sec. 8.3). Therefore, an approximate of the average error, P ε , is used as
ρ' G ⋅ ( 1 + x̃ ) 2 2
P ε = I LSB ⋅ X DC ⋅ -------------------------------- ≈ [ I LSB ⋅ X DC ⋅ ρ' G ⋅ ( 1 + x̃ ) 2 ] 2 =
1 + ρ' G ⋅ x̃
= ( I LSB ⋅ X DC ⋅ ρ' G ) 2 ⋅ ( 1 + x̃ ) 4 = ( I LSB ⋅ X DC ⋅ ρ' G ) 2 ⋅  1 + --- x 2 + --- x 4 ,

6 3
(4.83)
 2 8 
where x = X AC ⁄ X DC . Further on, we neglect the DC error, since this is of less importance
for us. Therefore, we get
X AC 2 1 X AC 4
P ε = 3 ( I LSB ⋅ X DC ⋅ ρ' G ) 2 ⋅  ---------- + --- ⋅  ---------- (4.84)
 X DC 8  X DC
Now, we find the signal-to-noise-and-distortion ratio (SNDR) as a function of the output

impedance by combining (4.82), (4.79), and (4.84), hence
2
P Ps X AC ⁄ 2
SNDR = -----s = -----------------
- = ---------------------------------------------------------------------
-. (4.85)
Pe Pq + Pε
2  2 AC 
X 4
1 1
------ + 3ρ' G ⋅  X AC + --- ⋅ ---------- -
12  8 X DC  2
In Fig. 4.13 (a) we show the simulated SNDRs of 10-bit, 12-bit, and 14-bit DACs as functions
of the conductance ratio, ρ G . The input signal is a full-scale sinusoid and we measure the
positive output currents. In the simulation we use a 50- Ω load resistance. The simulated
SNDR is compared with the calculated results from (4.85) and the formula is well verified
although there is a small deviation due to the approximations in (4.83). It is though important
to understand that the formula describe a lower bound. We find that the different SNDRs
reach their maximum for low conductance ratios, i.e., the quantization noise is dominating
and we have
SNDR = 6.02 ⋅ N + 1.76 dB. (4.86)
Simulated and calculated single−ended SNDR Simulated and calculated differential SNDR
86
14
86
74 14
12
74
62 12
10
SNDR [dB]
SNDR [dB]
62
50 10
50
38
38
26
26
14
14
−10 −8 −6 −4 −10 −8 −6 −4
10 10 10 10 10 10 10 10
Conductance ratio Conductance ratio
Figure 4.13 Simulated (solid) and calculated (dashed) (a) single-ended and (b) differential SNDR as
For intermediate conductance ratios where the error due to finite output impedance are much
larger than the quantization noise, we have the approximation of (4.85) as
1 1
SNDR ≈ --------------------------------------------- ≈ -----------------------------------------------------
2 2 2
- (4.87)
2  X AC  6ρ G ⋅ ( X DC + X AC ⁄ 8 )
2
6ρ' G ⋅  1 + ------------- -
 8X DC 2

and in dB, we get

 X AC2 
SNDR ≈ – 8 + 10 ⋅ log10  1 + -------------
- – 20 ⋅ log10 X DC – 20 ⋅ log10 ρ G dB. (4.88)
 8X DC 2

We see that with increasing AC amplitude, the SNDR is improved. Further, assuming that the
input signal is a FS sinusoid, i.e.,
X AC = X DC ≈ 2 N – 1 , (4.89)
we get the approximate SNDR (in dB)
8
SNDR ≈ 10 ⋅ log10 ---------- – 6 ( N – 1 ) – 20 ⋅ log10 ρ G ≈ – 6 ( N – 0.4 ) – 20 ⋅ log10 ρ G . (4.90)
9⋅6
From (4.85) and (4.88) we also find that with increased amplitude the SNDR is improved, but
by increasing the DC level the SNDR is decreasing. This is examplified in Fig. 4.14 where we
show the simulated and calculated SNDR as function of the AC amplitude level for a 14-bit
DAC. The conductance ratio is ρ G = 10 –8 .
In the differential case the SNDR will improve since even-order harmonics cancel. It can for
this case be shown (Sec. 8.3) that for intermediate conductance ratios, the SNDR is approxi-
mately (in dB)
4 2 2
SNDR ≈ 9 – 20 ⋅ log10 ρ G – 10 ⋅ log10 ( 5X AC ⋅ ρ G2 – 24X AC ⋅ X DC ⋅ ρ G + 32X DC ) . (4.91)
In Fig. 4.13 (b) we show the simulated SNDR as function of the conductance ratio for the dif-
ferential output of the 10-, 12-, and 14-bit converters with FS single-tone inputs. We get a
very good resemblance. Notice the influence of the double signal power due to the differential
mode.
Simulated and calculated single−ended SNDR
75
72
62
SNDR [dB]
50
Simulated
38
Calculated
−48 −42 −36 −30 −24 −18 −12 −6 0

Figure 4.14 Simulated (solid) and calculated (dashed) single-ended SNDR as function of the AC level.
4.3.5 SFDR as Function of the Output Resistance

The SNDR gives us an indication on the total error power. In some applications it is more
interesting to find out how the error is distributed throughout the frequency domain. Espe-
cially, how large the harmonics are. They can be derived by finding the Taylor expansion of
the transfer characteristics. We may also find them by considering the case of single sinusoid
input as given in (4.81). The current through the load as determined by (4.65) becomes
I LSB ⋅ ( X DC + X AC ⋅ sin α ) 1 + x ⋅ sin α
I out(X ) = --------------------------------------------------------------------- = I DC ⋅ ---------------------------------------- , (4.92)
1 + ρ G ⋅ ( X DC + X AC ⋅ sin α ) 1 + ρ' G ⋅ x ⋅ sin α
where x = X AC ⁄ X DC and the noise term ν from (4.81) has been neglected. To simplify the
notation, we let α = ωT ⋅ n be the angle. (4.92) is rewritten as
I DC
I out(X ) = I DC ⋅  1 + ------- – --------- ⋅ ---------------------------------------- .
1 1
(4.93)
 ρ' G ρ' G 1 + ρ' G ⋅ x ⋅ sin α
Examining (4.93) we find that only the second term contains AC components, hence for this
analysis we neglect the first DC term. When finding the SFDR or the harmonic distortion we
only care about the power ratio between the fundamental and the largest harmonic tone.
Therefore, the sign and the gain factor of the second term may be neglected as well. We iden-
tify a normalized AC current as
1 1
I AC(X ) = ---------------------------------------- = ----------------------------- , (4.94)
1 + ρ' G ⋅ x ⋅ sin α 1 + A ⋅ sin α
where
X AC ρ G ⋅ X AC
A = ρ' G ⋅ x = ρ' G ⋅ ---------- = ------------------------------
-. (4.95)
X DC 1 + ρ G ⋅ X DC
We assume that the signal is not clipping which normally implies that X AC < X DC and
X DC ≈ 2 N – 1 . Therefore, we also know that
0≤A<1 (4.96)
and
A ⋅ sin α < 1 . (4.97)
Using the property in (4.97) we know that the normalized AC current in (4.94) can be written
as a converging Taylor expansion series. We have
∞
I AC(X ) = ∑ ( – A ) n ⋅ sinn α . (4.98)
n=0
We isolate the DC term and the fundamental tone and we split the sum into the positive and
negative values
∞ ∞
I AC(X ) = 1 – A ⋅ sin α + ∑ A 2n ⋅ sin2n α – ∑ A 2n + 1 ⋅ sin2n + 1 α (4.99)
n=1 n=1
The DC level (unity) and the linear gain ( A ) can once again be neglected. By using trigono-
metric formulas, we find that (4.98) is equal to
∞ 2n ∞ 2n
 ---
A  2n + 1 – cos 2α ⋅ 2  ---
A  2n  ,
I AC(X ) = f (X ) – sin α ⋅ A ⋅ 1 + ∑  2  n  ∑  2  n – 1
n=1 n=1
(4.100)
where f (X ) contains the DC component and higher order harmonics that do not influence the
SFDR. In Sec. 8.3 a derivation of the SFDR is given and it is shown that the power of the har-
monics are decreasing with higher frequencies. The SFDR is now found as the power ratio
between the fundamental and the second harmonic as
∞ 2n
2
1 + ∑  --- 
A 2n + 1
 2   n  2
A2 1 + 1 – A2
SFDR = ------ ⋅ -------------------------------------------------------
n=1
- =  ----------------------------- o. (4.101)
4 ∞ 2n  A 
∑  ---2   n – 1
A 2n
n=1
By substituting back A from (4.95) in (4.101) we get the SFDR expressed in the amplitude
levels as
2
1 1
SFDR = --------------- + ---------------------2- – 1 . (4.102)
ρ' G ⋅ x ( ρ' G ⋅ x )
When the conductance ratio, ρ G , is small, i.e., well-designed current sources, we have that
(4.102) can be approximated
1 2 4
SFDR ≈ 2 ⋅ --------------- = ---------------------2- . (4.103)
ρ' G ⋅ x ( ρ' G ⋅ x )
Further, if ρ G ⋅ X DC « 1 , or ρ' G ≈ ρ G ⋅ X DC , the SFDR becomes approximately
4
SFDR ≈ ----------------------------2- . (4.104)
( ρ G ⋅ X AC )
In dB we may write (4.104) as
4
SFDR = 10 ⋅ log10 ----------------------------2- = 6 – 20 ⋅ log10 ρ G – 20 ⋅ log10 X AC dB. (4.105)
( ρ G ⋅ X AC )
The SFDR is strongly dependent on both the conductance ratio and the AC amplitude. We see
that for increasing AC amplitude, the SFDR decreases. For the (worst-) case of a full-scale
signal, i.e. X AC = X DC ≈ 2 N – 1 , we have
1 2
SFDR = 1 + ---------------------- ⋅ ( 1 + 1 + 2 ⋅ X DC ⋅ ρ G ) , (4.106)
ρ G ⋅ X DC
which equals
1 2
- ⋅ ( 1 + 1 + 2 N ⋅ ρG )
SFDR = 1 + ----------------------- (4.107)
ρG ⋅ 2 N – 1
or if we assume that ρ G is small we have
SFDR ≈ 6 – 20 ⋅ log10 ρ G – 20 ⋅ log10 2 N – 1 = – 20 ⋅ log10 ρ G – 6 ⋅ ( N – 2 ) dB. (4.108)
From (4.105) we realize that with a doubling of the load resistance, the conductance ratio is
doubled and the SFDR is decreased by 6 dB. From (4.108) we see that with a maintained con-
ductance ratio, the linearity will also deteriorate with an increased nominal number of bits.
In Fig. 4.15 (a) we show the simulated and calculated single-ended SFDR as function of the
conductance ratio for a 10-, 12-, and 14-bit DACs. At low ratios (well-designed current
sources) the simulated values are saturated since the spuriouses are hidden in the noise floor
(due to short vector lenghts in the simulations) and at high ratios (poor current sources) the
distortion becomes large (compare Fig. 4.13). The simulated SFDR follows the mathematical
result well. From the results we also find that lower-bit converters are less sensitive to low
output resistance.
Simulated and calculated single−ended SFDR Simulated and calculated differential SFDR
110 110
14 14
104 104
12 12
91 91
SFDR [dB]
10
SFDR [dB]
10
76 76
62 62
47 47
33 33
−10 −8 −6 −4 −10 −8 −6 −4
10 10 10 10 10 10 10 10
Conductance ratio Conductance ratio
Figure 4.15 Simulated (solid) and calculated (dashed) (a) single-ended and (b) differential SFDR as
Using differential signals, harmonics of odd order will be cancelled and the third harmonic
dominates. It can be found (Sec. 8.3) that the SFDR in this case is
2
SFDR = 1 – --------------- ⋅  --------------- + ---------------------2- – 1
2 1 1
. (4.109)
ρ' G ⋅ x  ρ' G ⋅ x ( ρ' G ⋅ x ) 
For low conductance ratios, this is approximately
16
SFDR ≈ ---------------------4- . (4.110)
( ρ' G ⋅ x )
For X DC = X AC ≈ 2 N – 1 and ρ G ⋅ X DC « 1 we get

SFDR ≈ – 40 ⋅ log10 ρ G – 12 ⋅ ( N – 2 ) dB. (4.111)
In Fig. 4.15 (b) we find the simulated and calculated SFDR for the differential output. From
(4.108) and (4.111) we find that the SFDR with respect to the third harmonic is decreasing
faster with respect to an increase of the nominal number of bits, N , than for the SFDR with
respect to the second harmonic. However, it is obvious that if a differential output signal is
used, the requirements on the output impedance can be relaxed hence a higher conductance
ratio, ρ G , is allowed. For example, for a 14-bit converter and with a conductance ratio of
10 –8 we get SFDR ≈ 88 dB in the single-ended case and in the differential case we would get
as much as SFDR ≈ 176 dB. The design problem is that the output impedance is decreasing
by -20 dB / decade due to the output pole of the current sources. Therefore, the SFDR will
also decrease with higher frequencies. This is discussed later on in the thesis.
4.3.6 Influence of Parasitic Resistance

In the previous models, we only considered the load and DAC output conductances. Now we
consider the situation with finite switch on-resistance and parasitic wire resistance. Consider
the modified current source in Fig. 4.16. For the current source corresponding to the k -th bit
we include a parasitic resistance, R p, k , which is associated with interconnection wires and the
on-resistance of switches. Hence in this case, we assume that the switch is a transistor operat-
ing in its linear region. In the model, we also assume that for each bit one single switch is
used but typically implemented with differently sized transistor. It is obvious that the parasitic
resistance will influence the MSB current sources more than the LSB sources due to the lower
output resistance of the MSB current sources.
2k-1GS
2k-1I LSB (k)
Gsrc
(k)
Isrc
Rpar,k
RL
RL
(a) (b)
Figure 4.16 (a) Model of the current source at bit position k with parasitic resistance, Rpar,k, from
switches and internal wires and (b) modified model.
Using Norton’s theorem, the circuit in Fig. 4.16 (a) can be transformed into the case shown in
(b). The current source then becomes similar to the one illustrated in Fig. 4.5. For the k -th bit
we get a current source with the value
(k) I LSB ⋅ 2 k – 1
I src = -----------------------------------------------
- (4.112)
1 + G S ⋅ R p, k ⋅ 2 k – 1
and the output conductance
(k) GS ⋅ 2 k – 1
GS = -----------------------------------------------
-. (4.113)
1 + G S ⋅ R p, k ⋅ 2 k – 1
The effects of the parasitics, as given in (4.112) and (4.113), can be included in the expression
for the output current as in (4.65)
N N
(k) 2 k – 1 ⋅ bk
∑ I src ⋅ bk I LSB ⋅ ∑ 1 + G ⋅ R ⋅ 2 k – 1-
-----------------------------------------------
k=1 k=1 S p, k
I out(X ) = ---------------------------------------
(k)
- = ------------------------------------------------------------------------------
N
-, (4.114)
N
2 k – 1⋅b
GS
1 + ∑ ---------- ⋅ b k 1 + ρ G ⋅ ∑ ----------------------------------------------- k
-
GL 1 + G S ⋅ R p, k ⋅ 2 k – 1
k=1 k=1
where b k are the individual bits in X . If we assume that the switches are designed progres-
sively so that the on-resistance is decreasing with higher bit significance, i.e.,
R p, k = 2 –( k – 1 ) ⋅ R p . For this case, we have the output current from (4.114) as
N
2 k – 1 ⋅ bk I LSB
I LSB ⋅∑ 1 + GS ⋅ R p-
-------------------------- -⋅X
--------------------------
1 + GS ⋅ R p
k=1
I out(X ) = ---------------------------------------------------------
- = --------------------------------------------- . (4.115)
N
2k – 1 ⋅ bk ρG
1 + ρ G ⋅ ∑ --------------------------- 1 + --------------------------- ⋅ X
1 + GS ⋅ R p 1 + GS ⋅ R p
k=1
This will give rise to a gain error of 1 ⁄ ( 1 + G S ⋅ R p ) and the conductance ratio will be modi-
fied as
ρG
ρ G, p = --------------------------
-. (4.116)
1 + GS ⋅ R p
The result from (4.116) is then be used in the expressions for DNL, INL, SFDR, and SNDR
that were derived in the previous sections. As the output conductance decreases, the influence
of the switch on-resistance becomes more severe.
4.3.7 SNDR and SFDR as Functions of the Output Impedance

As was illustrated in Fig. 4.9 and Fig. 4.10 we found that with higher signal and/or clock fre-
quencies the nonlinearity increases, hence the SNDR and SFDR decrease. It is therefore inter-
esting to know by how much these measures will decrease and which parameters that
determine the influence.
In Fig. 4.17 we show with solid lines how the measured differential SFDR is decreasing with
higher sample frequency for a 14-bit DAC and two different input frequencies. The signal’s
amplitude level is –3 dBFS. We see how the performance is decreasing with higher frequen-
cies and higher SUFR. The measured converter is a 5-V current-steering DAC processed in
0.6-µm CMOS and the output currents are terminated over 50 Ohms each and fed into a trans-
former. We see that the SFDR is decreasing with higher SUFR and with increased clock fre-
quency by approximately –16 dB/decade. In the figure we show the simulated SFDR results
with dashed lines and same frequencies and amplitude levels. In the simulation, we have used
a conductance ratio of ρ G = 10 –9 and a capacitance ratio of ρ C = 9 ⋅ 10 –8 . The measured
SFDR is dotted. The signal frequencies are around f s ⁄ 25 where f s is the sample frequency.
The measurement setup is further presented in Chapter 5.
Simulated and measured SFDR
Simulated
Measured
75
Measured
65
SFDR [dB]
55
45
5 20 50
Sample frequency [MHz]
Figure 4.17 Measured and simulated SFDR as function of the signal and update frequencies.
For future analysis we would introduce the impedance or admittance ratio. The impedance
ratio is defined
Z R S + 1 ⁄ jωC S 1 1 + jωτ S
- = ------ ⋅ ---------------------- ,
ρ Z = -----S- = --------------------------------- (4.117)
ZL R L + 1 ⁄ jωC L ρ C 1 + jωτ L
where R S and C S are the output resistance and capacitance of the unit current source. R L and
C L are the load resistance and capacitance, and τ S is the time constant of the unit current
source and τ L is the time constant of the load impedance. The admittance ratio is given by
Y G S + jωC S 1 + jωτ S
- = ρ G ⋅ ---------------------- .
ρ Y = -----S- = -------------------------- (4.118)
YL G L + jωC L 1 + jωτ L
Typically, τ S » τ L due to the high output impedance and we have that for frequencies between
e.g. 1 ⁄ τ 1 and 1 ⁄ τ 2 the admittance ratio is increasing by 20 dB/decade. An analytical for-
mula that describes the SNDR and SFDR as functions of the different parameters is hard to
find due to the rather high complexity. Roughly, we can for example use the absolute value on
the admittance ratio to use as the conductance ratio in the previously derived formulas. This
will however give an upper bound on the achievable result. The influence of the increased
clock frequency is for example not covered. This is left as future work and some results are
also presented in related publications [74, 75, 77]. In Chapter 5 we find another comparison of
calculated, simulated and measured SFDR.
4.3.8 Influence of Parasitic Impedance

The switches and the interconnection wires will also introduce parasitic capacitance. This will
give rise to additional poles that significantly increases the complexity of the system.
The analysis in general follows the concept as was presented in the previous sections. For the
parasitic resistances we can rewrite the situation as we did in Sec. 4.3.6 and hence introduce
modified conductance and capactiance ratio parameters. We will however also add some volt-
age sources dependent on the previous sampling instant for the switch and wire capacitances
as well. (Compare with the derivations in Sec. 4.3). Dependent on how we model the switched
and interconnection wires, e.g., lumped or distributed RC-networks, the models can be simpli-
fied since some of the capacitive elements can be neglected since they will be connected in
parallel with the dominating load capacitance. In related work [74, 78] we have been further
focusing on these issues.
4.4 Influence of Circuit Noise

Another limit on achievable resolution and performance is the noise level found at the output.
The resolution of the converter is guaranteed as long as the circuit noise and induced noise
power within the Nyquist band is sufficiently lower than the quantization noise power.
We model the circuit noise in the unit current sources as shown in Fig. 4.18, i.e., as an error
current source in parallel with the unit current source. Further, each unit current source is
associated with an output conductance and capacitance, G S and R S . We denote the actual
output current from each unit current source as I u, m where m = 1, 2, …, 2 N – 1 . We have
the ideal output Ĩ u, m = I u = I LSB . With each unit current source, I u, m , a noise current
source, δi u, m , is associated. We assume that the noise is Gaussian distributed and that the
sources are all uncorrelated. The mean value and variance of the noise are given by
E { δi u, m } = 0 (4.119)
and
2 2 2
E { δi u, m } = δi u = σ n . (4.120)
Iu,m
2
diu,m
~
Iu,m
Figure 4.18 Unit current source with noise current source, δiu,m.
The load impedance (if we assume it to be dominating) will LP filter and we have the approxi-
mate noise bandwidth [7, 8]
1
BW ≈ -------- . (4.121)
4τ L
The induced noise error vary with time and have different amplitudes at different sampling
instants. For each new sample, we have a new noise amplitude level for the corresponding
Influence of Circuit Noise 111
current sources. We assume that the standard deviation and mean values are independent of
time. We have the output current with the noise included (at the sampling instants)
N
I out(nTs) = I u ⋅ X (nT ) + ∑  bk(nT ) ⋅ ∑ δi u, m(nT ) ,

(4.122)
k=1 m ∈ Mk
where M k is the set of unit current sources associated with the k -th bit. Typically, these set of
transistors is chosen so that the matching errors are minimized. The normalized total output
noise power, P n(nT ) , within the bandwidth, BW , is given by the sum of the contribution
from all noise sources, and the instantenous sum is signal and time dependent [7]. We have
N 2
 
∑ bk(nT ) ⋅ ∑
2
P n(nT ) = δi tot = E δi u, m(nT )  =
 k=1 m ∈ Mk 
N N
∑ ∑ ∑ bk(nT ) ⋅ ∑
2 2 2
= b k (nT ) ⋅ E { δi u, m(nT ) } = σn =
k=1 m ∈ Mk k=1 m ∈ Mk
N
∑ bk(nT ) ⋅ 2 k – 1
2 2
= σn ⋅ = σ n ⋅ X (nT ) . (4.123)
k=1
According to the discussions in the previous section, the noise current directed to the output
will in reality be influenced by the limited output impedance of the current source [7]. If we
assume that the internal capacitance do not influence the result, we have a transfer function
from each noise current source to the output as
GL 1
H (s) = ---------------------------------------------------
- = ---------------------------------------------------------- . (4.124)
G L + sC L + G S + sC S 1 + ρG + s ( τL + τS ⋅ ρG )
If we assume that the output resistance is very high, i.e., ρ G ≈ 0 , we get that the pole domi-
nates further yielding the noise bandwidth as described in (4.121). Including these kinds of
nonidealities will only introduce minor modifications to the following derivations and there-
fore we neglect their influence. We have the time-averaged normalized noise power
2 2
P n = P n(nT ) = σ n ⋅ X (nT ) = σ n ⋅ X DC , (4.125)
where X DC is the input DC level which normally is set to FS ⁄ 2 . The output power for a
sinusoid is given by
2
X AC 2
P s = ---------- ⋅ I LSB , (4.126)
2
where X AC is the AC amplitude and I LSB is the nominal output current of the LSB source
which in most designs corresponds to the unit current source size, I u . The SNR is found by
comparing (4.125) with (4.126) and adding the quantization noise as we did in (4.76)
2
X AC 2
Ps ---------- ⋅ Iu 6X AC
2
2
SNR = ------------------ = ---------------------------------
2
- = ------------------------------------------- (4.127)
Pq + Pn 2
Iu 2 δi u
------ + σ n ⋅ X DC 1 + 12 ⋅ X DC ⋅ ------ -
12 2
Iu
In the current-steering DAC, the thermal noise from the channel resistance in the MOS current
sources is dominating in wideband applications [7, 8]. As long as the gain in the cascode tran-
sistors is high, the noise will practically be determined by the source transistor. Typically, we
have [7, 8]
2 8kT 2 1 2 1
δi u = ---------- ⋅ g m ⋅ BW ≈ --- kT ⋅ β ⋅ I u ⋅ ----- = --- kT ⋅ β ⋅ I u ⋅ ------------- (4.128)
3 3 τL 3 RL C L
where k is the Boltzmann’s constant, T is the absolute temperature, g m is the small-signal

transconductance of the source transistor, and β is the transconductance parameter. Since the
load resistance most likely is much smaller than the output resistance of the current source,
(4.128) holds for both single transistor and cascoded current sources. In Fig. 4.19 the simu-
lated (solid) and calculated (dashed) SNR for a 14-bit DAC as function of the relative mis-
match stanard deviation is shown. It is seen in Fig. 4.19 that for high unit currents, the thermal
noise becomes lower than the quantization noise and hence the quantization noise determines
the SNR (SNR = SQNR). The simulated curves fit well to the calculated values.
Simulated single−ended SNR
86
80
74
SNDR [dB]
68
62
56
50
−8 −6 −4 −2 0
10 10 10 10 10
Relative noise error
Figure 4.19 Simulated (solid) and calculated (dashed) single-ended SNR as function of the the LSB
current for a 14-bit DAC.
For lower currents, i.e., higher thermal noise, we have that the SNR from (4.127) can be
approximated by the compact formula
2
SNR ≈ 3 ⋅ ( N – 2 ) + 20 ⋅ log10 I u – 10 ⋅ log10 σ n dB. (4.129)
Substituting the values from (4.128) into (4.129) gives the approximate expression
Current Source Mismatch 113
2kT ⁄ 3
SNR ≈ 3 ⋅ ( N – 2 ) + 15 ⋅ log10 I u – 5 ⋅ log10 β – 10 ⋅ log10 ----------------- dB. (4.130)
RL C L
Now, we find how the choice of transistor sizes and unit current values influence the SNR. For
example, consider (4.129). For a 14-bit resolution, we must guarantee that the SNR with
respect to the thermal nosie is higher than the quantization noise, i.e.,
SNR ≥ 6.02 ⋅ N + 1.76 dB. Thereby, we have
2
3 ⋅ ( N – 2 ) + 20 ⋅ log10 I u – 10 ⋅ log10 σ n ≥ 6.02 ⋅ N + 1.76 dB. (4.131)
From (4.131) we get

2
2 Iu
σn ≤ --------------------
-. (4.132)
3 ⋅ 2N + 1
From this equation and (4.128), etc., we can then derive the necessary limits on design param-
eters, such as the transistor widths, etc.
4.5 Current Source Mismatch

In an actual implementation, the current sources will not only due to the limited output imped-
ance and circuit noise give a fault output current. The influence of matching errors makes the
sizes of the transistors to differ from their designed values and hence the output currents will
not be correct. In fact, the matching errors tend to be the dominating error sources in the cur-
rent-steering DACs, since the matching errors are not cancelled by using differential signals.
For the CMOS current source, the so called β - and V T -mismatch can be characterized by
their distribution, the transistor sizes, and physical distance [68, 69]. These issues are further
addressed in Chapter 5 and in this chapter we stay on a higher level of abstraction.
In a similar way as we have derived in the previous sections, the output signal will be dis-
torted. Since a matching error is associated with a certain bit and hence the output error cur-
rent will become signal-dependent. Unlike the noise current, which is of similar nature as the
matching error, the matching errors for one single DAC or chip are static. Hence, they do not
change as function of time, signal or clock frequency. When comparing several chips with
eachother the matching errors will become Gaussian distributed. Therefore, the analysis dis-
cussed in this section will focus on the case of comparing a large number of chips. Hence, we
want to find the expected SFDR and SNDR for a certain standard deviation.
A current source with mismatch error can be modeled as an additional current source (similar
to the noise current source) in parallel with the nominal current source, as shown in Fig. 4.20
for the k -th LSB current source. We still assume that 2 k – 1 unit current sources are used to
define this current source. We denote the actual output current from each unit current source
as I u, m where m = 1, 2, …, 2 N – 1 . Also in this case, we assume that the ideal output is
Ĩ u, m = I u = I LSB . For each unit current source, we associate an absolute matching error,
δI u, m and hence the actual current becomes
I u, m = Ĩ u, m + δI u, m = I u + δI u, m . (4.133)
The relative matching error is given by

Iu,m
DIu,m
~
Iu,m
Figure 4.20 Modeling of current source with error current source, ∆Iu,m.
δI u, m δI u, m
ε u, m = ------------
- = ------------
-. (4.134)
I u, m Iu
In this first discussion we assume that the matching errors are statistically independent and
that they are Gaussian distributed with zero mean and a variance of σ u2 , hence
2 2 2 2
E δ { δI u, m } = 0 and E δ { δI u, m } = σ δ = I u ⋅ σ u for m = 0, …, 2 N – 1 . (4.135)
Another approach would be to consider the entire current source as a stochastic variable with
mean value I u and variance I u2 ⋅ σ u2 . The formulas in the following would apply in the same
way.
We have for the k -th bit its output current
Ik = ∑ I u, m = ∑ ( Ĩ u, m + δI u, m ) = 2 k – 1 ⋅ I u + ∑ δI u, m , (4.136)
m ∈ Mk m ∈ Mk m ∈ Mk
where M k is the set of unit current sources associated with the k -th bit, i.e., M k = 2 k – 1 .
This is a subset of the entire unit current source array. We denote the absolute error for the k -
th bit as
δI k = ∑ δI u, m . (4.137)
m ∈ Mk
As was discussed in Sec. 4.2.1 (equation (4.12)) the variance of the matching error from M
unit current sources in parallel will become M times larger than the variance of the error of a
single unit current source. Thereby, we have that the error current for the k -th bit will have a
variance of
2 2 2 2
σ k = E δ { δI k } = 2 k – 1 ⋅ I u ⋅ σ u . (4.138)
The total output current is given by the contribution from all bits and it becomes
N N N
I (X ) = ∑ I k ⋅ bk = ∑ ( 2k – 1 ⋅ I u + δI k ) ⋅ b k = I u ⋅ X + ∑ δI k ⋅ bk . (4.139)
k=1 k=1 k=1
From (4.139) we identify the absolute output error current as

N
∆I (X ) = ∑ δI k ⋅ bk . (4.140)
k=1
We have the variance of the error current as

N 2 N
 
∑ δI k ⋅ bk ∑ E δ { δI k } ⋅ bk2 .
2 2
σ ∆I (X ) = E δ { [ ∆I (X ) ] 2 } = E δ   = (4.141)
 k=1  k=1
Since b k is 0 or 1, we have that b k2 = b k and using (4.138) in (4.141) gives

N N
∑ ∑ 2 k – 1 ⋅ bm
2 2 2 2 2 2
σ ∆I (X ) = E δ { δI k } ⋅ bk = Iu ⋅ σu ⋅ = I u ⋅ σu ⋅ X , (4.142)
k=1 k=1
which resembles to the result derived for noise in (4.123). From (4.142) we find the variance
of the error current is linearly dependent on the signal level as was also concluded in Sec.
4.2.1. E δ { A } is used to denote the expectation value of A with respect to the stochastic vari-
able δ and the value E δ { A } denotes the average with respect to the code X (hence the input
signal).
In reality, mismatch errors of transistors due to process variations include both graded and sto-
chastic errors. Gradients in oxide thickness and along wires or voltage drops over supply lines
create linear matching errors which are strongly dependent on the layout of the current
sources. These type of errors are discussed in Sec. 4.5.3. However, it is hard to find general-
ized mathematical models, since the matching errors are strongly dependent on layout style.
In Fig. 4.21 we show the output spectrum of a 14-bit DAC when applying matching errors
with a relative standard deviation of 1.5 per cent. The spectrum displayed is the average of
several runs with other randmozied matching errors. The SFDR is approximately 83 dB for an
FS sinusoid input. An interesting notation for differential current-steering DACs is that the
even-order distortion terms due to matching errors are not cancelled as for the case with e.g.
limited output impedance. This is since the two output channels in binary-weighted DACs
never use the same sets of weights instantenously, especially not for FS signals. Therefore, the
errors cannot be cancelled. In reality errors may cancel due to the correlation between differ-
ent weights, etc.
Since the mean values of the matching errors are modeled to be zero we have that the DNL
and INL will not give us any information on the matching errors. Comparing a large number
of chips and using the models above, all matching errors will be averaged towards zero.
Instead, we investigate the power spectra and how the RMS value of the error signal behaves
as a function of amplitude levels and how this is distributed throughout the frequency domain.
However, it must be emphasized that for a single chip, the DNL and INL measures can givev-
ery valuable information on the distribution of the matching errors over the chip.
4.5.1 SNDR as Function of the Stochastic Mismatch Errors

Since the mismatch errors are assumed to be uncorrelated, the average value of the squared
current from (4.139), i.e., the normalized signal power, is
2 2
E δ { [ I (X ) ] } = [ I u ⋅ X ] 2 + E δ { [ ∆I (X ) ] } . (4.143)
Simulated single−ended output with 1.5−% matching error

0
−40
PSD [dB/Hz]
−80
−120
0 0.55 1.1
Frequency [MHz]
Figure 4.21 Output spectrum for a 14-bit DAC with approximate mismatch error standard deviation of
1.5 %.
Using the result from (4.142) in (4.143) gives

2 2 2 2
E δ { [ I (X ) ] } = I u ⋅ X 2 + I u ⋅ X ⋅ σu . (4.144)
We find the code-averaged squared value for the expression in (4.144) as

2 2 2 2 2 2
E δ { [ I (X ) ] 2 } = I u ⋅ X 2 + I u ⋅ σ u ⋅ X = I u ⋅ X 2 + I u ⋅ σ u ⋅ X DC , (4.145)
where X = X DC is the average input, i.e., the DC value. From (4.145) we get the average
error power
2 2
P e = I u ⋅ σ u ⋅ X DC (4.146)
and we see that by reducing the DC value of the signal, we also reduce the error power. How-
ever, in most applications this is not possible since the DC value is fixed to FS ⁄ 2 to allow
maximal signal swing. Assume that the input is given by a sinusoid as in (4.81). Then we have
the signal power as
P s = I u ⋅ X 2 = I u ⋅ ( X DC + X AC ⋅ sin α ) 2 = I u ⋅  X DC + --- ⋅ X AC .

2 2 2 2 1 2
(4.147)
 2 
We find the SNDR by taking the ratio between the signal power and the matching plus noise
error power. For our purpose we neglect the influence from the DC term on the signal power.
We have the SNDR as
1 2 2
Ps --- ⋅ X AC ⋅ I u 6 ⋅ X AC
2
2
SNDR = ------------------ = ------------------------------------------
- = ----------------------------------------
-. (4.148)
Pq + Pe I 2 1 + 12 ⋅ σ u ⋅ X DC
2
2 2
-----u- + I u ⋅ σ u ⋅ X DC
12
With a full-scale signal, X AC = X DC ≈ 2 N – 1 , we have an SNDR of
3 ⋅ 2 2N + 1
SNDR = ------------------------------------
2
-. (4.149)
1 + 3σ u ⋅ 2 N + 1
In dB we have that
2
SNDR ≈ 6.02 ⋅ N + 1.76 – 10 ⋅ log10 ( 1 + 3 ⋅ σ u ⋅ 2 N + 1 ) dB. (4.150)
In Fig. 4.22 we show the simulated (solid) and calculated (dashed) SNDR as function of the
mismatch for 10-, 12-, and 14-bit DACs. The input signal is full-scale. The simulation results
were found by taking the average value of 1024 simulations for each mismatch value. We find
that the simulated values match the calculated ones well. At low mismatch the simulated
curves reach their ideal values determined by SNDR = SQNR ≈ 6.02 ⋅ N + 1.76 dB.
Simulated single−ended SNDR
90
85
14
80
75
12
SNDR [dB]
70
65
60 10
55
50
45
40 −4 −3 −2 −1
10 10 10 10
Mismatch standard deviation
Figure 4.22 Calculated (dashed) and simulated (dashed) SNDR as function of the mismatch error stan-
dard deviation for 10-, 12-, and 14-bit DACs.
4.5.2 SFDR as Function of the Stochastic Mismatch Errors

To find the SFDR, we have to investigate how the mismatch error power is distributed in the
frequency domain. We will do this by investigating the Fourier series coefficients, C f , k . For
bit b k we have
L–1 l
1 – j2π ⋅ --- ⋅ f
C f, k = --- ⋅
L ∑ bk ( l ) ⋅ e L , (4.151)
l=0
where l is the sequence index, L is the signal period in number of samples, and f denotes the
frequency, i.e., f = 1 corresponds to the normalized angular frequency ω 0 T , etc. ω 0 is the
signal angular frequency and T is the sample period. Each Fourier coefficient states the
amplitude and phase of the tone at the corresponding frequency. The Fourier series coeffi-
cients for the (ideal) output current must be given by
IuL – 1 l
– j2π ⋅ --- ⋅ f IuL – 1 N l
– j2π ⋅ --- ⋅ f
C f = ---- ∑ X (l) ⋅ e L = ---- ∑ ∑ 2k – 1 ⋅ b k (l ) ⋅ e L =
L L
l=0 l = 0k = 1
N L–1 l N
1 – j2π ⋅ --- ⋅ f
= Iu ∑ 2k – 1 ⋅ ---
L ∑ b k (l ) ⋅ e L = Iu ∑ 2k – 1 ⋅ C f , k . (4.152)
k=1 l=0 k=1
Further, we find the corresponding Fourier series coefficients for the error current
N
∑  ∑ δI u, m ⋅ C f , k .
(e)
Cf = (4.153)

k = 1 m ≈ Mk
The expectation value of this expression is

N
∑  ∑ E δ { δI u, m } ⋅ C f , k = 0 .
(e)
Eδ{C f } = (4.154)

k = 1 m ∈ Mk
The expected squared absolute value is

N
C (f e )∗ } ∑  ∑ E δ { δI u, m } ⋅ C f , k
2
Eδ{ C (f e ) 2 } = E δ { C (f e ) ⋅ = 2 =

k = 1 m ∈ Mk
N
∑ 2k – 1 ⋅
2 2
= σu ⋅ Iu ⋅ C f, k 2 . (4.155)
k=1
Equation (4.155) expresses the expected power of each tone and frequency. Consider Fig. 4.23
where we show the simulated waveforms for the eight MSBs in a 14-bit converter. The input
signal is a full-scale sinusoid. By investigating how these waveforms determine the different
tones in the frequency-domain, we can determine the distortion. In terms of Fourier series
coefficient, the power of the tone at f is given by
(e)
P s, f = 2 ⋅ E δ { C f } . (4.156)
The harmonic distortion with respect to the f -th tone, HD f , is given by

N
⋅ ∑ 2k – 1 ⋅ C f , k 2
2 2
⋅ Iu σu
P s, f 2 ⋅ E δ { C (f e ) 2 } k=1
HD f = ---------- = -----------------------------------
2 2
- = ----------------------------------------------------------------------------
N
-. (4.157)
Ps 2 ⋅ C1 ⋅ I u
( 1 + σ u ⋅ I u ) ⋅ ∑ 2 k – 1 ⋅ C 1, k 2
2 2
k=1
We see that for the fundamental we have the influence of the matching errors as well (in the
denominator). Neglecting this and expressing the signal power as
2 2
2 2 X AC ⋅ I u
P s = P s, 1 = 2 ⋅ C 1 ⋅ Iu ≈ -------------------- , (4.158)
2
where X AC is the AC amplitude, gives
Characteristic bit waveforms in 8−bit DAC
MSB
Amplitude level
LSB
0 0.25 0.5 0.75 1

Length of period
Figure 4.23 Transient behavior of the individual bits when applying a full-scale sinusoid.
σu ⋅ ∑
2 N
P s, f 2k – 1 ⋅ C f , k 2
k=1
HD f = ---------- = ------------------------------------------------------------
2
-. (4.159)
Ps X ⁄2 AC
Due to the scaling as expressed by (4.152) we assume that the matching error is dominated by
the matching errors in the few MSBs and that the DC level of the signal is given by FS ⁄ 2 .
Notice that these assumptions allow us to derive the approximate harmonic distortion for a
sinusoid with lower power than FS (down to a certain level). If the input signal is a sinusoid,
the MSB will have a pulse width of M ⁄ 2 and a period of M (see Fig. 4.23). For the second
MSB the pulse widths are smaller, but the period is still M . The Fourier series coefficients for
the two MSBs are derived in Sec. 8.4 and we have for odd f that
C f , N 2 ≈ 1 ⁄ ( fπ ) 2 (4.160)
and
 2 cos πf
2
------ – 1
 6 
C f , N – 1 2 ≈ ----------------------------------
-, (4.161)
( πf ) 2
where the approximations hold for smaller f ⁄ M ratios. In the static case, or lower frequen-
cies, i.e., the period M is much larger than the normalized angular frequency fπ . For even f ‘s
the coefficients in (4.160) and (4.161) are zero for the MSBs. For the LSBs, the frequency
spectrum is more noise-like. To find the harmonic distortion we use the approximations in
(4.160), and (4.161) to rewrite (4.157) as
2
 2 cos πf
2 2 N–1 ⋅ σu
⋅∑
2 N
2k – 1 ⋅ C f , k 2 ------ – 1 + 2 ⋅ ----------------------- -
2σ u
k = N–1
 6  ( fπ ) 2
HD f ≈ -----------------------------------------------------------------------
2
- = ------------------------------------------------------------------------------- .
2
(4.162)
X AC ⁄ 2 X AC ⁄ 2
Hence with lower signal amplitude the harmonic distortion increase. This is mainly due to the
fact that the MSB is varying around the DC level although the amplitude is lowered. This is
shown in Fig. 4.24, where we show the expected simulated SNDR as function of the AC
amplitude for a matching error standard deviation of approximately 5% in a 14-bit DAC.
From (4.162), we see that the SFDR will decrease in the same way as well. With an FS sinu-
soid (4.162) becomes approximately
 2 cos πf
2
------ – 1 + 2 ⋅ σ u
2
 6 
HD f ≈ ------------------------------------------------------------
-. (4.163)
2 N – 2 ⋅ ( fπ ) 2
Simulated and calculated single−ended SNDR
67
56
SNDR [dB]
45
33
Simulated
Calculated
−36 −30 −24 −18 −12 −6 0

Figure 4.24 Simulated SNDR as function of the input amplitude for mismatch standard deviation of
5%.
Also notice that there is error tones overlapping the signal at the fundamental frequency. For
improved accuracy we can take this into account as well. However, for the dominating 3rd-
order harmonic ( f = 3 ) , we have an expected harmonic distortion of
2
σu
HD 3 ≈ --------------------------
-. (4.164)
2 N – 2 ⋅ 3π 2
and
2 3π 2
HD f ≈ 10 ⋅ log10 σ u – 3 ⋅ N – 20 ⋅ log10 ---------- ≈ 10 ⋅ log10 σ u – 3 ⋅ N – 8.7 ≈
2
2
≈ 10 ⋅ log10 σ u – 3 ⋅ ( N + 3 ) dB. (4.165)
Thereby, we also find the SFDR which is given by the minimum value of (4.163) for all
f ≥ 3 . As is found in Sec. 8.4 this is the case for f = 3 , i.e.,
2
SFDR ≈ 3 ⋅ ( N + 3 ) – 10 ⋅ log10 σ u dB. (4.166)
In Fig. 4.25 we show the simulated (solid) and calculated (dashed) SFDR for 10-, 12-, and 14-
bit DACs as function of the relative matching error. As we see there is a small deviation
between the simulated and calculated values. This depends on the approximation in (4.162)
where only a few MSBs were considered. Since we are assuming uncorrelated errors, the
error power from all bits should be added to the specific tone. This would result in a slightly
lower calculated SFDR. The curves saturate for lower mismatch errors, since in the simula-
tions the harmonics are hidden in the noise. The simulated results shown in Fig. 4.25 are
found by taking the average from 1024 2 16 -point spectra for each mismatch value.
Simulated single−ended SFDR
111
14
100
12
10
SFDR [dB]
80
60
40
−4 −3 −2 −1
10 10 10 10
Mismatch standard deviation
Figure 4.25 Calculated and simulated SFDR as function of the mismatch for 10-, 12-, and 14-bit
DACs.
Influence of segmentation and thermometer code

A notation is that the distribution of the distortion terms will slightly differ for thermometer
coded and segmented converters. Compare for example the simulation result Figure 7.8 on
page 202 where we have applied matching errors in a 8-bit converter that is fully thermometer
coded. There we find that it is the second harmonic that determines performance. For the
binary converter it is the third harmonic. This is due to the fact that for thermometer-coded
DACs there is not the same fluctuation around the DC level in terms of number of bits that are
switching. With only one LSB changing around DC, all bits are changing in the binary-coded
DAC and hence much worse matching error than for the thermometer-coded DAC where only
one bit changes. Secondly, the analysis must be slightly modified, since we cannot use the
approach as examplified by Fig. 4.23. We get back to this issue in Chapter 5 where we com-
pare measured with simulated results and the mathematical modeling is left for future investi-
gation, where the aim is to generalize the expressions above to fit for a K MSB segmented
converter, where K is arbitrary in the interval 1 < K < N .
4.5.3 SNDR and SFDR as Function of the Graded and

Correlated Mismatch Errors
As was indicated, the matching errors cannot only be considered to be independent Gaussian
distributed variables. In reality, the matching errors in two adjacent current sources can be
highly correlated. This is due to edge matching but also since we most likely have linear
graded distribution of the matching errors over the array of unit current sources. Typically, the
current sources should be distributed in such a way that the gradients are cancelled out as
much as possible. Given a certain assumption on the nature of the linear gradients, e.g., as in
(4.3) and Sec. 4.2.1, we can use an optimization program to find the optimum layout that min-
imizes the influence of these matching errors. This is also discussed in related work [78]
where methods to describe the SFDR and SNDR as functions of the matching error gradients
have been derived. In the work it is assumed that we have laid out the unit current sources in
an array where the unit current sources have been placed in a 2 K × 2 M array with
K + M = N . This is illustrated in Fig. 4.26 where we see that the unit sources are not placed
in an efficient way in terms of reducing the influence of graded matching errors. With this
approach, the LSB current sources will be laid out in one row and the MSB will occupy 2 K – 1
rows. k x and k y are the gradients in the respective directions. It can be shown that for a FS
sinusoid the SFDR and SNDR are approximately given by
SFDR ≈ 21.6 + 6 ⋅ ( M – N ) – 20 ⋅ log10 k y dB (4.167)
and
SNDR ≈ 17 + 6 ⋅ ( M – N ) – 20 ⋅ log10 k y dB. (4.168)
2K
2M
Figure 4.26 Layout of the unit current sources in a folded array structure.
It is noted that the k x parameter is not appearing in the formulas. This is due to the fact that
its influence on the MSBs is zero since for this bit entire rows are used and hence the influ-
ence of the gradient in the x -direction is cancelled. k x will however influence the LSBs, but
its magnitude becomes very small. Instead the k y parameter is the one determining the SFDR
and SNDR for this particular layout style. Also notice that the formulas in (4.167) and (4.168)
are determined for one specific chip. If we take a large number of chips and compare them,
the gradients will also behave as Gaussian distributed parameters and we will end up in results
similar to those in the previous sections.
4.6 Glitches and Influence of Bit Skew

In the previous sections, we have discussed how the output currents are dependent on errors in
some different static values, hence the values given by the settled signal after a code transi-
tion. We have also touched upon the dynamic properties of signal-dependent settling time, etc.
In this section we briefly discuss some different models on the influence of bit skew and
Glitches and Influence of Bit Skew 123
glitches. In the litterature, there are few that have been discussing the influence of glitches and
how they can be modelled [73, 79].
It is important to guarantee the switching instants n ⋅ T u to be as accurate as possible.
Although it is not really applicable for DACs, it can be shown that for a FS sinusoid input, the
SNDR with respect to sampling jitter is in ADCs approximately [14]
SNDR ≈ – 20 ⋅ log10 ( 2π ⋅ f in ⋅ σ T ) dB, (4.169)
where f in is the signal frequency and σ T is the standard deviation of the Gaussian distributed
sampling uncertainty. For DACs, we basically have the same problem, but instead we care
more about the end value after settling, i.e., settling error, as described in the previous sec-
tions.
Instead we are much more concerned with the sampling jitter between different bits. Timing
errors of this kind will add voltage or current spikes to the output signal, i.e., glitches as was
discussed in Chapter 2. The settling behavior will also be affected in a nonlinear way since the
start value of the settling can vary dramatically. The glitches are especially large at major code
transitions as for example
011…11 → 100…00 (4.170)
If the MSB switches faster than the LSBs, we may for a short period of time have the code
111…11 represented. This will for the current-steering DAC generate a glitch with a height
of approximately half scale, i.e., I g ≈ 2 N – 1 ⋅ I u , where I u is the unit current. The duration of
this glitch can be assumed to be T g . Naturally, in a good design the glitch energy ( I g2 ⋅ T b ) or
glitch area ( I g ⋅ T g ) should be kept as low as possible, by for example using segmentation
and proper switching schemes. To investigate the behavior of glitches, we introduce a switch-
ing time uncertainty for bit k as
τ k(X (T n)) (4.171)
where T n = n ⋅ T u and T u is the sampling period. This timing error is dependent on the bit
significance k , the input code, and the time. We can for example model this time period to be
described by a Gaussian distribution with zero mean and standard deviation σ T . This may be
a rough approximation since the timing errors may be to some extent fixed for each bit in the
same way as matching errors, hence during processing mismatch in switch drivers, etc., intro-
duce different delays in the circuit. Further extension is to analyze how the timing uncertainty
is dependent on the voltages applied on the current switches. Assuming NMOS current
switches and PMOS current sources in the current-steering DAC, the gate-source voltage of
the switch would be dependent on the output voltage and from there we could model the time
from cut-off to a conducting region of the switch as a function of the signal and current
through the switch. In [79] a model that is focusing on the electrical behavior of the glitch is
presented. We will however stay at a slightly higher level of abstraction. The timing error τ k
in (4.171) can be both negative and positive. With a positive timing error we understand that
the switch is delayed and with a negative value, the switch changes before the wanted time
instant.
In Fig. 4.27 we show how the time skew can be modeled for the k -th bit. In (a) we find the
ideal (dashed) pulse and the linearized model of the actual pulse (solid) due to timing errors.
In (b) we show the same situation but with a box model. Hence, the error (shaded) is given by
a square wave and not a triangular wave.
bit k bit k
t t
(a) (b)
Figure 4.27 Model of timing uncertainty. The ideal switching signal (dashed) is compared with the
actual signal (solid). In (a) a linearized model and in (b) a box model.
The switching activity in bit k is denoted as

∆b k(T n) = b k(T n) – b k(T n – 1) . (4.172)
If the switching activity is negative, we have that the bit goes from 1 to 0, hence is turned off,
it is positive if the bit goes from 0 to 1. If the switching activity is zero, the bit does not
change. A positive τ k (4.171) together with a positive switching activity implies that we have
a delayed signal and that we should subtract a pulse from the wanted result. A positive τ k
with a negative switching activity implies that we should add a pulse. The same holds for the
case with a negative τ k and positive switching activity. Finally, with a negative τ k and nega-
tive switching activity we should subtract a pulse. Therefore, we define the error pulse (from
Fig. 4.27 (b)) for positive τ k as
 – 1 τ k > 0 T n ≤ t ≤ T n + τ k(X (T n))

(n) 
U k (t) =  1 τ < 0 T + τ ( X (T ) ) ≤ t ≤ T . (4.173)
 k n k n n
 0 else
We can now describe the glitches in the time domain by

∞ N
(n)
G(t) = I u ⋅ ∑ ∑ 2 k – 1 ⋅ ∆bk(T n) ⋅ U k (t ) . (4.174)
n = 0k = 1
We see that the glitches are described by several ( N ) overlapping square-waves with different
durations and amplitudes centered around the ideal sampling instants, T n . The overall result-
ing waveform will then most likely not be given by a square wave. The expression above
depends on the unit current I u , the switching activity, and the time uncertainties and to the
expression, we have not added glitches arising from for example CFT or similar cross cou-
pling.
In Fig. 4.28 we show the simulated output spectra for a 14-bit DAC with FS sinusoid input.
The timing errors are large to illustrate the effect, they have a standard deviation of approxi-
mately 5 per cent of the whole update period. Compare with (2.96) and (2.98) where we for a
14-bit converter would require the glitch width to be in the order of 7.4 ⋅ 10 –7 % and
6.1 ⋅ 10 –3 %, respectively. (The expressions assume maximum glitches and therefore the
Glitches and Influence of Bit Skew 125
extremely low values).
Simulated signal without glitches

0
−40
Power [dB]
−80
−120
0 0.55 1.1
Frequency [MHz]
(a)
Simulated spectrum with glitches Simulated spectrum with glitches
0 0
−40 −40
Power [dB]
Power [dB]
−80 −80
−120 −120
0 0.55 1.1 0 0.55 1.1

(b) (c)
Figure 4.28 Simulated output spectrum for (a) ideal signal, (b) randomly varying glitch model, and (c)
fixed glitch model.
In Fig. 4.28 (a) we find the ideal output spectrum. In (b) we see the resulting output spectrum
when glitches have been included. In this case, the glitches have been selected randomly each
sampling instant, i.e., the timing errors are time and signal independent. Therefore, the noise
floor is drastically increased and reduces the SNDR. Another approach is to assume that the
glitch errors are only dependent on the bit, hence the static mismatch error. For each chip, we
have a fixed set of τ k for k = 1, …, N , hence U k( n )(t) will be equal for all n . In this case, we
will have signal-dependent glitch errors and distortion will arise. In Fig. 4.28 (c) we show the
simulated output spectrum when the timing errors are fixed. Now, we clearly can identify har-
monics that limit the achievable SFDR.
5 Current-Steering D/A
Converters
5.1 Introduction
In this chapter we present work on circuit implementations of different D/A converters. We
discuss how the proposed formulas from the previous chapter relates to the design phase.
Throughout the thesis, we have identified the current-steering DAC as a suitable candidates
for high-speed and high-resolution communication applications. This architecture does not
need any output buffer as for example the switched-capacitor DAC. It will however become
sensitive to finite output impedance. Further, the current-steering DAC can be implemented
with MOS-only components and still reach rather high accuracy. Resistor-string or R–2R lad-
ders are also very fast, but they require high-accuracy on-chip resistors. Although the R–2R
architecture is a current-steering DAC, it will not be further addressed in this chapter. Instead,
we focus on the pure current-steering versions where a number of weighted current sources
are used to form the conversion function. An overview of different layout strategies for the
unit current sources is given in Sec. 5.2. We highlight the advantages and disadvantages with
the different topologies. For some of the topologies there are inhereted good properties for
high performance.
In Sec. 5.3 we discuss some practical design issues. In the previous chapter we found that per-
formance is strongly dependent on e.g. the output impedance of the current sources since the
linearity is degraded. The circuit noise is determined by the DC output current of a current
source and matching is practically determined by the transistor size, i.e., the gate area. The
output impedance is dependent on the DC current and the DC current is dependent on the
transistor size, etc. When increasing the output current with the ambition to improve the SNR,
the output impedance is decreasing and thereby the nonlinearity increase, etc. Therefore, as
always in analog design, we have a delicate relation between design parameters and usually a
trade-off has to be done. Further the influence of clock feedthrough in switches as well as the
on-resistance is crucial. Also the influence of the interconnecting wires must not be neglected,
127
etc.
To further illustrate the current-steering architecture, we present the results from implementa-
tion of wideband CMOS DACs for xDSL applications in Sec. 5.4. We show design trade-offs
and ideas on how to implement the required circuit elements. Measured and simulated results
from the wideband DAC are discussed in Sec. 5.5. Output spectra from single- and multi-tone
measurements are shown. We also compare the results from two similar DACs that have varia-
tions in design of the unit current sources and interconnection wires. We have found that with
a small variation in layout, an SFDR improvement of over 12 dB is achieved.
5.2 Current-Steering DAC Architectures

The current-steering DAC architecture was described in Sec. 3.6.1 and the structure is once
again sketched in Fig. 5.1 for convenience. There is a number of current sources and switches.
Depending on the input code, X , the current from the corresponding sources is directed by the
switches to the output and terminated by an off-chip resistor or I/V converted (and filtered)
using a buffer at the output as shaded in the figure. The output buffer will guarantee a low-
impedance node at the output of the DAC and hence we do not have to worry as much about
the limited output impedance. Instead the matching errors will strongly influence the perfor-
mance. This was also discussed in the previous chapter and as is commonly known, good
matching of the current sources is reuiqred for high performance. Instead of using a current
source with the nominal value M one uses M unit current sources in parallel. We will then
have the same type of edge matching errors for each element. Secondly, we may also use spe-
cial layout techniques, such as interdigitized or common-centroid in order to smooth out the
influence of graded mismatch errors.
bN bN-1 b1
Iout(t)
RL
Figure 5.1 Principle of an N-bit current-steering DAC.
If no buffer amplifier is used at the output, the DAC will be sensitive to the limited output
impedance. As found in Sec. 4.3 the SNDR and SFDR are dependent on the conductance ratio
ρG = GS ⁄ GL , (5.1)
where G S is the output conductance of the unit current source and G L is the load conduc-
tance. Typically, with an output buffer, this will become approximately zero, G L ≈ 0 , due to
Current-Steering DAC Architectures 129
the virtual ground at the input of the amplifier.
To guarantee good matching we need the gate areas of the current sources to be rather large.
We have that the matching is inversely dependent on the gate area of the transistor and the dis-
tance between the transistors that should be matched [68], e.g.,
A
σ (∆I ) = -------β- + A d ⋅ D 2 ,
2
(5.2)
WL
where A β and A d is a process-dependent parameter and D is the distance to another transis-
tor. Hence we want the area WL to go towards infinity and the distance D to go towards zero.
Obviously, this is a contradiction, since one of the main targets is to lay out the current
sources as close to each other as well. The design issue is to find the optimum W and L ,
where the D parameter is a function of the W and L . This is discussed more in the design of
unit current sources in Sec. 5.3.1. Since we will occupy a large area for good matching, the
total area of the DAC will become very large.
To the matching errors and output impedance issues, we also have to add the influence of the
interconnection wires. In the following we discuss some different approaches for laying out
the unit current sources.
5.2.1 Flat and Folded Array Structures

The first, simplest, and perhaps the most naive approach is to lay out the unit current sources
as shown in Fig. 5.2 (a). The MSB current source is formed by taking 2 N – 1 parallel unit cur-
rent sources in one row. The second MSB is formed in the similar way with 2 N – 2 sources
from another row, etc. Each row is interconnected and fed to a current switch. It is obvious
that the array becomes very wide for a higher number of bits. The DAC also becomes sensi-
tive to matching gradients.
IN
IN-1 IN
I2 IK
I1
I1 I2
IK-1
(a) (b)
Figure 5.2 (a) “Flat” and (b) “folded” array layout of unit current sources.
The natural and obvious way to circumvent this is for the MSBs to use more than one row and
for the LSBs to use the same row as illustrated by the “folded” approach in Fig. 5.2 (b). This
also makes the converter less sensitive to linear graded mismatch errors in at least one direc-
tion [78]. To relax the design of interconnection wires, one could for the MSBs also duplicate
the digital logic circuits and for example use one switch for each row and hence several
switches for the same bit operating in parallel.
These approaches, however, are not suitable for higher resolutions, due to the requirements on
parasitic resistance in switches and wires as well as the current source matching.
To make the DAC even less sensitive to matching gradients one should preferrably distribute
the current sources over the array as illustrated in Fig. 5.3 for a 6-bit binary-weighted DAC
with 63 unit current sources. The numbers indicate to which bit the current source is associ-
ated. We assume that the matching errors are approximately given by a plane and the gradi-
ents are rather large, k y = k x = 0.05 and that the distance between the unit current sources is
unity in both directions.
INL for best−fit line

DAC unit current source array 4
6 6 6 6 6 6 6 6 3
6 6 6 6 6 6 6 6 2
6 6 6 6 6 6 6 6 1
INL [LSB]
6 6 6 6 6 6 6 6 0
5 5 5 5 5 5 5 5 −1
5 5 5 5 5 5 5 5 −2
4 4 4 4 4 4 4 4 −3
0 1 2 2 3 3 3 3 −4
10 20 30 40 50 60
Input code
(a) (b)
Figure 5.3 Influence of gradients for a (a) flat layout approach on the (b) INL.
Further we assume that the zero value is at the center of the array. Using the equation from
(4.3) we find that the upper left current source would have the nominal value
I u, 1 = Ĩ u – 3.5 ⋅ k x + 3.5 ⋅ k y (5.3)
and the lower right
I u, 63 = Ĩ u + 3.5 ⋅ k x – 3.5 ⋅ k y , (5.4)
etc. In Fig. 5.3 (b) we discuss how this affects the INL of the DAC, the maximum INL is
approximately 3 LSB. In Fig. 5.4 we show an approach when the current sources have been
laid out in a more random manner. We find that the impact on INL is much lower (b). We have
that the maximum INL is about 0.2 LSB. However, the approach in Fig. 5.4 (a) requires more
complex routing of the interconnecting wires, etc. This will increase the parasitics and noise
levels. Notice that the distribution of the current sources examplified in Fig. 5.4 (a) is not the
optimal one, it has been done by hand. With a computer program, the optimal layout can be
found. Further, we can add cost functions such as the impact on DNL and INL, wire lengths,
selection algorithms, etc.
INL for best−fit line

DAC unit current source array 1
6 4 6 4 6 5 6 5 0.8
0.6
5 6 5 6 4 6 4 6
0.4
6 5 6 5 6 3 6 3
0.2
INL [LSB]
3 6 3 6 5 6 5 6 0
6 2 6 1 6 5 6 5 −0.2
−0.4
5 6 5 6 0 6 2 6
−0.6
6 5 6 5 6 4 6 4
−0.8
4 6 4 6 5 6 5 6 −1
10 20 30 40 50 60
Input code
(a) (b)
Figure 5.4 Influence of gradients for a (a) distributed layout approach on the (b) INL.
5.2.2 Segmented Structures

To reduce the effects of too large currents through the current switches, which implies diffi-
culties with matching and resistance ratios, etc., we can – as mentioned in the previous –
duplicate the digital switching logic for the MSBs and use several switches for the same bit.
This will allow us to use shorter interconnection wires, and a more modular layout, etc.
Another approach, which should be used for higher resolutions, is to segment the MSBs. The
MSBs are encoded from a binary representation into a thermometer code (see Sec. 3.5.2). It is
very difficult to use a full thermometer code representation for all bits in high-resolution con-
verters, since the number of switches and the complexity of the interconnection wires, etc.,
grows exponentionally with increasing number of bits.
In Fig. 5.5 we show an example of segmentation of the most significant bits. The M MSBs
are thermometer coded and the N – M LSBs are binary weighted. With the thermometer code
we have a number of equally large current sources: 2 M – 1 sources with 2 N – M unit current
sources each. The DAC can be laid out more regularly and it becomes simpler to distribute the
sources to minimize the influence of the graded matching errors. We can also use the same
size on the switches for the thermometer-coded bits which further improves matching.
Another major advantage is that with this approach matching enhancement techniques, such
as dynamic randomization, current source calibration, averaging, etc., becomes much simpler.
These techniques are further discussed in Chapter 7.
A fully thermometer-coded DAC guarantees montonicity and minimal glitches. However, for
high resolution this is not feasible and there is a trade-off between the number of bits to seg-
ment and the impact on layout complexity, glitches, mononicity, etc. As we discussed in Sec.
2.4.2 and Sec. 4.6, the glitch energy can roughly be characterized by the number of bits that
switch between two input codes. Functions describing the impact of glitches can be the ones
described in Sec. 4.6, etc. If we use segmentation we introduce more glitches, but with a lower
energy. Further assuming that the width and amplitudes of the glitches is of stochastic nature,
there will be an improvement in SNR in the order of 2 M (Sec. 2.4.2). The simulated normal-
ized SNDR with respect to glitches for a 14-bit DAC is shown in Fig. 5.6. We have applied a
multi-tone signal with some different PAR values. The duration of the glitch pulses have been
Is,2M-1
Is,2M-2
Is,1
I1
I2
IN-M
Figure 5.5 Illurstration of a segmented current source array. The M binary MSBs are encoded into T =
2M–1 thermometer coded bits.
assumed to be Gaussian distributed. We find that up to five or sex segmented bits gives a large
improvement in performance. For higher degree of segmentation, the gain is not as significant.
Not considered in the simulation is the need for more digital circuits and hence higher com-
plexity, power consumption, and induced noise. The design of segmentation circuits is further
discussed in Sec. 5.4.3.
Glitch power for 14−bit multi−tone signal
24
Normalized glitch power [dB]
18
12
1 2 3 4 5 6 7 8 9
Number of segmented bits
Figure 5.6 Estimated glitch power as function of the number of segmented bits in a 14-bit DAC.
In the literature, the 12- or 14-bit DACs with highest performance have five to seven ther-
mometer-coded MSBs [46, 62]. A similar, intuitive approach is to use a multi-segmented
structure [59]. The M MSBs are thermometer coded in one cluster, the K LSBs are kept
binary coded, and the N – M – K intermediate bits are also thermometer coded in another
separate cluster.
5.2.3 Encoded Array Structures

Another popular structure for an intermediate number of bits is the encoded array structure
[49, 59, 63, 90]. Also, in this approach the unit current sources are laid out in an array (or
matrix) as in the previous cases. However, we now add the switches to each unit current
source and create a unit current cell. This cell contains some digital encoding and driving cir-
cuits. By using encoding the binary input into row and column decoding signals we can select
the desired number of sources from the array. This structure is illustrated in Fig. 5.7. Each
current cell, Fig. 5.7 (b), requires three control signals, one for the column ( C ) , one for the
row ( R ) , and one signal for additional column selection ( S ) . The switching signal ( Φ ) is
determinewd by
Φ = S ∨ (R ∧ C) . (5.5)
X
N
Column encoder
C S
R
Row encoder
Iu
F
Iout
Figure 5.7 Unit current source array with decoding circuits.
The selection signals are generated and synchronized with a global clock outside the sensitive
analog array [95]. The array can be laid out regularly and the unit current sources are distrib-
uted as for example the case in Fig. 5.4 (a). We also have the possibility to modify the distri-
bution of the unit current sources for each DAC by reprogramming the switching sequences
[96]. Extending this, dynamic randomization techniques can be used, i.e., the unit cells are
randomly selected and distortion due to matching errors become noise instead. Another good
property is that, instead of using cascoded transistors in the unit current sources (see Sec.
5.3.1), the switch transistor can be used as cascode to improve the output impedance [63, 59].
There are some drawbacks with this architecture. Within the unit current cell a certain amount
of digital logic is needed. This requires distribution of digital power supply lines to each cell.
At the same time we need the three control signals, analog power supply, analog bias voltages,
and a differential output current, i.e., two more wires. This is a total of nine or ten wires
dependent on the choice of current source. To decrease the amount of noise, we want to shield
the analog wires from the digital as much as possible, which will require a large chip area. In
Chapter 7 we discuss some different approaches to modify the DAC so that we can lower the
amount of digital contents within the array.
For DACs with resolutions higher than 8 to 10 bits this technique is somewhat limited due to
the required chip area and complexity of decoding circuits. Hybrid DAC versions use the
array approach for the MSBs and a binary-weighted or thermometer-coded structure for the
LSBs [90].
5.3 Practical Design Considerations

In this section we present some practical design considerations concerning the layout and
choice of circuit elements in a typical current-steering DAC. Especially, we consider the unit
current source and the current switch, but also some of the digital interface circuits.
5.3.1 Unit Current Source

Naturally, the unit current source may be designed in several different ways [46, 51, 97],
PMOS or NMOS, cascoded or not, etc. In Fig. 5.8 we show three versions of the current
source where a single PMOS transistor is used (a) together with one (b) or two cascode (c)
PMOS transistors. It is the source-gate voltage applied on transistor M1 that practically sets
the nominal current through the current source [7]. An ideal current source should have an
infinite output impedance and the cascode transistors are used to increase the output resis-
tance, hence the effects of the nonzero channel length modulation are reduced since the varia-
tions on the drain-source voltage of M1 is decreased. In the examples in Fig. 5.8, all bulks are
connected to the positive power supply. This will slightly decrease the gain of the cascodes,
but the advantage is that the layout becomes somewhat simpler. Using PMOS instead of
NMOS transistors will (for the same transistor sizes) give a lower 1 ⁄ f -noise due to the lower
mobility of holes but a higher thermal noise level.
VG1 VG1 VG1

M1 M1 M1
Iout VG2 VG2

M2 M2
M1
Iout VG3
M3
Iout
(a) (b) (c)

Figure 5.8 Schematic view of PMOS current sources using (a) single transistor and (b) single cas-
code, and (c) double cascode.
In the following we discuss some of the properties of the current sources. We use the PMOS
transistors as example, but the results apply on NMOS transistors as well.
Practical Design Considerations 135
Output impedance
We require a very high output resistance for high performance. In the previous chapter we
found that the SFDR and SNDR are highly dependent on a nonzero conductance ratio. The
output resistance for the sources in Fig. 5.8 (a) through (c) are denoted R a , R b , and R c ,
respectively, and they are approximately given by [7]
1 ( 1 + η 2 ) 2β 2 ( 1 + η 3 ) 2β 3
R a ≈ --------------- , R b ≈ R a ⋅ ---------------------------------- , and R c ≈ R b ⋅ ---------------------------------- . (5.6)
λ1 ⋅ I u λ ⋅ I λ ⋅ I
2 u 3 u
where I u is the DC output current of the source, λ i is the channel length modulation factor,
β i is the transconductance parameter, and η i is a parameter determined by the bulk-source
transconductance of the transistors. The output resistance of the current source is increased by
a factor corresponding to the approximate gain of the cascode transistor. The current, I u , is
mostly set by the specification, e.g., with a 1-V swing over a 50-Ω termination the peak output
current is 20 mA. In a 14-bit DAC, we then get the LSB current as
–3
20 ×10
- ≈ 1.22 µA .
------------------- (5.7)
2 14 – 1
For high output resistance we must guarantee that the transistors are operating in their satura-
tion regions. The output current of the unit current source is then approximately given by [7]
β1 2 µ 0, p C ox W 2
I u ≈ ----- ⋅ V eff = -------------------- ⋅ ----- ⋅ V eff , (5.8)
2 2 L
where β 1 is the transconductance parameter, µ 0, p is the charge mobility, C ox is the capaci-
tance per gate area, W ⁄ L is the transistor’s size aspect ratio, and V eff is the effective gate
voltage. Further, the channel length modulation factor is inversely dependent on the channel
length [7], λ ∼ 1 ⁄ L . Since the current is fixed by the specification, we have that
Ra ∼ L1 . (5.9)
For high resistance we require long channels. For the cascoded current sources, we get
R b ∼ L 1 ⋅ W 2 L 2 and R c ∼ L 1 ⋅ W 2 L 2 ⋅ W 3 ⋅ L 3 , (5.10)
hence for high output resistance we require large cascode transistors.

The current source will have an output pole due to the parasitic capacitances associated with
the transistors. In Fig. 5.9 we show the simulated output impedance for three current sources
as the examples in Fig. 5.8. In the simulations a 0.6- µm CMOS process was used and the
gate widths of all transistors were equal, W = 2 µm , but the channel lengths were
L 1 = 8 µm , L 2 = 2 µm , and L 3 = 1.2 µm . The currents through the current sources are
approximately 1.22 µA.
From Fig. 5.9 we clearly see the output resistance is improved by using cascodes, it is
improved from approximately 300 MΩ to 30 TΩ. Using the results from the models in the
previous chapter (4.90), we have that if the SNDR of the 14-bit converter in the single-ended
case for an FS sinusoid should be higher than say 80 dB we get
Output impedance of current sources
29T Double cascode

Single cascode
Single transistor
104G
6.3G
Impedance [Ω] 292M
0.2 45 16k 1M 1G
Frequency [Hz]
Figure 5.9 Simulated output impedance of three different unit current source configurations.
–9
SNDR ≈ – 6 ( 14 – 0.4 ) – 20 ⋅ log10 ρ G > 80 ⇒ ρ G < 7.94 ×10 . (5.11)
This gives an upper bound on the output conductance as

–8
G S < 2.442 ×10 ⋅ GL , (5.12)
where G L is the load conductance. With a 50-Ω load we get the maximum unit output con-
ductance as
– 10
G S < 1.589 ×10 . (5.13)
This corresponds to an output resistance of

R S > 6.29 GΩ . (5.14)
We see from the simulation results in Fig. 5.9 that this requirement is met for the single- and
double-cascoded current source configurations, but not for the single transistor approach.
However, for higher frequencies the output impedance is decreasing by 20 dB/decade due to
the output poles. At higher frequencies (above 50 kHz), all sources basically have the same
impedance characteristics. Although it is a somewhat rough approach, we can see that the
bound in (5.14) cannot be guaranteed for frequencies above only 630 Ω for the cascoded cur-
rent sources.
These limitations are due to the capacitive parts of the current source and if we assume that
the cascodes’ gains are rather high the dominating capacitances will be the ones found at the
drains closest to the outputs. These are typically the gate-drain overlap capacitance and the
drain-bulk capacitance. The overlap capacitance can be neglected and we have the drain-bulk
capacitance given by [7]
C db ≈ A d ⋅ C jd , (5.15)
where A d = W ⋅ L d is the drain area and C jd is the junction capacitance per drain area. L d is
the drain length. Approximately, we get that the capacitance is linearly dependent on the
width
C db ∼ W . (5.16)
The output poles for the current sources in Fig. 5.8 (a) through (b) can roughly be determined
by combining (5.6), (5.9), (5.10), and (5.16). We get some approximate relations as
1 1 1 1 1 1
ω a ≈ ------------------------ ∼ ------------------ , ω b ≈ ------------------------ ∼ ----- ⋅ ---------- ⋅ ------------
- , and
R a ⋅ C gd, a L 1 ⋅ W 1 R b ⋅ C gd, b L 1 L W 3 ⁄ 2
2 2
1 1 1 1 1 1
ω c ≈ ----------------------- ∼ ----- ⋅ ---------- ⋅ ---------- ⋅ ------------ ⋅ ------------
-. (5.17)
R c ⋅ C gd, c L 1 L L W W
3⁄2
2 3 2 3
From this we have the intuitive result that the larger we make the widths of the transistors the
lower pole. In an implementation, it can be advantegous to choose all transistor widths to be
equal since the layout becomes somewhat simpler. In that case, we end up with the lengths L i
as design parameters. More analysis on the influence of the pole in the unit current source can
be found in e.g. [126].
Another interesting design issue is how the current sources react on variations of the DC sup-
ply voltage and the DC voltage applied at the output of the current source. In Fig. 5.10 we
show the simulated output impedance for the single-cascoded (Fig. 5.8 (b)) current source for
different supply and output voltage levels. In Fig. 5.10 (a) we vary the supply voltage from
2.2 V to 5 V and the output voltage level is held constant at 0.5 V. In Fig. 5.10 (b) we fix the
supply voltage at 5 V and the output voltage is varied from 0 to 1.2 V. The current through the
source is kept nearly constant and equal to 1.22 µA. We find that the output resistance is lin-
early depdent on supply and output voltage variations and hence as expected the impedance is
dependent on the current through the mirror and due to the high output impedance, the
changes are relatively small. From Fig. 5.10 (a) we see for the double cascode current source
that a minimum supply voltage of approximately 3.2 V is required, since otherwise the tran-
sistors work in the linear regions.
Matching
As we have discussed in the previous sections, there are several sources for the matching
errors, i.e., transistor size errors, threshold voltag variations, supply and bias voltages varia-
tions, oxide thickness variations, output voltage variations, etc. The graded matching errors
can be minimized by spreading out the unit current sources as smart as possible. The stochas-
tic matching must be minimized through proper choice of transistor sizes. From studies in the
literature [41, 49] we know that the β - and V T -matching are uncorrelated and that their vari-
ance is inversely proportional to the transistor area, WL and linearly dependent on the dis-
tance between the objects to match. If the different parameters are provided by the process
distributor, we can find a trade-off yielding the minimum error. For example, if we have a
rather simplified formula as
b
σ 2 = a + -------- + c ⋅ W 2 + d ⋅ L 2 + e ⋅ WL , (5.18)
WL
where a, b, c, d, e are the process-dependent parameters. The minimum is found by deriving
(5.18) with respect to the widht and length:
Output resistance vs. supply voltage Output resistance vs. output voltage
Double cascode
100T Single cascode 100T
Single transistor
Output resistance [Ω]
Output resistance [Ω]

1T 1T
1G 1G
Double cascode
10M 10M Single cascode
Single transistor
2 2.5 3 3.5 4 4.5 5 0 0.2 0.4 0.6 0.8 1 1.2
Supply voltage [V] Output DC voltage [V]
(a) (b)
Figure 5.10 Simulated output impedance of the unit current sources as function of the (a) supply volt-
age and (b) output DC voltage level.
∂σ 2 b
--------- = 2c ⋅ W + e ⋅ L – ----------
- = 0 ⇒ 2c ⋅ W 3 L + e ⋅ W 2 L 2 – b = 0 (5.19)
∂W W 2L
and
∂σ 2 b
--------- = 2d ⋅ L + e ⋅ W – ----------2- = 0 ⇒ 2d ⋅ L 3 W + e ⋅ W 2 L 2 – b = 0 . (5.20)
∂L WL
From (5.19) and (5.20) we get for example
W d
2c ⋅ W 3 L = 2d ⋅ L 3 W ⇒ ----- = --- . (5.21)
L c
Typically, we have that the larger transistors we choose, the better matching. However, with
larger widths the output pole will move towards the origin. A natural choice is to choose the
gate length of the source transistor to be large. Further examples on the calculation of opti-
mum sizes can be found in for example [98, 99].
Matching errors similar to those of graded oxide variations and similar may also arise due to
poorly designed interconnection wires [69, 100]. We have that the output resistance and the
output current is dependent on the bias voltage applied on the gate voltage of the source tran-
sistors M1. The voltage is generated by a bias current, which basically is a current mirror and
the reference current through the primary side of the mirror is controlled by a termination
resistance. However, especially for high resolutions, we have to guarantee that very accurate
and equal bias and supply voltages are supplied to all unit current sources. In Fig. 5.11 we
illustrate the effects of voltage loss over for example the supply wire. The wire is modeled as
a number of resistances in series. In a regular layout these resistances are all equally large.
Since we are tapping current through the unit sources, we will have voltage drops along the
supply wire. With the directions used in the figure, we have V DD > V 1 > … > V N . Dependent
on layout style, the currents, I i , are typically determined by a number of parallel unit current
sources. Further on, the current I i , is given by the effective voltage according to (5.8), i.e.,
dependent on the voltage, V i . Therefore, along the wire the currents will become smaller and
smaller. The deviations are also growing quadratically due to the dependency on the effective
voltage.
VDD DR V1 DR V2 DR VL
I1 I2 IL
Ik
Figure 5.11 Model of the voltage supply wire connected to a number of DAC current sources and the
drop of accuracy in the currents.
5.3.2 Current Switches

The current switches can be implemented in several different ways [52, 59, 97], e.g., PMOS,
NMOS, transmission gates, etc. Typical crucial design parameters are the on-resistance and
clock feedthrough (CFT). For high-performance applications we must also guarantee that the
driving circuits for the switch signals are fast and accurate enough. We discuss some of the
switch properties in the following.
On-resistance
In Fig. 5.12 (a) we show the circuit model of the differential switch and how it can be imple-
mented with MOS transistors in (b). The on-resistance needs to be low in order to reduce the
voltage drop over the switch which influences the linearity of the current source. Especially, if
single-transistor current sources are used. For an MOS transistor implementation, this implies
that the size aspect ratio of the transistors needs to be high.
Iin Iin
f f f f
I+ I- I+ I-
(a) (b)
Figure 5.12 Differential current switch as (a) circuit model and (b) MOS transistor implementation.
However, large switches will also induce a large clock feedthrough (CFT) due to the increased
gate capacitance. The lower switch on-resistance, the more transistors should be connected in
parallel, as illustrated in Fig. 5.12 (b). The on-resistance of an MOS transistor in the linear
region is approximately [7]
1
R sw ≈ ---------------------------------------------- , (5.22)
β ⋅ (V φ – V T – V D)
where β is the transconductance parameter of the transistor, V φ is the gate voltage, V T is the
threshold voltage, and V D is the drain voltage. For the example shown in Fig. 5.12, the drain
voltage is equal to the output voltage of the DAC, V D = V out , and V φ is given by the switch-
ing signals, φ, φ , whose amplitudes typically are equal to the supply voltage. From Sec. 4.3.6
we found that if we size the switches so that the LSB will have the highest on-resistance and if
we for bit k use
R sw, 1 = 2 k – 1 ⋅ R sw, k , (5.23)
there will only be a linear gain error. Otherwise, we also get a (small) nonlinear gain error.
The switches also influence the output capacitive parts of the output poles of the converter and
as always we should try to keep the capacitance as low as possible. NMOS transistors can be
used since the charge mobility is higher than for PMOS transistors [7]. Hence a lower on-
resistance and CFT for the same transistor sizes. Using NMOS as switches in a single-well
process implies that there will be an offset in the bulk-source voltage. Therefore, the threshold
voltage, V T , becomes somewhat larger and hence the on-resistance increases.
If PMOS transistors are used as switches for PMOS current sources they may operate in the
saturation region instead of the linear region. If the transistor is in the saturation region and
not in the cut-off region, ( V S – V φ > V T ) , we have
VS – Vφ – VT < VS – VD . (5.24)
The PMOS is conducting as the gate voltage is set to ground, ( V φ = 0 ) . From (5.24) we get
VS > VT > VD . (5.25)
The threshold voltage vary slightly with the process, but there are no major problem to meet
the requirement in (5.25) as long as the supply voltage is reasonably high. In Fig. 5.13 we
show how the switch on-resistance depends on the supply voltage level and the DC output
level. Single-cascoded unit current sources are used and in the example we show the situation
for the LSB. The current through the switch is approximately 1.22 uA. When sweeping the
supply voltage, the DC output is fixed at 0.5 V and when sweeping the output DC level, the
supply voltage is kept constant at 3.3 V. We find that the relation in (5.22) is verified in Fig.
5.13 (a). We also see that the resistance is dependent on the output DC voltage. This will
therefore introduce a slightly non-linear DAC transfer function and it is important that we try
to keep the slope of the curve in Fig. 5.13 (b) as constant as possible.
Using transmission gates as current switches as illustrated in Fig. 5.14 will further reduce the
on-resistance since we have PMOS and NMOS transistors in parallel. The charge feedthrough
will cancel since the PMOS transistor absorbs the charge that the NMOS repels as it goes into
its cut-off region [7]. There are two drawbacks, one is that the layout of the switch becomes
more complex and the risk of introducing parasitics becomes higher. The second is that we
need a special inversed clock phases on the transmission gates. Hence, we need additional
switching signal drivers. Single transistor solutions are usually sufficient.
Output resistance vs. supply voltage Output resistance vs. output voltage
480
900
460
Switch on−resistance [Ω]
Switch on−resistance [Ω]

800
440
700
420
600
500 400
400 380
2.5 3 3.5 4 4.5 5 0 0.2 0.4 0.6 0.8 1 1.2

Supply voltage [V] Output DC voltage [V]
(a) (b)
Figure 5.13 Simulated switch on-impedance as function of the (a) supply voltage and (b) output DC
voltage.
Iin
f f f f
I+ I-
Figure 5.14 Transmission gates used as current switches.
Clock feedthrough (CFT)

In Sec. 2.4.3 we discussed the clock feedthrough (CFT) and we found that it will influence
higher frequencies due to the charge injection on the output signal. Typically, the CFT give
rise to a frequency component at f u ⁄ 2 as well [23].
The CFT arise due to two reasons, one is the overlap capacitance at the drain or gate and the
other is the channel charge [7]. The overlap capacitance is given by
C ov = W ⋅ L ov , (5.26)
where W is the gate width and L ov is the length of the overlapping gate. There will be small
voltage variations at the output due to the changes of the gate voltage. These voltage varia-
tions are given by
1
---------
sC L C ov W ⋅ L ov
∆V ov = ---------------------------- ⋅ maxV φ = ---------------------- ⋅ maxV φ ≈ ------------------ ⋅ V DD , (5.27)
1 1 C L + C ov CL
--------- + -----------
sC L sC ov
where C L » C ov is the load capacitance and we have assumed that the maximum switch volt-
age is equal to the positive supply. Hence, the smaller V φ and C ov the better. The charge
trapped in the channel when the transistor is operating in its linear region is approximately
given by
Q ch = W ⋅ L ⋅ C ox ⋅ V eff , (5.28)
where C ox is the capacitance per unit gate area, V eff ≈ V out is the effective voltage. When the
transistor is turned off/on, half the channel charge will be absorbed to or rejected from the
channel, so called channel charge injection. This will add a small voltage change at the output
as well. We have that
Q ch 1 W ⋅ L ⋅ C ox ⋅ V eff
∆V ch = --------- ⋅ ------ = ----------------------------------------
-. (5.29)
2 CL 2C L
On the output we will then have V out + ∆V ch + ∆V ov . Once again, we find a contradictive
design issue; the larger gate area, W ⋅ L , the larger CFT, but lower R sw .
An approach to reduce the effect of the channel charge is to use so called dummy transistors
[7] as illustrated in Fig. 5.15. Actually the dummy transistor operates as a capacitor which
absorbs the repelled channel charge instead of letting it be transported to the output. Therefore
we need to switch the dummy in counter phase and design it to have half the gate width,
W ⁄ 2 . The operation of transmission gates is basically the same. However, the dummy tran-
sistor is operating as a capacitor and will therefore lower the bandwidth of the converter.
Iin
f f
f f
I+ I-
Figure 5.15 Dummy transistor used in the switch to reduce the effect of channel charge injection.
Switching signals
Since we are switching a current source, we must ensure that the current switch does not
switch the current source completely off. Otherwise, this will force the potential at the output
of the current source to drift towards the power supply voltage as it is switched off. When it
switches on again, the potential difference or voltage drop between the current source output
and the DAC output is large and a glitch is induced. In extreme cases, the current source tran-
sistor may also get into the linear operation region and will then have a much worse output
impedance. To avoid this, we use differential switches, so that the current source always deliv-
ers current. The switching signals also have to be properly matched to reduce the glitches.
Proper switching signals for a differential PMOS and NMOS switch, respectively, are
sketched in Fig. 5.16 (a). The switching signals can be generated by using a set-reset latch
(SR) as shown in Fig. 5.16 (b) and (c). Additional inverting delays (dimmed in the figure) may
be required for even more overlap. A compact transistor implementation [5] is shown in (b). It
is a back-to-back inverter pair with controlling clock and select signals.
f
f f
f
clk clk
f
bk bk
(a) (b)
bk f
f
(c)
Figure 5.16 (a) Wanted switch signals for a differential current switch and (b) and (c) show possible
circuit implementations generating overlapping signals.
Another issue is to keep the rise and fall behavior of the switch signals as equal as possible to
make the switch time independent.
Switch memory
The switches have a memory function due to the capactive elements and the channel charge,
i.e., the speed for the switch to turn on/off is dependent on the previous states of the switch.
For multi-tone signals the signal itself will introduce much of jitter to the switches and this
problem will be minor. We also do not consider the problem to be especially dominating for
the 14-bit wideband applications.
A return-to-zero (R2Z) switching scheme, as is further discussed in Sec. 7.5.3, can be used to
reduce the memory function since the switches are resetted every half clock period.

For the differential current switches proper switching signals must be guaranteed to never turn
off the current source completely. We have previously discussed the influence of glitches and
to reduce them we need to have very strict requirements on the timing between different bits.
A good clock distribution is therefore needed to minimize the skew. Typically, tree structures
where the clock and data signals are fed in the opposite directions [5, 6], etc., is advantegous.
Segmentation circuits
As we have seen in the previous chapters, to allow good matching strategies, reduce glitching,
allow calibration, etc., the segmented DAC architectures should be used. A number of the
most significant bits are thermometer coded, hence a binary to thermometer encoder is
required. This encoder converts the K MSBs of the binary code into the 2 K – 1 bits of the
thermometer code representation according to Table 2.1 on page 29. The design of the
encoder is straightforward. For example, if the number of bits to segment is two, K = 2 , the
output bits are given by
c 3 = b N ∧ b N – 1 , c 2 = b N , and c 1 = b N ∨ b N – 1 , (5.30)
where b N and b N – 1 are the MSBs of the binary input. Due to the propagation delay through
the encoder, the LSBs have to be delayed correspondingly long time. The functions in (5.30)
can be realized by directly implementing the boolean functions, i.e., one OR and one AND
gate. For more bits to segment, this approach is too naive. The number of expressions grow
exponentially and a tree structure should be used instead. The tree structure is an iterative
structure and hence we can implement a K -to- ( 2 K – 1 ) encoder using a ( K – 1 ) -to-
( 2 K – 1 – 1 ) encoder and an additional vector of AND and OR gates. This concept is illus-
trated in Fig. 5.17. The outputs from the lower-bit encoder are fed to 2 K – 1 – 1 AND and OR
gates together with the more significant bit, b K . The depth of the tree is K – 1 . The structure
can be pipelined by adding the proper number of delays in each layer (or some proper layers)
of the tree. All outputs are aligned with eachother and the LSBs with a register and then fed to
driving circuits for the current switches.
bk+1 bk b2 b1
(k+1)-to-(2k+1-1)
binary-to-thermometer
encoder
k-to-(2k-1)
bk+1 binary-to-
thermometer
encoder
2k-1 2k-1
2k-1 1 2k-1
Figure 5.17 Iterative implementation of a binary-to-thermometer encoder. Note that there is 2 K – 1 – 1

AND and OR gates in parallel.
We realize that the size of the digital contents of the DAC increases rapidly, however, due to
technology scaling, the relative size of the analog parts will become larger and larger. We still
require rather large transistors in the unit current sources to achieve good matching and a high
output impedance. In DACs where the number of bits to segment is high, we want to imple-
ment the encoder as efficiently as possible. As is illustrated in Fig. 5.18 it is also possible to
realize the AND-OR pairs in the ( K – 1 ) -th layer using 2-2 multiplexers where the control bit
is given by bit b K . The multiplexers can be realized with transmission gates or MOS transis-
tors only. Then we also need buffers to generate robust voltage levels at the outputs of each
layer. Instead of using inverters, we can utilize the delay elements that may have been added
for pipelining. Notice from Fig. 5.18 (b) that an additional dummy ‘0’ must be added to the
input for the 2-2 mux approach.
Other techniques to generate the thermometer code are described in Sec. 7.4.
b0 b1
b0 b1 s1
s1
s2
s2
s3 s3
0
s4
(a) (b) (c)

Figure 5.18 Example of a 2-to-3 encoder with AND-OR pair (a). Same encoder implemented by (b) 2-
2 multiplexers. (c) Pass-transistor implementation of the 2-2 multiplexer.
5.3.4 Mixed-Signal Design

In mixed analog/digital design, disturbances from the digital to the analog part (or vice versa)
spread along supply lines and the substrate [7, 8, 13]. As was discussed in Sec. 1.1.3 the sub-
strate coupling may be strong. It is therefore necessary to do careful designs with proper
shielding, which can be done in several different ways, i.e., guard rings, grounding, etc. In
Fig. 5.19 we show an example of shielding an analog block by using guard rings. The guard
rings are typically implemented by N and P diffusion. These diffusions are connected to a
quiet analog ground or common-mode voltage. It is important that the layout of the guard
rings is symmetrical so that the shielding is equal for the analog components.
Analog Digital
Analog Digital
Figure 5.19 Shielding of sensitive analog blocks by using guard rings.
The shielding techniques differ for low-ohmic and high-ohmic substrates. For high-ohmic
substrates the noise tend to spread in a horizontal direction and guarding with diffusion rings
is effective. For low-ohmic substrates the noise spread in the vertical direction. This implies
that especially for higher frequencies the noise will go down to the bottom-end of the sub-
strate to the back-plane die contact. From there the noise is then distributed over the whole
substrate.
The capacitive coupling between the output current and other sensitive wires and the substrate
can be reduced with shielding of the wires. Typically, we encapsulate the wires within ground
wires as illustrated in Fig. 5.20 (a). (The metal wires are separated by an oxide layer not dis-
played in the figures). The routing will require a larger chip area. Further, if a positive doped
substrate is used, we can use an n-well layer, i.e., n-doped substrate, underneath the wires in
order to further decouple the wires from the p-substrate.
At board level it is also necessary to shield and separate the analog and digital pins. This is
illustrated in Fig. 5.21 where the analog pins should be separated from the digital as far as
possible. Grounding pins inbetween are used as shielding. For this purpose a quite ground
should be used, i.e., we should never use the digital ground since it contains much noise from
the switching activity of the digital circuits.
Signal
Vias
N+
Ground Signal Ground
(a) (b)
Figure 5.20 Shielding of sensitive analog signal wires (a) by using ground wires and (b) also using n-
doped substrate layer in the p-substrate underneath the wires.
Digital
GND GND
Analog
Figure 5.21 Separation of analog and digital pins at the board level.
CMOS Current-Steering DACs for VDSL Applications 147
5.4 CMOS Current-Steering DACs for VDSL Applications

In this section we give a brief overview of the design of some DACs for DSL applications.
The resolution of the converters range from 10 to 14 bits. The number of segmented bits range
from 4 to 7. The supply voltages range from 2.5 to 5 V. To meet the VDSL specification, the
clock frequencies range up to 88.32 MHz. The peak output currents range from 10 to 20 mA.
The dual outputs are terminated over 50-Ω loads and the output voltages are fed to a trans-
former generating the differential output. The processes used are 0.25-, 0.35- and 0.60-µm
CMOS from UMC, AMS, and Ericsson, respectively.
As a comparison, we describe the differences in implementation of two DACs, where the
design of the current sources and interconnection wires differ slightly. Measurement results
and conclusions are presented in Sec. 5.5. It is found that an improvement of approximately
12 dB at lower frequencies was achieved.
Some of the behavioral-level models from the previous chapter were used when designing the
building blocks of the DACs. With the knowledge of how the output current affects output
impedance and noise, lets us choose proper values on transistor sizes, etc. However, no pro-
cess information on matching characteristics of the different processes was available.
The design of the DACs is divided into the digital parts, analog parts, and the current
switches. These different blocks are discussed in the following. In Table 5.1 on page 152 we
summarize the data of some of the implemented chips.
5.4.1 Current Sources and Bias

The layout style of the unit current sources is the flat and folded array structures as discussed
in Sec. 5.2.1. For the k -th LSB, 2 k – 1 unit current sources from the array are connected
together and their output is fed to the current switch controlled by the k -th bit. When seg-
menting the K MSBs in the 14-bit DAC, they will turn into a set of bits controlling 2 K – 1
equally large sets of unit current sources. Each of these sets contain 2 N – K unit current
sources. The rows of unit current sources for the segmented MSBs were interdigitized to
reduce the effect of graded matching errors as illustrated by Fig. 5.4.
The unit current sources have been implemented with both NMOS, and PMOS transistors and
with both single- and double-cascode transistors. In implementations with a lower supply
voltage (< 3.3 V) only single-cascoded transistors were used. For the PMOS current sources,
NMOS switches were used for higher speed and for the NMOS current sources, we have used
NMOS switches as well. These are further discussed in Sec. 5.3.2.
The typical layout of a current source is shown in Fig. 5.22. In (a) there is a single-cascode
and in (b) there is a double cascode. All transistors (M1, M2, M3) in the current source are
designed to have the same gate widths. This simplifies the layout and especially the intercon-
nection of all gates with the bias network. In the example shown in the figure, the width is
W = 2 µm , and the lengths are L 1 = 8 µm , L 2 = 2 µm , and L 3 = 1.2 µm .
We found from the simulation results in Fig. 5.9 that for frequencies above approximately
60 kHz we find that there is no improvement by using cascodes. The design criterion is there-
fore set by the output resistance (at DC) where we want to meet 14 bits of resolution. Obvi-
ously, to meet an exact 14-bit resolution we would require an infinite output resistance if the
number of input bits is 14. Instead, we use the result from (5.14) where we found that in the
single-ended case, for an 80-dB SNDR, i.e., ENOB = 13, the resistance must be R S > 6 GΩ .
VDD
VDD
M1
M1
Vsrc
Vsrc
M2 Vcasc1
M2 Vcasc1
M3 Vcasc2
Iout
Iout
(a) (b)
Figure 5.22 Layout view of a (a) double-cascoded and (b) single-cascoded PMOS unit current source.
For a 13.5-bit resolution, we require that R S > 8.5 GΩ .

Once again, we see from the simulation results in Fig. 5.9 that the 13.5-dB resolution is
roughly fulfilled up to 50 kHz.
Bias and supply network

For the biasing of the transistors in the unit current sources current mirror structures were
used as illustrated in Fig. 5.23 (a). The primary current of the current mirror is terminated off-
chip by a potentiometer. In the designs this bias current is in the order of a few mA. For the
lower-voltage DACs a wide-swing current mirror as illustrated in Fig. 5.23 (b) was used. An
additional off-chip voltage was used to control the gates of the cascodes. The mirror rates was
512 to 1 and 1024 to 1. The bias circuits in Fig. 5.23 are not designed to handle temperature
variations. For this purpose, we should use bandgap references or similar temperature stabiliz-
ing circuits [7, 8].
A stable supply voltage for all unit current sources must be guaranteed and therefore a power
supply plane is covering the whole array of sources. A higher metal layer has been used to not
influence the matching of the sources too much [71].
Matching considerations
There were no process information available on parameters determining the variation of sto-
chastic matching errors as described by e.g. (4.13) and (5.2). The edge matching was
improved by using dummy elements (dummy unit current sources) at the edges of the array.
The unit current sources were also placed as densely as possible. To improve V T -matching
substrate contacts were placed near each unit current source. The segmented MSBs were
interdigitized to reduce the effect of graded matching errors. The array of unit current sources
is surrounded by a double guard ring, e.g., both n- and p-diffusion contacts.
CMOS Current-Steering DACs for VDSL Applications 149
DAC
current Off-chip
sources voltage
Iu DAC
current
Iu sources
Off-chip
Off-chip resistor
resistor
,
(a) (b)
Figure 5.23 (a) Cascoded and (b) wideswing PMOS current mirror bias circuits.
5.4.2 Current Switches

In order to make sure that the current source never turns off completely we use differential (or
dual) current switches and we require proper overlapping switching signals. The signal path
must be balanced. The layout of a differential current switch for the LSBs is shown in Fig.
5.24, where we have chosen to use one of eight NMOS transistors in parallel as switch transis-
tor for each channel. To achieve equal capacitive load for all switches, i.e., to have an equal
delay for all bits and hence lower skew, the number of transistors (eight in this example) in the
switches is the same for all bits. To keep a progressive sizing of the switches, some of the
transistors are shorted for the LSBs. For the MSBs the transistors that are shorted for the
LSBs are active.
A shielding ground plane around all switches is used together with a guard ring (the complete
ring is not shown in the figure). The on-resistance was simulated and shown in Fig. 5.13 and it
varies only slightly for the different DAC implementations.
One implementation included dummy switches (Sec. 5.3.2) to reduce the charge injection or
the CFT. The effect of using these was not noticable, since other parameters were limiting the
measured performance.

The digital circuits in the DACs were implemented in a straightforward way. The lower-order
segmentation circuit, i.e., 4-to-15 binary-to-thermometer encoder, was constructed by realiz-
ing the boolean expressions that describe the 15 outputs. Subexpression sharing was used to
reduce the number of logic gates in the encoder. The gates were implemented with unclocked,
static CMOS circuits. The total delay through this encoder is given by four gates and inverting
buffers at the output. This delay is short enough for an 80 MHz application. The LSBs were
delayed by an inverter chain and finally aligned with the MSBs by a register. A tree-formed
clock distribution with tapering factor of three was used to guarantee a small clock skew. In a
0.35-µm CMOS process this encoder occupies a chip area of 60 × 80 µm .
The 6-to-63 binary-to-thermometer encoder was implemented with true single-phase clock-
Ground
φ +
Iout
Iin
–
Iout
φ
Figure 5.24 Layout view of a differential current switch for the LSBs.
ing (TSPC) logic. The tree was pipelined to ensure a high clock frequency. In a 0.25-µm
CMOS process, this encoder occupies a chip area of 1.1 × 0.165 mm2.
The circuits generating overlapping switch signals had a structure as shown in Fig. 5.16 (c).
For PMOS switches we replace the NAND gates with NOR gates to compensate for the oppo-
site polarity.
5.4.4 Chip Implementations

The layouts of the DACs are all similar with some exceptions. In Fig. 5.25 we show a die pho-
tograph of one of the chips (This is DAC A in Table 5.1). Since it was designed as a test chip
the digital circuits were placed apart from the unit current source array. A better implementa-
tion would be to rotate the digital circuits and put the closer to the current source array. Then
we get much shorter interconnection wires which reduces the parasitic resistance.
These types of changes were done in some of the other DACs as the example in Fig. 5.26
shows. (This is DAC E in Table 5.1). It has a larger digital contents due to the 6-to-63 binary-
to-thermometer encoding circuit.
In Table 5.1 we summarize some of the implemented Nyquist-rate DACs. The data on the unit
current sources and the switches is also included in the table. Further, we find the measured
SFDR for some different signal and clock frequencies. More on these results is discussed in
the following section.
5.5 Measurement Results

In this section some measured results are shown and concluded. Some results are summarized
in Table 5.1 on page 152. A comparison study is also given where the measured, simulated,
and calculated results are compared. DAC A and B are of the same generation. DAC C is from
the second generation, DAC D third generation, and DAC E is the fourth generation. Two
DACs of different generations, DAC A/B and C, are compared and the improvement in mea-
sured SFDR is discussed.
Measurement Results 151
Encoder
Current
source array
Figure 5.25 Chip photograph of the 14-bit current-steering 0.60-µm CMOS DAC.
Encoder
Current
source array
Figure 5.26 Chip photograph of the 12-bit current-steering 0.25-µm CMOS DAC.
DAC A DAC B DAC C DAC D DAC E

Supply voltage [V] 3-5 3-5 3-5 3-5 2.7
Core chip area [mm2] 4 4 4 4 1.1

Number of bits 10 - 14 10 - 14 14 14 12
Peak output current [mA] 12 - 20 12 - 20 12 - 20 12 - 20 12
CMOS process [µm] 0.60 0.60 0.60 0.35 0.25
Number of segmented
4 4 4 4 6
MSBs
single double double single single
Current source
cascode cascode cascode cascode cascode
implementation
PMOS PMOS PMOS PMOS NMOS
Table 5.1. Data summary of some implemented DACs.
5.5.1 Measurement Setup and Techniques

Naturally, there are several different ways of measuring the performance of the DACs. How-
ever, since we are measuring the outputs of high-speed and high-resolution converters, a suit-
able way is to use an input data generator (pattern generator) together with a low-jitter clock
generator and with a spectrum analyzer and a high-bandwidth oscilloscope we measure the
single-ended and/or differential outputs. The same principles as were used for the simulations
of the converters. Still a proper input signal has to be guaranteed to be able to analyze the out-
put signal correctly.
Another setup that has also been used in this work is based on PC-controlled measurement
boards, Ballyneuy and Ballyderl, which has been developed for Ericsson Microelectronics AB
in Linköping. The boards was designed by Nallatech, inc., UK [101]. In Fig. 5.27 we show
the concept of this idea. With Matlab the DAC input signal is generated and the vectors are
stored in a memory on the Ballydell PC board. The vectors are then looped and sent to the
DAC. The DAC output is observed by a GPIB controlled spectrum analyzer and the measured
data can be sent to the computer. We can also feed the DAC output to a high-speed, high-reso-
lution ADC. For our purposes, a 14-bit 66 MHz ADC from Analog Devices, inc., AD6644
[102], was used. Naturally, this reference converter has to have higher resolution than the
DAC under test and their performance behavior must be known to be able to analyze the result
from the converter under test. Otherwise, we may not be too sure about the error sources in
the measurement chain. To perform DNL or INL measurements of a 14-bit DAC (with
2 14 = 16384 amplitude levels) we measure the settled output values to get a picture of the
distribution of matching errors on the different bits. For communications purpose, we mostly
only care about the SFDR, SNDR, and MTPR.
Test signal generation

For full-scale single-tone measurements, an update frequency that is relatively prime with the
signal frequency is used to guarantee that all codes are used in a nonsymmetric way. Other-
wise, all information about the converter’s performance is not fully extracted. Using this
prime relation also ensures that the distortion terms are not folded back onto and interfering
Supply
generators
Reference Oscillo-
ADC scope
PC Ballyderl
boards
DAC Spectrum
Software GPIB under test I / V analyzer
out out
controller controller
Pattern
generator
Figure 5.27 View of a measurement system.
with other frequency components and causing problems in the measurement. For dual-tone
measurements the signal frequencies are also chosen to be relatively prime, and they are rela-
tively prime with respect to the sampling frequency. For multi-tone measurements we apply a
number of tones with frequencies at multiples of a fundamental frequency according to a
DMT signalling scheme.
The input test pattern has to be long and accurate enough, since small irregularities in the
input signal give rise to severe unwanted behavior. Clipping of the DAC input signal will
affect the output spectrum as the example of a 14-bit DAC illustrates in Fig. 5.28. In (a) we
show the spectrum of the unclipped signal and in (b) we find the spectrum for the signal
clipped at 99.9 % of its maximum and minimum values, the SFDR is limited to 80 dB and the
SNDR is 70 dB (11 bits). Clipping at 99.9% of its maximum value corresponds to a loss of
approximately 16 LSBs (4 bits). It is however very simple to guarantee that the signal is not
clipping for a single-tone input, but we have to be more careful when using multi-tone signals.
For multi-tone signals we have the peak-to-average ratio (PAR) as a measure on clipping
probability. The influence of different PAR values was discussed in Chapter 1 and Chapter 2.
Also, applying a signal with high PAR on a DAC will give rise to more distortion due to large
amplitude changes of the signal that makes dynamic errors more obvious. Further, we may
have higher distortion for higher amplitude levels applied to the analog components that have
worse linearity at their boundaries.
An input signal that has a slightly irregular periodic behavior will also give rise to distortion
or increased noise. In Fig. 5.28 (c) we show the simulated ideal spectrum of a single-tone
input to a 14-bit DAC. In (b) we show the spectrum when only one sample of the whole
period consisting of 1024 samples has been left out. We see that the signal peak is spread out
due to the jitter in the signal vector.
Ideal 14−bit signal

0
−30
PSD [dB/Hz]
−60
−90
0 0.25 0.5
(a)
Clipped 14−bit signal Clipped 14−bit signal
0 0
−30 −30
PSD [dB/Hz]
PSD [dB/Hz]
−60 −60
−90 −90
0 0.25 0.5 0 0.25 0.5

(b) (c)
Figure 5.28 Output amplitude spectra from a 14-bit DAC with (a) ideal input signal, (b) clipped signal
at 99.9% of its maximum value, and (c) repeated signal but with its period truncated.
5.5.2 Measured Results

When presenting the measured results in this section we refer to the DACs A, through D in
Table 5.1 on page 152. We show the measured differential and single-ended output spectra.
In Fig. 5.29 (a) we find the measured differential output spectrum for DAC A. The signal is a
FS single-tone and the supply voltage is 3.3 V. The signal frequency is approximately
3.43 MHz and the update frequency is 20 MHz. It is found that the third harmonic is the one
setting the SFDR to 48 dB. In Fig. 5.29 (b) we show the measured dual-tone differential out-
put for DAC B. The signal frequencies are approximately 3.43 MHz ( f 1 ) and 3.51 MHz
( f 2 ) and the each tone is half-scale. The supply voltage is 5 V and the update frequency
20 MHz. The harmonic distortion HD 2 ≈ 62 dB and the intermodulation distortion IMD 2, 1 ,
given by 2 f 1 + f 2 , is 50 dB and IMD 2, –1 ≈ 54 dB. From the measured results above, we see
that the distortion is equal for both the single- and double cascoded cases. This is due to the
low-frequency pole at the output of the current sources. As the simulation results in Fig. 5.9
show, all current sources behave equally at frequencies above 60 kHz.
(a) (b)
Figure 5.29 Measured differential output spectra from (a) DAC A and (b) DAC B.
Single-ended vs. differential outputs

In Fig. 5.30 we show the measured output spectra for FS single-tone inputs to DAC C. In (a)
we find the single-ended output and in (b) the differential output. Clearly we see that the sec-
ond harmonic has been drastically reduced when the differential signal is considered. The
SFDR is in the single-ended case determined by the second harmonic and in the differential
case by the third harmonic.
The SFDR vs. update frequency for the single- and double-cascoded 14-bit DACs (DAC A
and B) is shown in Fig. 5.30 (a) and (b), respectively. The measured results from both 3.3-V
and 5-V digital and analog supplies are shown. The SUFR is approximately 0.18 and the
SFDR is decreasing from approximately 49 dB to 41 dB in all cases shown. From these
results, we find that the performance is not changing dramatically between the 5-V and 3.3-V
supply operation. This is due to the fact that the output impedance is not increasing dramati-
cally with the increase supply voltage. As we see from Fig. 5.10 (a) the impedance is increas-
ing from 11 to 28 TΩ. This is however for a fixed current through the current mirror. For our
case, the current through the DAC is increased with increased supply voltage due to the bias
configurations shown in Fig. 5.23. This will decrease the output resistance slightly and hence
the net result is an output impedance that is slowly varying with the supply voltage.
Comparison of two generation DACs

In Fig. 5.31 we show the measured differential SFDR for DAC C. The input is FS single-tone.
We find that there is an improvement in performance compared to the previous designs (DAC
A and B). For example; at 20 MHz update frequency and 3.6 MHz signal frequency the SFDR
is improved by approximately 10 or 12 dB. In Fig. 5.32 we show another plot showing the
SFDR (solid) for the newer DAC C as function of the clock frequency for some different
SUFR (compare with Fig. 5.30). In the figure, we have also included the interpolated (dashed)
measurement results from the older DACs (A and B). We see that the improvement in SFDR
is approximately 12 downto 6 dB with higher clock frequencies.
The two DAC generations differ in such ways that the layouts of the unit current sources are
slightly different and that the parasitic impedance in interconnection wires have been reduced.
Measured SFDR vs. update frequency (DAC A) Measured SFDR vs. update frequency (DAC B)
3.3 V 3.3 V
50 5V 50 5V
48 48
SFDR [dB]
SFDR [dB]
46 46
44 44
42 42
40 40
5 10 25 50 5 10 25 50
Update frequency [MHz] Update frequency [MHz]
(a) (b)
Figure 5.30 Measured SFDR for different update frequencies. The results for DAC A is shown in (a)
and for DAC B in (b). The supply voltages are 3.3 and 5 V.
Measured SFDR vs. SUFR for DAC C

80
4MHz
10MHz
70 2MHz
20MHz
SFDR [dBc]
40MHz
60
100MHz
50
40
0.05 0.13 0.43

Signal to update frequency ratio (SUFR)
Figure 5.31 Measured SFDR for DAC C as function of the signal and update frequency.
A partial plot of the unit current sources is shown in Fig. 5.33. In (a) we find a part of the ver-
sion used in DAC A/B. The internal nodes of the current sources are interconnected. The vias
connecting the sources of the transistors are placed on top of the M1 gates. In the version used
in DAC C, Fig. 5.33 (b), the interconnections were removed and the output capacitance of the
sources are reduced. This increases the output pole and increases the resolution bandwidth of
the DAC. The power supply connections are removed from the gate of M1 which improves
the matching since the standard deviation of the stochastic matching is reduced [71]. Wires
from the current sources to the switches and output were made wider and shorter. This
reduces the voltage drop along the wire and improves the matching between the sources of
different parts in the array.
Measured SFDR vs. clock frequency. DAC A and C.
SUFR = 0.03
SUFR = 0.06
70
SFDR [dB]
DAC C
60 SUFR = 0.18
SFD
50 R Im
prov
eme
SUFR = 0.18 nt
40 DAC A
5 12.5 25 50 100
Update frequency [MHz]
Figure 5.32 Comparison of the measured SFDR from DAC A and C.
VDD routing
moved away
VDD routing from gates
Inter-
connection No inter-
wires connection
wires
Wider
output
wires
(a) (b)
Figure 5.33 Part of current source array for the (a) second and (b) third generation DAC with double
cascode current sources.
5.5.3 Measured, Calculated, and Simulated Results

In this section we will compare some of the simulated, measured, and calculated results. To
illustrate some of the models from Chapter 4, we compare simulated with measured results.
Particularly, we use the DAC A/B and C converters as reference converters. The parameters
determining output poles and parasitics have been found through extraction in the design
tools. Some of these parameters were also overviewed in Table 5.1 where we showed the sim-
ulated paramters. The average matching error has been estimated or partially identified
through the measurement results. These measured results can be compared to the simulated
ones shown in Chapter 4. We identify the second tone to be determined by the limited output
impedance and the third tone to be given by matching errors and similar dynamic phenomena.
General considerations
Consider the measured single-ended results of DAC A and B shown in Fig. 5.34. The input
signal AC level has been varied from –18 to 0 dBFS. The DC value is kept constant. In (a) we
find the measured power of the 1st, 2nd, and 3rd harmonics. In (b) we find the measured har-
monic distortions, HD 2 and HD 3 . We see that with a higher signal power HD 2 increases and
HD 3 is approximately constant. The HD 2 is increasing by approximately 6 dB for each dou-
bling of the signal amplitude. From this result, we also see that the SFDR is decreasing with
an increasing input amplitude.
Measured harmonics power for different input levels Measured harmonic distortion for different input levels
−50
HD2
−10 HD3
1st −55
−30 2nd
3rd
Power [dBm]
Power [dB]
−50 −60
−70
−65
−90
−70
−15 −9 −3 −15 −9 −3
Input AC power [dBFS] Input AC power [dBFS]
(a) (b)
Figure 5.34 (a) Measured power in the fundamental, 2nd, and 3rd harmonics vs. signal power for a 14-
bit DAC and in (b) derived harmonic distortion from the results in (a).
In Fig. 5.35 we show the single-ended output spectrum the DAC C converter. The update fre-
quency is 25 MHz and the signal frequency is approximately 670 kHz. The load resistance is
50 Ω. The input signal amplitude is –15 dBFS, hence for a 14-bit DAC, we get
1 2 14 – 1
X AC = ---------- ⋅ ---------------- ≈ 1450 . (5.31)
4 2 2
The distortion with respect to the 2nd harmonic, HD 2 , is approximately 59 dB and for the 3rd
harmonic, HD 3 , we have 57 dB. The SFDR is also given by the third harmonic, since there is
no other spuriuous tone within the Nyquist range that is stronger than these harmonics. The
measurements have also shown HD 2 = 65 dB and HD 3 = 74 dBc at clock frequencies
around 5 MHz and signal levels at –6 dBFS. These results – as shown in previous figures –
also indicate the impact of the dynamic properties, which degrades the performance with
higher frequencies.
Output impedance
From circuit- and layout-level investigations we have identified parasitic resistances of
approximately 400 Ω from switches and wires. Using the values on the harmonic distortion
found in the measurements and the formulas from Chapter 4, we get for example for interme-
Measured Output Spectrum. 14b DAC.
−10
−20 RBW = 3kHz

VBW = 1kHz
F = 670kHz
−30 sig
Fclk = 25MHz
−40 SFDR = 57dBc
Power [dBm]
Amp. = −15dBFS
−50
−60
−70
−80
−90
−100
0 2 4 6 8 10 12
Frequency [MHz]
Figure 5.35 (a) Measured output spectrum for a 14-bit DAC. Update frequency is 25 MHz and signal
frequency 670 kHz. The input amplitude level is –15 dBFS.
diate sizes of the output impedance
2
SFDR ≈ 20 ⋅ log10 --------------------- (5.32)
ρ G ⋅ X AC
For the 5-MHz measurement result ( HD 2 = SFDR = 65 dB ) and with the AC amplitude
level of approximately 4096 (–6 dBFS) from we get the approximate output impedance as
65
(5) 1 ------
Z unit = --- ⋅ 50 ⋅ 4096 ⋅ 10 20 ≈ 182 MΩ . (5.33)
2
For the 25-MHz measurement result we get
59
( 25 ) 1 ------
Z unit = --- ⋅ 50 ⋅ 1450 ⋅ 10 20 ≈ 30 MΩ . (5.34)
2
Comparing the two results in (5.33) and (5.34) also indicates the effect of varying sampling
frequency and amplitude levels. Consider also the compared results shown in Fig. 4.17 where
we see the drop of the SFDR with increasing frequencies.
Device matching
To estimate the size of the matching error, we have considered the differential outputs in order
to minimize the influence of the limited output impedance. We also use the derived formulas
from Sec. 4.5 where we investigate how the matching error is influenced by different ampli-
tude levels, etc.
From the different measurement results we identify a stochastic matching error to be approxi-
mately σ u ≈ 5 %. For this large number, we have also included approximations of the influ-
ence of for example the graded errors and edge matching. Therefore, we end up with a pretty
large number.
Measurement conclusions
In Fig. 5.36 we show the simulated single-ended output spectrum of a 14-bit converter with
the four MSBs segmented. The output impedance of each unit current source is approximately
60 GΩ and the capacitance associated with each unit source was approximately 20 fF. The
load resistance is 50 Ω and the parasitic resistance for each one of the segmented MSBs is in
the order of 400 Ω. The load and parasitic capacitance is in the order of more than 50 pF. The
update frequency is 25 MHz and the signal frequency is 670 kHz. Finally, the amplitude level
is –15 dBFS.
Simulated Output Spectrum. 14b DAC.
−10
Fsig = 670kHz
−20
Fclk = 25MHz
−30 SFDR = 56dB

Amp = −15dBFS
−40
Power [dBm]
−50
−60
−70
−80
−90
−100
0 2 4 6 8 10 12
Frequency [MHz]
Figure 5.36 Simulated output spectrum for a 14-bit DAC with similar conditions as used for the mea-
sured DAC result in Fig. 5.35.
The simulated spectrum can now be compared with the measured spectrum in Fig. 5.35. The
performance of the converter may be predicted using Matlab simulations. We find that that the
spectra behave similarly and the second and third tones are at the same levels below the fun-
damental. We also see some of the other spurious tones correspond to eachother, such as for
example the fifth tone.
It should be mentioned that the matching errors have been applied as random errors and hence
in the spectrum we only see the result for a single batch. Secondly, we have used the approxi-
mate formulas for the estimation of the output impedance and assumed that the entire con-
verter is binary coded. This is not the case, since we have four of the MSBs thermometer
coded. This will, as mentioned previously, also influence the second harmonic and not only
the third harmonic as derived in Chapter 4.
6 Oversampling D/A
Converters
6.1 Introduction
The oversampling D/A converter (OSDAC) is typically used when high linearity is preferred
over high bandwidth. Traditionally, OSDACs are used in audio DACs since there the band-
width is relatively low and a high linearity is required [27, 29]. One of the advantages of using
OSDACs is that the major part of the converter is implemented with digital circuits. There-
fore, we can avoid many of the analog errors. With technology scaling the digital circuits can
be kept at a relatively small chip area and power consumption and hence the OSDACs can
also be used in applications were the bandwidth reaches the MHz range or even higher. We
can allow oversampling ratios in the order of 32, 64, or even more for, for example, ADSL
applications where the signal bandwidth is approximately 1.104 MHz. Some of the digital cir-
cuits then have to operate at frequencies around 71 and 141 MHz, respectively. The increased
update frequency allows us to design the analog image-rejection filters with very low com-
plexity. Large requirements are however set on the switch signal generators and e.g. the cur-
rent switches due to the high sampling frequency.
The operation and properties of the oversampling converters in general were presented in
Chapter 3. In Sec. 6.2 we take a somewhat closer look at the different building blocks. In Sec.
6.3 we present the simulated behavior of some of the building blocks in the oversampling D/A
converter. We overview for example some filter orders and modulator orders and their behav-
ior. In Sec. 6.4 we describe a 3.3-V 14-bit current-steering OSDAC with a 5th-order modula-
tor for DMT-ADSL.
6.2 OSDAC Building Blocks

The operation and use of the oversampling digital-to-analog converter (OSDAC) was pre-
sented in Chapter 3 and in Fig. 6.1 we repeat the block view of a general OSDAC. We have
the interpolator taking the input signal which is bandlimited to f N = f u ⁄ 2 and increases the
161
update frequency by OSR times, and we get the new update frequency of f O, u = OSR ⋅ f u .
The interpolation filters attenuate images due to the interpolation operation and in the ideal
case, they bandlimit the signal at the output of the interpolator to f N . The modulator reduces
the number of bits in the signal. Instead the signal is represented through pulse code modula-
tion (PCM). The reduction of bits is done through truncation where the truncated bits (the
truncation error) or the modulator’s output is used in a feedback loop. The M -bit modulator
output is fed to the DAC, which is a Nyquist-rate DAC with its input signal bandlimited to
1 ⁄ OSR of the update frequency. With a lower-bit DAC, we have less analog components to
lay out and special matching improvement techniques can be used since the parasitics from
interconnection wires become smaller. If M = 1 we have a one-bit modulator and in this
case, the DAC can be implemented by a so-called semi-digital FIR filter which takes the bit
stream and lowpass filters it. Thereby, the requirements on the analog image-rejection filter
can be significantly reduced.
x(n) A(t)
IPF SD DAC LP
N M
Figure 6.1 Generalized OSDAC architecture including interpolator, modulator, DAC, and analog LP
filter.
In the frequency domain the power spectral density (PSD) of the internal OSDAC signals
( X 1, …, X 5 ) are illustrated by the example in Fig. 6.2 where the oversampling ratio (OSR) is
8 and the modulator order is 2. In (a) we show the input consisting of four –12 dBFS tones
and the whole bandwidth up to half the update frequency f u is used. Through interpolation
the update frequency is increased and a number of images ( OSR – 1 ) is introduced in the fre-
quency domain as shown in (b). The interpolator is also designed to perform a filtering func-
tion and in (c) we show the result using a 6th-order Cauer approximation as interpolation
filter. The modulator truncates the input signal drastically and this operation introduces a large
amount of out-of-band noise (d) due to the highpass filtering of the truncation error. In (e) we
show the same result but with a logarithmic frequency axis. The modulator has a one-bit out-
put and therefore the high noise power. The (sub-) DAC that is operating at the higher fre-
quency f O, u generates the output. This output should be filtered by an analog, continuous-
time filter that attenuates the out-of-band noise and the images that arise due to the discrete-
time operation of the DAC. Since the DAC is a one-bit DAC it can be cascaded and used a
semi-digital FIR filter. In (f) we show the result when using a 19th-order semi-digital FIR fil-
ter at the output.
From the example in Fig. 6.2 we see that the oversampling ratio is much too low for a first-
order, one-bit modulator since the noise shaping function is not powerful enough. Either we
have to increase the number of output bits from the modulator. This will however force us to
use a multi-bit DAC and the semi-digital filtering function Fig. 6.2 (f) cannot be implemented.
It is therefore better to increase the order of the modulator or the oversampling ratio. Further,
dependent on the order of the modulator the amount of out-of-band noise power will vary.
This affects the filtering function of the continuous-time filter which then must be designed to
have a high stopband attenuation and with poor design even for a narrow transition band.
Then the complexity is too high since the purpose of the OSDAC is to reduce the amount of
analog hardware. The same occurs if we use interpolation filters with poor stopband attenua-
OSDAC Building Blocks 163
OSDAC input signal OSDAC interpolated signal with zero−padding

0 0
−18 −18
−36 −36
Power [dB]
Power [dB]
−54 −54
−72 −72
−90 −90
0 0.28 0.55 0.83 1.1 0 2.21 4.42 6.62 8.83

(a) (b)
OSDAC interpolated signal with filtering OSDAC modulated signal

0 0
−18 −18
−36 −36
Power [dB]
Power [dB]
−54 −54
−72 −72
−90 −90
0 2.21 4.42 6.62 8.83 0 2.21 4.42 6.62 8.83

(c) (d)
OSDAC modulated signal OSDAC modulated signal

0 0
−18 −18
−36 −36
Power [dB]
Power [dB]
−54 −54
−72 −72
−90 −90
1.1 2.2 4.4 8.8 1.1 2.2 4.4 8.8

(e) (f)
Figure 6.2 Example spectra for different signals in an OSDAC with OSR = 8: (a) Original input spec-
trum, (b) interpolated spectrum, (c) filtered interpolated signal, (d) introduction of noise by
the modulator, (e) same as (d), but with logarithmic axis, and (f) final output signal.
tion. The fewer bits in the modulator, the more truncation noise is introduced and it also
makes the overhead design of the modulator more complex due to the stability requirements.
On the other hand, reducing the number of bits to only one in the modulator is good, since a
one-bit DAC can be used. The one-bit DAC is completely linear with respect to matching
errors since its DC transfer characteristics can always be described by a straight line. Another
advantage is that the one-bit DAC can be combined with filtering in a semi-digital FIR filter.
This relaxes the requirements on the continuous-time filter dramatically (Sec. 6.2.3).
6.2.1 Interpolator and Interpolation Filters

The purpose of the interpolator is as presented in Sec. 3.3 to pad OSR – 1 zeros between each
sample of its input signal and increase the sampling speed as

y(k) =  x(k ⁄ OSR) k = m ⋅ OSR (6.1)
 0 k ≠ m ⋅ OSR
where x is the input signal to the interpolator, OSR is the oversampling ratio, and m and k
are sequence indeces. The output y(k) is updated at the higher frequency f O, u . The operation
creates a signal frequency spectrum as was given in Fig. 6.2 (b), hence images are introduced.
In the frequency domain, the expression in (6.1) corresponds to
Y ( z ) = X ( z OSR ) , (6.2)
where z = e jωT O on the unit circle and T O is the update time period. From (6.2) we find that
the operation in (6.1) also introduces images, and as was mentioned previously, we want to
relax the requirements on the following modulator and filter by removing or attenuating the
images and resulting in a spectrum as illustrated in Fig. 6.2 (c). This is preferrably done with
interpolation filters.
The shrinking area of the circuits imply that we care less about the number of transistors.
Instead, important performance or cost measures are the number of operations (multiplication
and/or addition) per sample in the filter and length and complexity of the coefficients. We
want as few operations per sample and as short coefficients with as few ‘1’s (in a 2’s comple-
ment representation) as possible. With an optimizatiion program we can with a computer find
a set of suitable solutions for a given specification.
One way – and perhaps the simplest – to implement the interpolation filter (IPF) is to use a
one-stage interpolation filter, as the FIR filter example in Fig. 6.3 shows. The FIR filter has K
taps, i.e., a ( K – 1 ) -th order filter, and the output is in the frequency domain given by
Y (z) = H (z) ⋅ X (z) = [ a 0 + a 1 z –OSR + … + a K – 1 z –OSR ⋅ ( K – 1 ) ] ⋅ X (z) (6.3)
where a i are the coefficients of the filter. If the OSR is high, the passband and especially the
transition band of the interpolation filter has to be very narrow. (This is of course dependent
on the specification). A narrow transition band increases the order of the FIR filter rapidly.
The filter order is approximately inversely dependent on the width of the transition band,
∆ωT O , as [80]
1
K ∼ --------------- . (6.4)
∆ωT O
x(n)
To To To
a0 a1 a2 aK-1
y(m)
Figure 6.3 One-stage FIR interpolation filter. The delay To is related to the oversampling frequency.
A high filter order increases the occupied chip area and power consumption since a large
number of additions and multipliers is needed. Using IIR filters the order is not increasing as
rapidly (compare with Table 3.1 on page 59) and therefore IIR filters should be preferred over
FIR filters for high OSRs. However, the design of the IIR filters can be more complex due to
the influence of round-off noise, etc. The reachable, maximum sample frequency is also lower
than for FIR filters [81].
It can be advantageous to use multi-stage or multi-rate filtering as illustrated in Fig. 6.4. Sev-
eral interpolation filters that operate at different sampling frequencies are used. The interpola-
tion is done in several steps of e.g. R stages and the the total OSR is given by
R
OSR = L 1 ⋅ L 2 ⋅ … ⋅ L R = ∏ Lr , (6.5)
r=1
where L r are the interpolation rates of the individual interpolation filters.
x(n) y(m)
L1 H1(z) L2 LR HR(z)
x(n) y(m)
HOSR(z)
Figure 6.4 Principle description of multi-stage interpolation filtering.
Using (6.2) we write the transfer function of the multi-stage filter in Fig. 6.4 as
H OSR(z) = H 1(z L 2 ⋅ … ⋅ L R) ⋅ H 2(z L 3 ⋅ … ⋅ L R) ⋅ … ⋅ H R(z) , (6.6)
where H i ( z ) are the transfer functions of the subfilters. By interpolating in stages and using
frequency masking techniques the total filter H OSR ( z ) may be designed with very narrow
pass and transition bands [80]. With this approach it may now become sufficient with lower-
order FIR filters as subfilters, H i . The subfilters can be implemented with halfband filters if
the specification allows a 3-dB loss at the passband edge ( f u ⁄ 2 ) . The halfband filters reduces
the complexity of the filters by a factor of 50 % since the number of coefficients can be
reduced to the half [81].
Also notice that interpolation filtering with approximately unity gain within the passband will
conserve the signal power, i.e., the signal power at the output of the filter will be equal to the
power at the input [80]. Therefore, in terms of amplitude, we need to scale the filter (or the fil-
ter outputs and inputs) so that there is no unwanted truncation of the signal which would
increase the noise and lower the SNR.
A simple, but poor, filtering function is achieved by directly sampling the input signal at the
higher frequency f O, u . The output of the interpolator is then given by
y(k) = x( k ⁄ OSR ) . (6.7)
This can also be considered as a sample-and-hold (S/H) function although it is in the discrete-
time domain. We know from the previous chapters that a S/H will cause a sinc weighting of
the signal spectrum. Hence in the frequency domain we have a transfer function as
1 – z OSR
Y (z) = -------------------- ⋅ X (z OSR) . (6.8)
1–z
On the unity circle, we get
ωT O
sin  ----------- ⋅ OSR j ----------- ωT O
 2  ⋅ ( OSR – 1 )
⋅ X (e jωT O ⋅ OSR) .
jωT O
Y (e ) = ----------------------------------------- ⋅ e 2 (6.9)
ωT O
sin -----------
2
The weighting is given by the sinusoid functions in the numerator and denominator. In Fig.
6.5 we show how the weighing affects the signal frequency domain for an oversampling ratio
of 8. Notice that the weighting has been normalized by a factor of OSR. Since we are holding
the input signal OSR periods, the power of the output signal is also increased by an amount of
OSR 2 . The power attenuation at the passband edge is as high as approximately 3.9 dB. The
rejection of the images is also poor, at frequencies above double the signal bandwidth the
attenuation is approximately 13 dB. Ususally, an additional filter is needed to recover the
passband loss. This is discussed in the following.
Attenuation due to S/H interpolation
30
Power attenuation [dB]
17.9
16.4
12.8
3.9
1/(2*OSR) 2/OSR
Figure 6.5 Illustration of normalized sinc-weighting through S/H interpolation.

Cascaded accumulator structure
We discuss another interpolation filter structure that shows good immunity towards round-off
noise [28]. These are referred to as cascaded differentiators and accumulators as illustrated in
Fig. 6.6, or moving average. Since the absolute transfer function of this type of filter is similar
to that of the sinc-function, they are also referred to as sinc filters. The accumulators are also
relatively simple to implement since there are no multiplying operations.
x(n) y(m)
D(z) D(z) L A(z) A(z)
To
Figure 6.6 Interpolation filter structure using differentiators, D(z), and accumulators, A(z).
The chip area and power consumption can be kept at a reasonable low level. The transfer
function of a differentiator is given by
D(z) = 1 – z –1 (6.10)
and for an accumulator by
z –1
A(z) = ---------------
-. (6.11)
1 – z –1
The transfer function of the filter, H 1(z) , before interpolation is
H 1(z) = [ D(z) ] J = ( 1 – z –1 ) J . (6.12)
For the filter H 2(z) we have similarly
z –1  J
H 2(z) = [ A(z) ] J =  ---------------
- . (6.13)
 1 – z –1
The exponent J from (6.12) and (6.13) is the chosen filter order. The total transfer function of
the interpolation filter, H ip ( z ) , describes a lowpass filter and is given by
z –1  J
H ip(z) = H 1(z OSR) ⋅ H 2(z) = ( 1 – z –OSR ) J ⋅  ---------------
- , (6.14)
 1 – z –1
where z is related to the higher oversampling frequency. The filtering function is identical to
that in (6.8) for J = 1 except for the delay. Hence for the higher order filters we get a higher
attenuation both of images and within the signal band. At the passband edge we get an attenu-
ation of approximately J ⋅ 3.9 dB. This high attenuation must be cancelled by using an addi-
tional compensation filter which restores a “flat” transfer function [82]. Since the sinc filters
reject the images rather well the additional filter need not to be designed with especially nar-
row transition band or high stopband attenuation. In Fig. 6.7 (a) we show this concept with the
additional filter and in (b) the simulated characteristics of a cascaded configuration where
OSR = 8 and J = 2 from (6.14). We have chosen a loose specification of a maximum rip-
ple in the passband of 0.1 dB and a minimum attenuation in the stopband of only 25 dB. The
passband edge is at the angle π ⁄ OSR and the stopband edge at 2π ⁄ OSR . The compensation
filter is an FIR filter of order 17 and its coefficients have been found using an optimization
program. However, the order of the compensation filter becomes high for higher OSRs due to
a narrower transition band.
We make the observation that the filtering function of (6.14) has J poles at unity (i.e. DC,
z = 1 ). The series expansion of the (6.14) becomes
–1 J
H ip ( z ) = ( 1 + z –1 + … + z –( OSR – 1 ) ) J ⋅ ( 1 – z –1 ) J ⋅  ---------------
-
z
=
 1 – z –1
= ( z –1 + z –2 + … + z –OSR ) J (6.15)
and the poles in the expression are cancelled. Therefore, we see that the (6.15), i.e., (6.14),
can also be realized by the single-stage FIR filter as shown in Fig. 6.3 but with mutlipliers of
unity gain.
Also notice that in the example shown in Fig. 6.7 (b), a single-stage FIR filter only, without
the sinc and compensation filter, would meet the same specification used in the figure above
with a filter order of only 19. Therefore the use of the sinc filters is somewhat of an open
question. Instead, the sinc filters can be used in multi-stage structures [80], for example, if we
want to achieve an OSR of 32 we may use the sinc filters for an interpolation of 8 and then
design the FIR filter for an interpolation of 4, etc.
Further, an interpolation filter meeting the ADSL specifications can be implemented with a
single-stage IIR filter of rather low order [83]. This is further examplified by the simulation
results in Sec. 6.3.
Sinc filters and compensating FIR filter
−10
−20
sinc FIR
Gain [dB]
filter filter
−40
0 1.6 3.1
Normalized angular frequency
(a) (b)
Figure 6.7 (a) A filter is compensating the large loss within the passband due to the sinc filters. (b)
Simulated characteristics of the sinc filter (dotted) and the result with compensation filter
(solid).
6.2.2 Noise-Shaping Modulator

The modulator in the OSDAC is used to reduce the number of bits representing the signal by
truncation. The truncation error is fed back and the modulator highpass filters the error (noise)
and lowpass or allpass filters the signa [7, 9, 27, 29]. This is referred to as spectral noise shap-
ing or just noise shaping and we use the noise transfer function (NTF) to describe the shaping
of the noise and the signal transfer function (STF) to describe how the signal is passed
through the modulator.
Generally, the modulator contains filters or blocks performing filtering functions in a feedback
configuration. The feedback can be of two kinds; signal feedback, where the modulator’s out-
put signal is fed back, and error feedback, where the truncation error is fed back. These two
architectures were presented in Chapter 3 but are repeated here for convenience. The signal
feedback modulator feeds back the quantized output signal, y ( n ) , as illustrated in Fig. 6.8 (a),
and this is subtracted from the input signal x ( n ) . We have an NTF and STF as
1 H (z)
NTF(z) = ------------------------------------- and STF(z) = ------------------------------------- . (6.16)
1 + H (z) ⋅ G(z) 1 + H (z) ⋅ G(z)
For the error-feedback modulator, Fig. 6.8 (b), the transfer functions are given by
NTF(z) = 1 – H (z) ⋅ G(z) and STF(z) = H (z) . (6.17)
For the error-feedback modulator we typically design the STF to be unity, i.e., H (z) = 1 .
When designing the modulators on an algorithmic level, it should also be guaranteed that they
do not contain delay-free loops. Further, we must have control over the signal gain at lower
frequencies (for the signal band). Dependent on the number of bits in the output of the modu-
lator the gain of the feedback loop varies. If the number of output bits is lower, the feedback
gain will be higher. In fact, due to the truncation, we have a nonlinear gain in the loop. We
will refer to this (signal-dependent) gain as λ which is the ratio between the input signal to
the quantizer and its output. Since we have λ = λ(Y ) we need to guarantee stability for
worst-case, e.g. λ < λ stable . These issues are well covered in [85] and also discussed some-
what more in the following.
H(z)
H(z) X(z) Y(z)
X(z) Y(z)
G(z)
G(z)
(a) (b)
Figure 6.8 Basic structure of signal- and error-feedback modulators.
The effect on the SNR using modulators was covered in Chapter 3 and we repeat equation
(3.30) for convenience. For an M -bit L -th order modulator with an oversampling ratio OSR,
the achievable SNR is given by
SNR = 6.02 ⋅ M + 1.76 – 10 ⋅ log10 P q( L, sb

) = …
π 2L + 1
… = 6.02 ⋅ M + 1.76 + ( 20 ⋅ L + 10 ) ⋅ log10 OSR – 10 ⋅ log10 ---------------- dB. (6.18)
2L + 1
It should be mentioned that the formula does not really hold for lower-bit modulators since
the quantization noise cannot be considered as white noise [9]. Also notice that the function
does not hold for higher modulator orders since in that case we have also included zeros to the
NTF that are not placed at DC, i.e., z = 1 . To not overdrive or saturate the accumulators, we
cannot use a full-scale signal at the input for all modulator architectures. Therefore, the result
in (6.18) should be modified by the attenuation of the input signal. If we need to attenuate the
input by 18 dB, then we also need the 3-bit design margin on the modulator.
Further, from Sec. 3.4 we know that we can divide the modulators into one-bit (or single-bit)
and multi-bit modulators. For a single-bit output, the output signal is equal to the MSB of the
quantizer’s input (Fig. 6.8) or using a 2’s-complement representation, the output of the quan-
tizer is equal to the sign of its input signal. Consider the simulated output signal from the one-
bit 1st- and 2nd-order signal-feedback modulators in Fig. 6.9. The input (dashed) is swept
from the minimum to maximum. The output signal (solid) is described by square-waved
pulses. For the modulators a certain input value is represented by the average value of the
pulses at the output, hence the average duty cycle. The maximum value of the input is repre-
sented by a stable maximum output value on the output. The input mean value (DC) is repre-
sented by pulses with a 50-% duty cycle.
1st−order modulated 6−bit signal 2nd−order modulated 6−bit signal
1 1
Amplitude [LSB]
Amplitude [LSB]
−1 −1
0 10 20 30 40 50 60 0 10 20 30 40 50 60
Sample Sample
(a) (b)
Figure 6.9 Simulated modulator output (solid) for ramped input (dashed) for (a) 1st and (b) 2nd order.
The transfer function of the one-bit modulator is highly nonlinear and the loop gain is high
due to the coarse truncation, i.e., the λ -factor becomes large and hence the stability of the
modulator has to be very carefully examined. A way to reduce the influence of signal-depen-
dent λ -factor is to adaptively change the parameters in the sigma-delta modulator as sug-
gested in for example [86].
Multiple-feedback modulators
Multiple-feedback (MF) or interpolative modulators are commonly used for higher-order
modulators [27, 29]. In Fig. 6.10 a general structure of an L th-order MF modulator is shown.
The coefficients a i and b i determine the NTF and STF. The a i coefficients are used to place
zeros in the NTF to reduce the noise gain near the passband edge. The blocks A(z) are dis-
crete-time accumulators as given by (6.11). The accumulators do not contain multipliers and
they can be implemented at a low hardware cost and they give a good immunity against trun-
cation noise. This is also why the interpolative structure is a popular choice. However, scaling
is typically added to the accumulators for hardware efficiency and to control the amplitude
levels in the accumulators [85].
aN-1 a1
A(z) A(z) A(z)

X(z) Y(z)
bN bN-1 b1
Figure 6.10 General multiple-feedback modulator of higher order (N).
There are several variations on the MF modulater structure. An additional set of coefficients,
c i , for feed-forward addition of the input signal can be used to modify the STF [29]. This
concept is illustrated in Fig. 6.11. We understand that the hardware cost is increased due to the
higher number of inputs on the adders as well as more mulitplier coefficients, yielding more
variables that determine the NTF and STF.
X(z)
cN aN-1 cN-1 a1 c1
A(z) A(z) A(z)

Y(z)
bN bN-1 b1
Figure 6.11 General multiple-feedback modulator with feedforward coefficients, c.
As an example we give the expressions of the signal and noise transfer functions of a 4th-
order modulator with the structure shown in Fig. 6.10. Since we have a signal-feedback con-
figuration, the NTF and STF will be determined by the expressions in (6.16). The STF is
A4
STF(z) = -------------------------------------------------------------------------------------------------------------------------------
--------------------------------------- (6.19)
1 + b1 A + ( a1 + a3 + b2 ) A 2 + ( a3 b1 + b3 ) A 3 + ( a1 a3 + a3 b2 + b4 ) A 4
and the NTF is given by

( 1 + a1 A 2 ) ⋅ ( 1 + a2 A 2 )
NTF(z) = -------------------------------------------------------------------------------------------------------------------------------
--------------------------------------- , (6.20)
1 + b1 A + ( a1 + a3 + b2 ) A 2 + ( a3 b1 + b3 ) A 3 + ( a1 a3 + a3 b2 + b4 ) A 4
where A = A(z) are the accumulators (without scaling coefficients). Normally, the STF will
describe a LP filtering function. The zeros of the NTF in (6.20) are chosen so that they further
attenuate the noise at frequency slightly below the signal passband edge and placed on or
close to the unit circle. Hence, we need to place them close to
π
ωT = ± ----------- . (6.21)
OSR
From (6.20) we derive the zeros for the 4th- (and 5th-) order modulator as
z 1, 2 = 1 ± j a 1 and z 3, 4 = 1 ± j a 3 . (6.22)
In the same way, for the 3rd-order modulator, we will have
z 1, 2 = 1 ± j a 1 (6.23)
and finally for a 6th-order modulator we have
z 1, 2 = 1 ± j a 1 , z 3, 4 = 1 ± j a 3 , and z 5, 6 = 1 ± j a 5 . (6.24)
We see that the real parts of the zeros are all 1 and hence we cannot put the zeros on the unity
cirle (for a i ≠ 0 ) and we need a high OSR to achieve a good influence from the zeros. The
poles of the transfer functions are given by complex expressions and the overall complexity of
the synthesis of the filter structures increases dramatically with increased modulator order
[29]. A thorough discussion on simulation and stability issues are also given in related work
[93] where the properties of 14-bit input MF single-bit modulators for OSR = 32 have been
carefully examined. Therefore, in Table 6.1 we repeat the derived feedback coefficients, b i ,
from [93] for MF single-bit modulators of order 1 to 6 and OSR = 32. Notice that the coeffi-
cients are only powers of 2. This enables the multipliers to be implemented by shifts only.
Further it is in the simulations assumed that the output is ± 2 N – 1 . (In reality we use the MSB
as output of the quantizer, i.e. 0 or 1). The concept ensures very hardware efficient modulator
solutions. Added to the table is also the simulated minimum λ -factor that is required for sta-
bility. We see from the table that the size of the coefficients are growing with decreasing
index. Hence, the coefficients with “shorter” loops are smaller.
Stability for modulators using the coefficients in Table 6.1 have been verified through simula-
tions in MATLAB. Typically, this is done by plotting the root locus (the pole locations) for the
transfer function, where λ is the varying feedback gain. In Fig. 6.12 we show the root locus
for the NTF given by (6.20) and the feedback coefficients from Table 6.1. The feedback zeros
are set to zero. From the simulation result we can identify for which λ > λ min that all poles
end up within the unity circle.
In Sec. 6.3 we show simulation results where some of the modulators are co-simulated with
different filter orders and structures. Later in the chapter we discuss the trade-offs in the
design of an OSDAC for DMT-ADSL.
Order b6 b5 b4 b3 b2 b1 λ min
1 1
2 1 2
–2
3 1 4 8 6.25 ×10
–2
4 1 4 16 32 1.56 ×10
–4
5 1 8 64 256 512 9.76 ×10
–5
6 1 16 256 2048 8192 16384 3.05 ×10
Table 6.1. Feedback coefficients for different multi-feedback modulator orders for OSR=32.
Root locus for 4th−order modulator
1
Imaginary
−1
−1 0 1
Real
Figure 6.12 Root locus for a 4th-order MF modulator without the ai feedback zeros.
Multi-stage modulators (MASH)

The design of higher-order modulators can be slightly relaxed using multi-stage modulator
structures (MASH) [87]. Consider the example in Fig. 6.13 where a 4th-order modulator is
realized by using two 2nd-order modulators. The overall NTF corresponds to that of a 4th-
order modulator, but the STF only to a 2nd-order. The error of the first (upper in the figure)
modulator is fed to the input of the second modulator. Each modulator has two accumulators
and the total output is generated as the sum of the first modulator and the second modulator.
To the second modulator, an additional notch filter, D(z) , is added. Assuming that the quanti-
zation error of the first stage is independent of the input signal, we get
A2
STF(z) = ------------------------------------------------------2- (6.25)
1 + b 1, 1 ⋅ A + b 2, 1 ⋅ A
and an NTF as
Q1 d ⋅ A 2 ⋅ Q1 + Q2
-2 + D ⋅ ---------------------------------------------2- ,
NTF(z) = --------------------------------------------- (6.26)
1 + b1 ⋅ A + b2 ⋅ A 1 + b3 ⋅ A + b4 ⋅ A
where Q 1 is the truncation error from the first stage and Q 2 is the truncation error from the
second stage. The filter D may for example be designed as a second-order HP filter. Com-
pared to a 4th-order single-stage modulator, the signal swing can be increased at the input
since the accumulators are not as easily saturated. The modulator can be more easily designed
for stability and high speed [87].
A(z) A(z)
X(z) Y(z)
b2,1 b1,1
d12
A(z) A(z) D(z)
b2,2 b1,2
Figure 6.13 Two-stage 4th-order modulator structure using two 2nd-order modulators.
6.2.3 M-bit DAC

The output of the modulator is fed to the M -bit DAC and converted into a piece-wise linear
signal. M is the number of bits representing the output of the modulator, which is lower than
the number of bits representing the original input to the whole OSDAC. This internal sub-
DAC has to operate at the oversampling frequency, but is a Nyquist-rate converter with its
input signal frequencies limited to a rather narrow band (i.e. interpolation DAC). Still, of
course, the DAC has to meet the same accuracy or resolution in terms of linearity and noise as
the input number of bits.
Due to the lower number of bits we gain in terms of circuit complexity and layout. Since we
have less components in the DAC that should be matched with eachother we can use
improved layout strategies. We can also use special randomization techniques in order to fur-
ther reduce the influence of matching errors on the SNDR [10, 11, 27]. This is also discussed
in Chapter 7.
Due to the lower number of bits representing the signal, the high-frequency noise, and the
high oversampling frequency, the switches operate at a much higher frequency. Therefore, it is
very important to design a low-glitch DAC with well-controlled switching signals and timing
instants [63, 88].
One-bit DAC and semi-digital FIR filter

To guarantee very high linearity and accurate matching, a one-bit modulator together with a
one-bit DAC should be used. The one-bit DAC has an infinitely linear DC transfer character-
ics, since the transfer between its extreme values always can be expressed by a straight line
even though there are matching errors. This is illustrated in Fig. 6.14 where we show the ideal
(dashed) linearized transfer function and the corresponding errors at the start and end values.
Notice that we have illustrated the input-output mapping with straight lines. In reality, there is
no output value defined between the 0 and 1 input states. Since we can find a completely
straight line between these values, we have a fully linear device. Discrepancies will only give
rise to an offset and a linear gain error which in most cases can be neglected. In a real imple-
mentation, other limitations such as linearity of switches, voltage drops over interconnection
wires, dynamic errors, glitches, etc., determine the linearity.
Transfer function of one−bit DAC
1
Output amplitude [LSB]
0 Ideal
With error
0 1
Input bit level
Figure 6.14 DC transfer characteristcs of a one-bit DAC with (solid) and without (dashed) matching
errors.
Another advantage with the one-bit DAC is that it can cascaded – in time – and the contribu-
tion from several one-bit DACs with different conversion levels can be summed. This is the
operation of a semi-digital FIR filter [89] as illustrated in Fig. 6.15. The conversion levels of
the DACs are the coefficients a i . It is possible to use the same approach for multi-bit DACs as
suggested in [90].
With this approach we include a filtering operation in the semi-digital FIR filter. This will fur-
ther relax the requirements on the analog LP filter as well as the requirements on the preced-
ing filtering functions.
1
To To To
b(m)
1-bit 1-bit 1-bit
DAC DAC DAC
a0 a1 aK-1
A(t)
Figure 6.15 Cascaded one-bit DACs forming a K-tap FIR filter structure.
The output signal of the semi-digital FIR filter is continuous-time and piece-wise linear due to
the S/H functions and at the sampling instants it is given by
y(t) = a 0 ⋅ w(t) + a 1 ⋅ w(t – T o) + a K – 1 ⋅ w(t – ( K – 1 )T o) , (6.27)
where K is the number of taps in the FIR filter and T o = 1 ⁄ f O, u is the sample period time.
Typically, we want the FIR filter to attenuate the out-of-band noise. If the noise transfer func-
tion has its cut-off frequency near the signal bandwidth frequency, f u ⁄ OSR , we need to
design the filter to have a narrow transition band as well. Since the number of taps, K , is
approximately inversely dependent on the width of the transition band, the order may increase
rapidly [80]. In terms of design complexity, long FIR filters are not hard to design due to the
modularity. On the other side, they will introduce a large delay through the registers (Fig.
6.15). In an actual implementation, a longer FIR filter also introduces larger glitches and
switching noise to the sensitive analog output signal.
Note, that matching errors in the coefficients will affect the transfer function (the filter specifi-
cation), i.e., ripple in passband, stopband attenuation, etc., no distortion will be introduced.
Hence, in the choice of the coefficients we have to have a filter design margin that also covers
the influence of the expected matching errors. In an actual implementation distortion will arise
due to other phenomena such as limited output impedance, nonlinear switches, etc. This is
also discussed in Sec. 6.4.
6.2.4 Interpolated Semi-Digital FIR Filter

A drawback with the semi-digital FIR filter is that the number of (nonzero) coefficients in an
FIR filter becomes high for narrow transition bands. Hence, the filter will become very large
at high oversampling ratios. Instead an interpolated FIR filter (IFIR) can be used [80, 94].
Using an IFIR filter we can reduce the number of nonzero coefficients. To design an IFIR we
start with designing for L times wider pass- and transition bands. This will give us a set of
coefficients and a transfer function described by
H (z) = c 0 + c 1 ⋅ z – L + c 2 ⋅ z –2L + … (6.28)
With an L th order interpolation, where ( L – 1 ) zeros are padded between each coefficient,
the resulting transfer function becomes
H IP(z) = H (z L) , (6.29)
hence we get the transfer function
H IP(z) = H (z L) = c 0 + c 1 ⋅ z – L + c 2 ⋅ z –2L + … (6.30)
Notice that the number of delay elements is still the same. Instead, we have a number of zero
taps included in the filter. These can however be laid out much more densely.
Through the interpolation the original magnitude response is “compressed” L times and
repeated L – 1 times within the Nyquist frequency range. Since the number of taps in the fil-
ter, K , is inversely proportional to the width of the transition band
1 1
K ∼ ------------ = -------------------------- , (6.31)
∆ωT ωs T – ωc T
we have that the number of (nonzero) taps in the IFIR case is decreasing with approximately
L compared to the corresponding original FIR filter.
In Fig. 6.16 the concept of IFIR filters is illustrated for an interpolation of four times. The
maximum attenuation in the passband up to ωT = π ⁄ 32 is 0.1 dB and the minimum attenua-
tion in the stopband from ωT = π ⁄ 16 is 40 dB. We show the magnitude response of an IFIR
with 34 nonzero taps. Due to the interpolation, the passband is then repeated. The correspond-
ing FIR filter that realizes the same LP function requires 131 taps. We need the image-rejec-
tion (continuous-time) filter to have a high attenuation for these frequencies. For a higher
degree of interpolation the analog filter order increases due to narrower transition band and
high stopband attenuation.
Magnitude responses of FIR and IFIR filters
0 FIR
IFIR
0
Power [dB]
−40
−40
pi/32 pi/2
Normalized angular frequency
Figure 6.16 Magnitude responses for an FIR filter and an interpolated (4 times) FIR filter. The IFIR has
a 5-dB offset for illustration.
Utilizing this technique we may relax the design of the analog filter by design the modulator
to perform a bandpass NTF instead of the common highpass approach [94]. This is also
referred to as a bandpass sigma-delta modulator [27, 29]. We let the NTF attenuate the trunca-
tion noise in the frequency space corresponding to the IFIR passbands. The complexity in
designing the modulator will increase, but we can once again gain in less complex analog cir-
cuits.
6.2.5 Image-Rejection and LP Filter

An analog LP filter at the OSDAC output (Fig. 6.17) attenuates the images occuring due to the
S/H elements in the semi-digital FIR filter, but must also be designed to attenuate the modula-
tor’s noise at higher frequencies. With high oversampling ratio and good interpolation filters
we get a very wide transition band, in the order of ( OSR – 1 ) ⋅ f u . However, the lower num-
ber of bits at the modulator’s output, M , the higher truncation noise power will be introduced
and hence higher attenuation in the stopband is required. In fact, the noise power spectral den-
sity (PSD) may even become larger than the signal PSD. If M = 1 , i.e., one-bit DAC, we
should use a semi-digital FIR filter instead of a single one-bit DAC since otherwise it becomes
difficult to design an analog filter meeting the specification. The filter order becomes high and
thereby we introduce to many error sources to our design and hence we do not gain in using
the oversampling technique.
In addition, in before the analog filter, an additional discrete-time IIR filter, e.g., switched-
capacitor or switched-current, can be used to further attenuate the spectrally shaped noise, as
illustrated in Fig. 6.17 (b). Then frequency masking techniques may be used as well [80].
Once again, we introduce additional sources for distortion and we should try to keep the ana-
log chain in the OSDAC as short as possible.
Semi-digital Analog
FIR filter LP filter
(a)
Semi-digital Discrete-time Analog

FIR filter filter LP filter
(b)
Figure 6.17 Images are rejected and noise attenuated with (a) continuous-time filter and (b) additional
discrete-time filters.
In Table 3.2 on page 60 in Chapter 3 we summarized the required order of the analog lowpass
or image-rejection filter at the output for an interpolation DAC. For a 60-dB stopband attenua-
tion and 1-dB passband ripple we found that the required filter orders are approximately 2 for
higher oversampling ratios. It was assumed that the interpolation filters were well-designed
with a high stopband attenuation. This is further discussed in the trade-off discussion in Sec.
6.3.
6.3 Simulation Results of OSDAC Blocks

In the previous discussions we have considered some of the properties of different OSDAC
building blocks. In Figure 1.16 on page 20 we found the spectral requirements on the trans-
mitted signal from both the CO and CPE side and in our work, we have focused on the CO,
where the requirements on the transmit path is somewhat tougher due to the higher transmis-
sion rate and bandwidth. In Table 1.3 on page 21 the spectral requirements were compiled.
In Sec. 6.4 we describe the implementation of an OSDAC with a fifth-order modulator and in
this section we will discuss the simulation results of some of the blocks that were used for this
DAC. Compared to Table 1.3 on page 21, we have not considered the band pass filtering (i.e.,
the POTS band removed). Instead we design the DAC for the low pass case and we under-
stand that additional passive filters will be used to filter out the POTS band up to 4–5 kHz.
Due to their advantages in terms of linearity and semi-digital FIR filtering option, we have
only considered one-bit modulators. No discrete-time IIR filters have been used to reduce the
analog components in the converter. In fact, the design of the entire OSDAC is similar to filter
optimization problems. This is examplified by Fig. 6.18 where several of the OSDAC’s filter-
ing functions are displayed: the ones orginitating from the interpolation filters, the NTF and
Simulation Results of OSDAC Blocks 179
STF of the modulator, semi-digital FIR filter, and the analog filter. By choosing a good semi-
digital filter the requirements on image-rejection filter may be relaxed significantly. With good
interpolation filters at the input, the requirements on the semi-digital filter may be relaxed.
Typical filtering functions in OSDAC
−36
PSD [dBm/Hz]
−90
Interpolation
Continuous−time
Modulator
Semi−digital FIR
0.026 1.1 2.2 4.9
Frequency [MHz]
Figure 6.18 Filtering functions in the of the OSDAC output signal, illustrated in the frequency domain.
A trade-off in terms of complexity vs. performance, power consumption, and chip area, etc.,
can be done. One of the major problems is to find a proper cost function that weights the dif-
ferent properties. In this work, it has not been considered and we leave it to the filter designers
to implement the proposed filters with as efficient structures as possible.
To find the influence of the different building blocks they can be modeled and simulated in
e.g. MATLAB on a behavioral level. Due to inaccurate models and process variations, the cir-
cuit implementations will not give the same results, but nevertheless with a reasonable amount
of accuracy, we have a design guide with our models. We know what parameters to change to
reach a higher performance.
The number of modulator output bits is set to be only one and first we check for which OSR
and modulator orders that the 14-bit resolution can be met. In Figure 3.11 on page 67 we
showed the achievable ENOB for a 6-bit modulator for different OSRs. For this case we use
equation (6.18) although it is not completely correct. In Table 6.2 we have summarized the
result. The ENOB values have been rounded to closest lower integer value to get a design
margin. The configurations meeting the 14-bit resolution are highlighted in the table. The
modulator configurations that are used in the simulation comparison are shaded. Hence in the
following we use oversampling ratios of OSR = 16 and 32. For ADSL the signal bandwidth is
1.104 MHz and i.e. the oversampling frequencies become 35.328 and 70.656 MHz. For higher
OSRs we consider the update frequency to be too high with the available CMOS technologies.
We also find that we would require at least a 7th-order modulator for OSR = 8. This is a very
high order and it will become rather large and complex. Further on we may with the low OSR
have trouble with placing the NTF zeros.
We should also be aware of the fact that we might not be able to force a full-scale signal into
the modulator since the accumulators will saturate. Hence the achievable SNDR will not reach
14 bits if the design margin in is too low. Therefore, we can expect for example the configura-
tions L = 3 , OSR = 32 and L = 5 , OSR = 16 , etc., to not give 14 bits. In some cases,
one can make a distinction in SNDR measured with respect to the signal and SNDR measured
with respect to the FS input, i.e., dB vs. dBFS.
Modulator order ( L )
OSR 3 4 5 6
8 7 8 10 11
16 10 13 15 18
32 14 17 21 24
64 17 22 26 31
Table 6.2. Achievable ENOB for different OSDAC configurations.
6.3.1 DMT-ADSL Input Signal

The input signal is a discrete multi-tone (DMT) signal as discussed in Chapter 1. In the down-
stream direction (the transmission from the CO) we have the tones spaced from 25.875 kHz to
1.104 MHz at multiples of the 4.3125-kHz frequency. (Some of the tones are left out accord-
ing to the specification [3]. Each tone is QAM modulated with the corresponding data. In our
simulations we let all tones have equal amplitude but with random phase. This keeps down the
peak-to-average ratio (PAR) and in the simulations it has been kept at values close to 3.
In Fig. 6.19 we illustrate the signal applied at the input of the OSDAC in (a) the time domain
and in (b) the frequency domain. In some of the simulations we have used single-tone signals
to simplify the presentation of the result and to simplify the calculation of the SNR. Another
approach would be to simulate the PSD of the input signal instead of generating a number of
tones [2]. This will give us a spectral view of the signal fed through the OSDAC. In this sec-
tion we will however use tones since it allows us to better understand the influence of distor-
tion and noise.
6.3.2 Interpolation Filters

As interpolation filters, we use single-stage Cauer approximations and FIR filters. This is to
illustrate two extremes in terms of hardware cost and complexity. According to the specifica-
tion [3], we want to attenuate the signal at higher frequencies by approximately 53.5 dB and
preferrably even more. The ripple in the passband should be kept below 3 dB, but we choose
0.5 and 0.1 dB as design specifications. There is a rather wide transition band, which makes
the single-stage solutions attractive [83].
In Table 6.3 we summarize the resulting interpolation filter orders. They have been found by
using corresponding filter design functions in MATLAB [91]. The Cauer approximation
requires a lower filter order, but the sensitivity to coefficient truncation is higher compared to
all FIR filters in direct form.
In Fig. 6.20 we show the simulated magnitude responses for the different interpolation filters
summarized Table 6.3 for OSR = 16 . In (a) we find the responses for the Cauer approxima-
tions for both oversampling ratios and in (b) we find the responses for the FIR version. The
dashed lines indicate the 0.1-dB specification on the maximum attenuation in the passband.
DMT ADSL signal DMT ADSL signal
8192 −6
−33
Power [dBFS]
0
−100
−140
−8192
0 1 2 3 0 0.276 0.552 0.828 1.104
Time [ms] Frequency [MHz]
(a) (b)
Figure 6.19 256-tone DMT Input signal.
IPF Cauer I IPF Cauer II IPF FIR I IPF FIR II
OSR A max = 0.5 dB A max = 0.1 dB A max = 0.5 dB A max = 0.1 dB

16 5 5 57 74
32 5 5 114 148
Table 6.3. Interpolation filter orders for different structures and OSR.
Cauer interpolation filters FIR interpolation filters
−36 −36
PSD [dbm/Hz]
PSD [dbm/Hz]
−90 −90
1/32 1/16 1/32 1/16

(a) (b)
Figure 6.20 Magnitude responses of (a) Cauer and (b) FIR interpolation filters for OSR = 16 and 32.
Solid lines indicate the 0.5-dB specification on the passband ripple and dashed lines the
0.1-dB specification.
6.3.3 Noise-Shaping Modulators

In the comparison we use MF modulators of orders 3, 4, and 5. The modulator coefficients for
OSR = 32 are derived heuristically using the approach as compiled in Table 6.1 and presented
in [85]. They are also given together with the a i parameters and the λ -factors in Table 6.4.
The coefficients need to be modified for the modulator with OSR = 16 – especially the a i
parameters that are determining the placement of the NTF zeros. Some of the configurations
are not feasible as shown in Table 6.2, e.g., we cannot reach the desired performance with a
3rd-order modulator for OSR = 16. Therefore, these configurations have been left blank in the
table. For the case with OSR = 32, we want to place the zeros close to
π
± j -----------
z = e OSR . (6.32)
Since the zeros for the MF architecture will have a real part equal to unity, we get according
to (6.22) and (6.23)
z = 1 ± j ai (6.33)
If OSR is reasonably large, we can use the first-order Taylor expansion of (6.32) to compare it
with (6.33) and we get
π π 2
z ≈ 1 ± j ----------- = 1 ± j a i ⇒ a i =  ----------- (6.34)
OSR  OSR
To choose a low-cost coefficient, we can use the upper and lower bounds as
8 16
-------------2- < a i < -------------2- , (6.35)
OSR OSR
For example, if OSR = 32 = 2 5 we get 2 –7 < a i < 2 –6 . The chosen coefficients for the dif-
ferent modulators are given in Table 6.4.
Coefficients
Order
OSR = 16 OSR = 32
–2
3 b 3, b 2, b 1 = 1, 4, 8 , λ = 6.25 ×10
N/A b 4, b 3, b 2, b 1 = 1, 4, 16, 32
4 –2
a 1 = 2 –7 , λ = 1.56 ×10
b 5, b 4, b 3, b 2, b 1 = 1, 8, 64, 256, 512 b 5, b 4, b 3, b 2, b 1 = 1, 8, 64, 256, 512

5 –3 –4
a 1, a 2 = 2 –7, 2 –6 , λ = 7.808 ×10 a 1, a 2 = 2 –8, 2 –7 , λ = 9.76 ×10
Table 6.4. Modulator feedback coefficients used in the OSDAC simulations.
In Fig. 6.21 (a) through (c) we show the simulated outputs of the different modulators of order
3, 4, and 5, in Table 6.4 for OSR = 32 . Instead of multi-tone signals, single-tone inputs are
applied to better illustrate the operation of the noise shaping modulators. We see the operation
of the NTF and the truncation noise power is increasing at higher frequencies. To further pre-
vent for overflow in the modulators, the input signals have to be scaled. Otherwise the accu-
mulator will saturate and we will not achieve stability. Therefore, for the 3rd-order modulator,
the input signal is –6 dBFS, for the 4th- and 5th-order modulators, it is –21 and –24 dBFS,
respectively. We see that we loose some in dynamic range due to this scaling. This is one of
the major drawbacks with the multiple-feedback architecture. Another disadvantage is the DC
gain (and the gain in the passband) that is larger than unity and that varies with the coeffi-
cients and filter order.
As a comparison of the spectra we show in Fig. 6.21 (d) the simulated output signal of the
5th-order modulator for OSR = 16 .
Output from 3rd−order MF modulator Output from 4th−order MF modulator

74
62 74
62
38
PSD [dBmFS/Hz]
PSD [dBmFS/Hz]
38
1.1 2.2 1.1 2.2

(a) (b)
Output from 5th−order MF modulator Output from 5th−order MF modulator
74 74
62 62
PSD [dBmFS/Hz]
PSD [dBmFS/Hz]
38 38
0 0
1.1 2.2 1.1 2.2

(c) (d)
Figure 6.21 Examples on modulator output spectra for single-tone inputs. Modulator orders are (a) 3,
(b) 4, (c) 5 for OSR = 32 and in (d) a 5th-order modulator for OSR = 16.
A related study on different kinds of sigma-delta modulators for these kinds of applications
(ADSL and VDSL) is presented in [84]. The work also presents the implementation of a 5th-
order error-feedback modulator for VDSL.
6.3.4 Semi-Digital FIR Filters and Image-Rejection Filter

Since we have fixed the number of bits in the modulator’s output to one, we use a semi-digital
FIR filter instead of a single-stage M -bit DAC. The coefficients of the FIR filter have been
truncated to an internal 9-bit representation, i.e., the analog elements used in the DACs consist
of unit elements where the largest tap could be given by approximately 512 unit elements.
In Table 6.5 we show two feasible filter orders for different OSR and specifications on the
attenuation in stop- and passband, i.e., A min and A max , respectively. The cut-off angles are
given by π ⁄ OSR and 2π ⁄ OSR . Since the coefficients are truncated, higher filter orders must
be used to meet the specifications. Once again, in a more dedicated filter design one could
apply an optimization program instead to achieve an even better solution.
OSR A max = 0.5 dB and A min = 53 dB A max = 0.1 dB and A min = 53 dB
16 84 101
32 157 189
Table 6.5. Semi-digital FIR filter orders for different OSR and stopband attenuation.
The original coefficients have been found with Remez’ algorithm. By truncating the coeffi-
cients we destroy the properties at the pass- and stopband edges and the ripple is no longer
equiripple in pass- and stopband. To meet the specification we have to increase the filter order
from the ideal 83 to 101.
In Fig. 6.22 we show the filter magnitude response for the semi-digital FIR filter, SD FIR I,
for OSR = 16 with (a) and without (b) truncated filter coefficients. F Notice, that we have
plotted the responses in a loglog scale.
Magnitude response of truncated semi−digital FIR filter Magnitude response of semi−digital FIR filter
0 0
Power [dB]
Power [dB]
−53 −53
pi/16 pi/8 pi/2 pi/16 pi/8 pi/2

Normalized angular frequency Normalized angular frequency
(a) (b)
Figure 6.22 Magnitude response of the semi-digital FIR filter, SD FIR I, (a) with and (b) without trun-
cated coefficients.
The image-rejection filter is preferrably chosen to be of Cauer approximation. Typically, it is

A CMOS Current-Steering 5th-Order OSDAC for DMT-ADSL 185
implemented with active RC or gm-C circuits. Since we want to keep the design effort on the
analog filter at a minimum and therefore the order of the analog filter should be of the order 1
or 2. Without the semi-digital FIR filter, we would require very high continuous-time filter
orders due to the high truncation noise power. For a Cauer approximation of the filter this
would result in orders of at least 6 or 7 as discussed in Chapter 3.
6.4 A CMOS Current-Steering 5th-Order

OSDAC for DMT-ADSL
It has been found [85, 92, 93] that the ADSL specification will not be met with the 3rd and
4th order modulators and only nearly met with the 5th-order modulator. This is due to the
required downscaling of the input signal, since we are not able to reach the desired dynamic
range with the chosen single-bit output. Further, an oversampling ratio of at least 32 is
required to allow a feasible implementation of a modulator with a single-bit output.
Once again, notice that in this work no co-optimization of the passband behavior has been
taken into account. Instead we sum up the total loss at the passband edge of all filters. There-
fore, we have chosen the passband ripple from the interpolation to be small ( A max = 0.1 dB).
Then we let, due to the coarse quantization of the coefficients, the semi-digital FIR filter have
a rather high ripple in the passband. (The specification allows that the carriers fluctuate by
approximately 3 dB). With an optimization toolbox we can generate filter coefficients in a
smarter way so that the behavior within the passband is much more controlled.
In this section we present the design of a 14-bit 5-V 0.6- mCMOS OSDAC for DMT-ADSL
applications [85, 92, 93]. The oversampling ratio is 32. The OSDAC is implemented without
interpolation filters or an analog filter. The modulator order is 5 and the semi-digital FIR filter
has 219 taps. In this section we briefly overview the design of the semi-digital FIR filter. The
analog filter was not implemented since it would require too large on-chip capacitors due to a
high output DC current from the semi-digital FIR filter. Secondly, the OSDAC was imple-
mented to meet an older ADSL specification than the one presented in Chapter 1 and hence
some specification values on the filter seem somewhat misplaced.
6.4.1 Semi-Digital FIR Filter

Since unit elements are used in the layout, the coefficients of the semi-digital FIR filter were
truncated according to the formula
max a i
ã i = J ⋅ ------------------- + 0.5 ⋅ sgn { a i } , (6.36)
min a i
where J is a gain value which determines the size of the truncation error. With higher accu-
racy, J , the errors in the filter’s frequency response will be smaller, but the chip area will
increase, since with a higher J we need more unit elements. The FIR filter was designed to
meet a specfication where the cut-off frequency was chosen to be
f c = 1.15 ⋅ f N ≈ 1.27 MHz which is slightly higher than the signal bandwidth of 1.104 MHz
to cover for the effects due to the truncation of the coefficients. Using the normalized angular
frequency the specification on the filter is
fN 2.30π
ω c T ≈ 2π ⋅ 1.15 ⋅ ------- = -------------- ≈ 0.23 (6.37)
fu OSR
and
fN 2.94π
ω s T ≈ 2π ⋅ 1.47 ⋅ ------- = -------------- ≈ 0.29 . (6.38)
fu OSR
The maximum passband ripple is 0.1 dB and the minimum stopband attenuation 34 dB. From
(6.37) and (6.38) we find the width of the transition band is ∆ωT = 0.64π ⁄ OSR ≈ 0.06 .
Using the Remez algorithm and iterating the results for different truncation levels ( J ) and
comparing each result with the specification, gives finally a 219-tap filter.
The implemented semi-digital FIR filter is of a current-steering architecture. Hence, each sub-
DAC controls a switch determining if a current source should be connected to the output. The
principle is shown in Fig. 6.23 (a), where the single-bit output from the modulator, w(n) , is
b(m)
To To To
a0Iu a1Iu a2Iu aK-1Iu
Iout(t)
(a)
a0Iu a1Iu aK-1Iu
Iout(t)
Positive Negative Positive Iout(t)

coefficient coefficient coefficient
(b)
Figure 6.23 (a) Current-steering implementation of a semi-digital filter with coefficient length K. (b)
Differential current switches where negative coefficients are realized by cross connecting
the outputs.
fed into a shift register and the contents of the shift register is used to control the current
switches. For each switch (or subDAC) a current source of strength a i ⋅ I u is associated. a i is
a filter coefficient and I u is a unit current size.
The filter uses a total of 2390 unit current sources in 219 taps. The largest coefficient consists
of 152 unit current sources and in general the design of the filter is straightforward and very
similar to the current-steering DAC designs described in the previous chapter.
Unit current source

The unit current source is similar to those described in Sec. 5.4 and in the filter single-cas-
coded PMOS current sources were used. As a design guide we considered the output resis-
tance of the filter. The peak number of unit current sources is less than 2390 and by current
division we have that the maximum current loss is given by
RL
∆I = ------------------------- ⋅ I peak , (6.39)
RS
R L + ----------- -
2390
where R L is the load resistance and R S is the output resistance (at DC). For a 14-bit resolu-
tion we want this loss to be less than
1
∆I < I peak ⋅ --- ⋅ 2 –14 . (6.40)
2
Combining (6.39) and (6.40) gives that
6
R S > R L ⋅ 2 15 ⋅ 2390 ≈ R L ⋅ 78.3 ×10 , (6.41)
which for a 50- Ω load requires an output resistance of at least R S > 4 GΩ which is fairly
easy to achieve according to the simulated results in Fig. 5.9 and Fig. 5.10. The layout of the
unit current source is similar to that of Fig. 5.22, i.e., the widths are equal
W 1 = W 2 = 3 µm and the lengths are L 1 = 8 µm and L 2 = 2 µm . The size of matching
errors apply in the same way as for the current-steering converter. Since we have truncated the
coefficients and used a design margin, the influence of the matching error can be kept within
these boundaries.
The unit current size is chosen to be approximately I u ≈ 1.65 µA , and hence the resulting
peak output current is I peak = 1.65 ⋅ 2390 µA ≈ 3.94 mA . The average output current, i.e.,
the current corresponding to a DC input, is found when the input to the shift register is alter-
nating between “0” and “1” with a 50-% duty cycle. We have
I out = I DC = I u ⋅  ∑ ai – ∑ a i ≈ 1318 ⋅ I u ≈ 2.17 mA, (6.42)

 
i odd i even
hence the average power for one channel in a 50-Ω load is given by
P out = I out 2 ⋅ 50Ω = 0.24 mW. (6.43)
A partial plot of the impulse response from the semi-digital FIR filter from a circuit-level sim-
ulation is shown in Fig. 6.24. The dual output currents are terminated by 50 Ω each. Due to a
startup phase, since the shift register has to be emptied, the figure only displays the 172 out of
219 center values. The register was designed without any reset signal.
Semi−digital filter impulse response

4.45
4.4
4.35
Differential output current [mA]

4.3
4.25
4.2
4.15
4.1
4.05
3.95
0 200 400 600 800 1000 1200
Time [us]
Figure 6.24 Impulse response from a circuit-level simulation of the semi-digital FIR filter.
Current switches
The switches are differential to reduce glitches and to improve linearity and noise behavior.
We must guarantee to never shut of the current sources completely. Since differential switches
are used, negative filter coefficients can be realized by cross-coupling the outputs for the spe-
cific tap as illustrated in Fig. 6.23 (b). All current switches are equally large and in each tap
eight NMOS transistors in parallel are used. This ensures equal capacitive load for all D-
latches. NMOS transistors were used for higher speed due to lower capacitive load and on-
resistance. The layout is similar to those of Fig. 5.24.
D-latches
The digital delay elements (D in Fig. 6.23) in the shift register are dynamic CMOS gates with
true single-phase clocking (TSPC) circuits [12]. This simplifies the clock distribution since
only one clock phase is required. We must, however, guarantee very short rise and fall times.
Each delay element uses two latches, one P-type and one N-type. Schematic views of the
latches are shown in Fig. 6.25 (a) and (b), respectively. The outputs, Q + and Q – , are comple-
mentary and hence suitable for controlling the differential current switches. The latches are
sensitive to the capacitive load on their outputs and we have guaranteed a constant capacitive
load by designing all current switches to be equally large. By cascading the P-latch with the
N-latch, we have a one-clock-period delay element (D-latch). The D-latch can be laid out as
compact blocks and in the filter they are designed to be as wide as the current switches and
the unit current sources (with interconnect). This allows us to design a tap slice, i.e., one-bit
sub-DAC (dashed in Fig. 6.23).
Filter taps
The tap slices contain as many unit sources as the largest tap does. To generate a coefficient
we select the corresponding number of unit sources to use and interconnect them. The other
sources are short-circuited by the supply or used as bias sources. Additional dummy sources
are used to improve the edge matching. This also makes it for example, simpler to implement
an automatic filter generator as well.
clk
Q Q
clk clk Q Q
D D
D D
(a) (b)
Figure 6.25 Transistor schematics of (a) P- and (b) N-type latches.
6.4.2 Complete Chip Layout

A die photograph of the implemented OSDAC is shown in Fig. 6.26. The floorplan of the
design is similar to the implementation of the Nyquist-rate converters in Chapter 5. The chip
is designed to have digital and analog supply voltages from 3V to 5V. The chip has not been
measured due to fabrication errors. On-chip decoupling capacitors have been added to stabi-
lize the supply voltage on chip, reducing the influence of parasitic inductance and resistance
in bond wires.
Filter
Modulator
Figure 6.26 Die photograph view of the OSDAC with modulator and semi-digital FIR filter.
A 5th-order one-bit modulator, designed by Dr. Yonghong Gao [92, 93] is implemented on the
chip. Its core size is approximately 1.2 × 0.8 µm 2 and the approximate power consumption is
92 mW at a clock frequency of 71 MHz and 3-V supply. To save hardware and to reduce
power dissipation the modulator’s coefficients have been scaled internally.
The core area of the semi-digital FIR filter is approximately 3.2 × 0.5 µm 2 . The average
power dissipation for the filter is approximately 6 mW at 71 MHz and with a 3-V analog and
digital supply. A higher-layer metal plate is covering the current sources to provide the current
sources with the positive analog supply. N- and P-diffusion layers are used as shielding layers
to decrease substrate coupling between the analog current sources and the digital shift register.
7 Special Techniques for
Enhanced D/A Conversion
7.1 Introduction
In the previous sections we have discussed implementation aspects and properties of mainly
current-steering DACs. We have found that the major limitations on performance are the out-
put impedance, matching errors, and noise. A finite output impedance will give a signal-
dependent settling time as well as a signal-dependent current loss through the DAC which
results in distortion. The matching errors are static and they will influence the DC transfer
characteristics. With a dual DAC output the even-order distortion due to matching errors do
not cancel eachother. This is, however, the case for the even-order terms arising due to the
finite output impedance. With an output buffer providing the DAC with a low-impedance
node, i.e., virtual ground, practically eliminates the problem with limited output impedance.
Therefore most effort should be put on minimizing the matching errors. Typically this is done
through careful layout with special techniques, such as using unit elements, interdigitized,
common-centroid and dummy elements for improved edge matching. However, there will still
be matching errors that influence the achievable performance.
In this chapter we discuss some different methods to reduce the effect of the matching errors
by using proposed algorithms and other special techniques in the digital domain. There are
several different approaches to improve performance and we divide them into three cases;
inverse functions (Sec. 7.2), element calibration (Sec. 7.3), and dynamic element matching
(DEM) techniques (Sec. 7.4).
The inverse-function methods presented in Sec. 7.2 require two important parameters: one is
knowledge about the nature of the nonlinearity and the second is a feedback loop including an
ADC or similar. For the calibration and DEM techniques this is not needed. The element cali-
bration technique aims on adjusting the size of the elements in the DAC. With DEM we get
the average of the signal-dependent errors and will transform into signal-independent noise or
offset.
191
There are also other issues to be considered. For example randomization techniques will give
rise to rather large glitches due to the frequent switching of reference elements. We have
investigated how the DAC behaves when unconventional or generalized codes are used for the
conversion. This investigation is discussed in Sec. 7.5. We show for example that a proposed
so-called linear code shows better glitch behavior in a 14-bit DAC than a binary-weighted
DAC with up to six segmented MSBs.
7.2 Nonlinear Error Compensation

At least on the behavioral level, the nonlinearity of the DAC can be cancelled in several way.
We consider three different ways; pre- and post-distortion and compensated DACs [103, 104].
The two former, Fig. 7.1 (a) and (b), creates an inverse function to be put either before or after
the DAC. In the latter approach, Fig. 7.1 (c), we use an additional DAC in parallel to add or
subtract the errors from the output.
DAC DAC
(a) (b)
Delay DAC
Comp
DAC
(c)
Figure 7.1 Error cancellation by using an inverse function (a) at the input, (b) at the output, and (c)
compensating DAC in parallel.
The difficulties with using compensating circuits are obvious; the errors in the DAC should be
á priori known, the inverse function must be nonlinear as well, i.e., its parameters might have
to be signal dependent, and a feedback loop providing us with information on the effective-
ness of the inverse function (e.g. an ADC) is needed.
The post-distortion circuits (b) must be implemented by analog circuits and it is difficult to
design. This design effort should instead be put on the design of the analog elements in the
DAC itself.
We should prefer the pre-distortion technique, since it can to a larger extent be implemented
with digital circuits (the feedback ADC not included). Pre-distortion is for example used in
measurement equipments where expensive process techniques are allowed for high accuracy
and calibration and service maintenance. This is not the case for consumer products where as
simple and cheap circuits as possible should be used. The pre-distortion technique is also
commonly used in radio applications, but with somewhat other approach than the ones
described in the following [103].
Nonlinear Error Compensation 193
The compensating DAC to be used in parallel with the original DAC has the advantage of that
we can in some sense copy the nonlinearities of the designed and implemented DAC which
gives us valuable information on the nature of the errors. We are also able to perform an error
correction that is not limited by the finite word length. (This is described further in the follow-
ing). The disadvantage with this approach is that the correction is done in both the analog and
digital domain. Therefore, we focus on the pre-distortion circuits instead.
7.2.1 Pre-Distortion Circuits

The operation of a pre-distortion circuit is straightforward. If we assume that the ideal output
of the converter Ã(X ) should be a linear function of the input
Ã(X ) = ∆ ⋅ X , (7.1)
where X is the input code and ∆ is the LSB step size. If the number of bits is large enough,
we can consider the quantization noise to be white and it is left out in the following discus-
sions. In a converter with static nonlinearities (matching errors), we will instead have
A( X ) = a ⋅ X + b ⋅ X 2 + c ⋅ X 3 + d ⋅ X 4 + … (7.2)
Since we are considering the memoryless case, there are no dependency on previous X val-
ues. By investigating the dynamic errors, we need to use other mathematical tools, e.g., Volt-
erra description of the system [105, 106, 107], etc. A typical discrete-time Volterra expansion
is expressed by
N–1 N–1 N–1
y ( k )(n) = ∑ ∑ … ∑ h ( k )(n 1, n 2, …, n k) ⋅ x(n – n 1) ⋅ x(n – n 2) ⋅ … ⋅ x ( n – n k )
n1 = 0 n2 = 0 nk = 0
, (7.3)
where x(n) is the input, y ( k )(n) is the output described by the k th-order Volterra model, and
h ( k ) is the k th-order Volterra kernel. This approach introduces a high complexity to the pre-
distortion circuits, but the theory is of a similar nature as the static case in (7.2) and in the fol-
lowing we will partially leave the discussion on Volterra expansions and we refer to related
material [74].
Now, we want to apply a digital input, X' , that cancels the higher-order terms in (7.2), i.e.,
A(X') = Ã(X ) . (7.4)

Hence we want to design a digital circuit to put in front of the DAC (Fig. 7.1) that performs
the following operation
X' = A –1( Ã(X )) = A –1(∆ ⋅ X ) (7.5)
The higher degree of nonlinearity that should be cancelled, the larger complexity of the com-
pensation circuit.
In this section we focus, as an example, on the influence of finite output impedance on the sin-
gle-ended output case. If we use the expression from (4.65) describing the distorted output we
have the output current as function of the input code X
Iu ⋅ X
I out(X ) = -----------------------
-. (7.6)
1 + ρG ⋅ X
We now want to find the X' that generates the ideal or wanted output current
Ĩ out(X') = I u ⋅ X . (7.7)
Combining (7.6) and (7.7) gives the inverse input signal

I u ⋅ X' X
------------------------- = I u ⋅ X ⇒ X' = ------------------------ . (7.8)
1 + ρ G ⋅ X' 1 – ρG ⋅ X
The operation above gives a nearly perfect cancellation in the static case. Due to truncation
errors and limited word length a perfect cancellation cannot be achieved though. If we use
oversampling we may trade resolution against frequency. This will however require special
techniques in implementing the correction algorithms.
The linearization approach in (7.8) requires a division, multiplier, and addition. This will be
costly in terms of hardware and power consumption. There are ways of speeding up the calcu-
lation, e.g., if the ρ G parameter can be written as a power of two the multiplication is done by
a simple shift operation, etc. However, to overcome the problems, we make an observation:
Assume that we have a 14-bit resolution at the input and that the conductance is very low
(typically in the order of 10 –8 ). We see that as long as the deviation from the ideal signal is
less than half an LSB we will not have any influence of the compensation circuit. Hence, with
the inverse input from (7.8) we investigate the inequality
X 1
------------------------ – X < --- . (7.9)
1 – ρG ⋅ X 2
From (7.9) we have that as long as
1
X < -------------- (7.10)
2ρ G
the compensation circuit will not make any difference. For example, if ρ G = 10 –8 , we have
that for X ≤ 7071 the compensation algorithm will, due to the limited resolution, not have any
influence on the input. For the amplitude range 7072 ≤ X ≤ 12247 we only need to add one
LSB to the signal to create the desired inverse, i.e., X' = X + 1 , for 12248 ≤ X ≤ 15810 we
need to add two LSBs to the signal, i.e., X' = X + 2 , etc. Therefore we suggest a much more
hardware efficient implementation that involves only a number of comparators and additions.
The threshold values with which the signal should be compared to is given by a function of
the conductance ratio, ρ G , and with test signals they can be continuously updated from a
RAM during DAC operation. In Fig. 7.2 we show this approach. The X i values are the thresh-
old values. With the delay element between each comparator, the circuit can be pipelined as
well. A drawback with the structure is that the number of comparators is dependent on the
size of ρ G . The smaller conductance ratio more distortion and hence more comparators. The
compensation technique is also similar to a look-up table approach where the data is stored in
tables instead of generating them with comparators [103].
If a higher resolution (word length) is available at the input and the number of comparators
Nonlinear Error Compensation 195
X A(t)
Tu Tu DAC
X1 X2 XM
Figure 7.2 Use of comparators in a hardware-efficient pre-distortion circuit.
becomes high we might instead use the series expansion of (7.8) up to the e.g. second order.
We have that
∞
X' = X ⋅ ∑ ( ρG ⋅ X )k ≈ X + ρG ⋅ X 2 . (7.11)
k=0
Now, the division can be skipped and hopefully we can still have a sufficient accurate com-
pensation algorithm. Otherwise, we can increase the number of terms used in the approxima-
tion in (7.11). Applying this compensated signal to the nonlinear system yields (again using
series expansion of (7.6) and neglecting the I u constant)
X'
I out(X ) = ------------------------- ≈ X' – ρ G ⋅ X' 2 = ( X + ρ G ⋅ X 2 ) – ρ G ⋅ ( X + ρ G ⋅ X 2 ) 2 =
1 + ρ G ⋅ X'
2 3
= X + ρ G ⋅ X 2 – ρ G ⋅ X 2 – 2ρ G ⋅ X 3 – ρ G ⋅ X 4 =
2 3
= X – 2ρ G ⋅ X 3 – ρ G ⋅ X 4 , (7.12)
where the quadratic term has been cancelled. Instead higher order terms are introduced and
this is also one of the drawbacks with some predistortion circuits. However, the higher-order
distortion terms are typically smaller than the original dominating second-order harmonic,
since for typical current sources, we should be able to guarantee that
2ρ G2 ⋅ A 3 < ρ G ⋅ A 2 ⇒ 2ρ G ⋅ A < 1 . (7.13)
In Fig. 7.3 we show the simulated output spectra for some different compensation techniques
as described above. A 14-bit current-steering DAC with a conductance ratio of ρ G ≈ 10 –7 is
used in the simulations. The input signal is a –3-dBFS single-tone.
To illustrate the pre-distortion circuit, we are only considering the single-ended output. In (b)
we show the resulting output when using the pre-distortion as given by (7.8) and truncated to
a 14-bit accuracy at the DAC input. In (c) we show the results of the proposed pre-distortion
with comparators as shown in Fig. 7.2 and in (d) we find the result when using the Taylor
expansion approach described by (7.12). We cannot use an FS signal since otherwise the com-
pensation circuits would clip the signal. We find that due to the limited resolution at the input
the distortion cannot completetly be compensated for. We also see that in case (b) and (d) give
the same result, hence the conductance ratio is low enough to make the series expansion
become equal to the inverse function (mainly due to finite resolution). The gain in SFDR is in
the order of 12 dB (2 bits of linearity). The threshold or comparator version in (c) only gives
an improvement in the order of 7 dB (1 bit of linearity). However, the hardware cost can be
Output without pre−distortion Output with inverse−function pre−distortion

0 0
−6 −6
Power [dBFS]
Power [dBFS]
−80
−92
−130 −130
0 0.125 0.25 0.375 0.5 0 0.125 0.25 0.375 0.5

Normalized Frequency Normalized Frequency
(a) (b)
Output with "comparator" pre−distortion Output with series−expansion pre−distortion
0 0
−6 −6
Power [dBFS]
Power [dBFS]
−87
−92
−130 −130
0 0.125 0.25 0.375 0.5 0 0.125 0.25 0.375 0.5

Normalized Frequency Normalized Frequency
(c) (d)
Figure 7.3 Output spectra from a nonlinear DAC without (a) pre-distortion, and (b) through (d) with
pre-distortion. In (b) we use complete inverse function, (c) comparator pre-distortion, and
(d) pre-distortion with Taylor expansion.
significantly reduced and there is no longer delay time. The SNDR is improved by a factor 3
to 4 dB. Also notice from the figures that for the (b) through (d) cases much of the distortion
is at higher frequencies that will be attenuated by the image-rejection filter if an amount of
interpolation is used.
7.2.2 Combinations and Variations on Linearization Techniques

The approaches from the previous section can or should also involve adaptive models. With a
training sequence the parameters of the model are updated. In Fig. 7.4 we have sketched this
idea for the pre-distortion as shown in Fig. 7.1 (a). The training sequence is sent through the
(nonlinear) DAC and the ADC measures the signal. The sent data together with the received
(measured) data are used to train the inverse model of the DAC. Logic circuits generate the
adaptation signal ε adapt that the pre-distortion uses to updates is models. In order to cover
problems with temperature variations, drifts, etc., regular updates and refresh of the loop are
required.
Current Source Calibration 197
DAC
eadapt
Logic ADC
Figure 7.4 Use of loops and adaptation for pre-distortion circuits.
In for example full-duplex modems there is an echo loop which can be used to measure the
quality of the ADC and DAC in the analog front-end in one CPE. However, for much better
performance, we need to co-optimize the whole system and we will leave this discussion to
future work.
Concluding, there are problems with estimating the size of the conductance ratio. We need an
ADC in a feedback loop that is accurate enough, which is expensive. We also have to take into
account the influence of the dynamic errors. This will make the pre-distortion circuit much
more complex since we need to estimate higher-order derivatives of the input signal and the
expected state of the output signal at each sampling instant. Once again, the achievable
improvement will be limited by the resolution at the input.
Instead of using training sequences, we can use the information of the signal properties. For
DMT-DSL applications the amplitude or code distribution will become Gaussian distributed
(compare with Fig. 1.12). Nonidealities will skew and transform this distribution slightly, e.g.,
change of mean value and standard deviation, and by proper methods we can extract informa-
tion on the nonlinearity by comparing the received amplitude (or code) histogram with the
expected one. In [108, 109] it is found that by using histogram methods, large improvements
in performance can be done by utilizing the information on the architecture of the device as
well.
Related work [74] involves more information on the nonlinear device (the DAC). There are
methods to use a sigma-delta feedback loop where the expected (nonlinear) settling error is
fed back [110, 111]. In Fig. 7.5 we illustrate the concept. An L th-order sigma-delta modulator
is used in the approach. The filters H (z) and G(z) are used to generate the STF and NTF.
However, instead of feeding back and shaping the truncation noise, we feed back and shape
the expected settling error. This settling error is approximated by a DAC model that is work-
ing “in parallel” with the modulator. This modulator approach has also been investigated in
related publications [74]. The advantage is that the model is described in the digital domain
and that the error is not spread out over the entire frequency domain. This allows us to gain
more in SNDR. A drawback is – as before – that we need additional feedback loops to update
the model. Another drawback is that we introduce additional poles and zeros to the system
due to more feedback loops and hence the stability must be carefully examined.
7.3 Current Source Calibration

One approach to improve the matching of the elements in the DAC is to trim or calibrate them
with a well-defined reference [9, 64, 112, 113]. In fact, since we in many applications do not
DAC
model
eexpect
X A(t)
H(z) DAC
G(z)
Figure 7.5 Use of signal-feedback sigma-delta modulators to spectrally shape the influence of nonlin-
ear errors.
care very much about offset and linear gain errors, we can at least use a reference that is com-
mon and well-defined for all elements, but the accuracy of its absolute value is of less interest.
If the calibration is to take place during operation, we need additional elements that can be
calibrated when the others are used in operation. Typically, the calibration needs to refresh the
elements at fixed time instants since otherwise the accuracy of the calibrated elements may
decrease below acceptable values, due to e.g. charge leakage or other phenomena causing the
values to fluctuate.
As an example, we highlight a common method for calibration of unit current sources [9].
Consider Fig. 7.6 where we show a unit current source biased as high-swing current mirror,
where the gate of the source transistor (M1) is connected to a switch, S 1 , and a capacitor,
C sg . This capacitor need not only to be the source-gate capacitance on M1.
Csg Csg
M1 M1
S1 S1
S2 S2
Iref Iref
f f f f
I+ I- I+ I-
(a) (b)
Figure 7.6 Example on circuit solution to calibrate the unit current sources during (a) calibration and
(b) operation phases.
During the calibration phase, the switch S 1 is closed and S 2 is connected as in Fig. 7.6 (a)
Dynamic Element Matching (DEM) Techniques 199
and in (b) the operation phase is shown. The reference current, I ref , is generated by an
NMOS current source with high output impedance. During calibration the unit current source
is connected as a current mirror and hence the source-gate voltage of M1 is determined by the
current through the source. We have
K' W
I ref = ----- ⋅ ----- ⋅ ( V SG – V T ) 2 . (7.14)
2 L
The nice property of calibration is that if we have a matching error on M1, e.g.,
W' = W + ∆W , we will force the source-gate voltage on M1 to change. The current through
the source is still the same, defined by the high-output-impedance NMOS source. Hence, we
have
K' W + ∆W
I ref = ----- ⋅ --------------------- ⋅ ( V SG + ∆V SG – V T ) 2 . (7.15)
2 L
The time to charge the capacitor, i.e., the calibration period, is determined by the on-resistance
through the switches, R sw, 1 + R sw, 2 , and the capacitor, C sg , as well as the previously stored
voltage on the capacitor.
During operation the gate of M1 will only be connected to the capacitor. However, the capaci-
tor will hold the source-gate voltage generated during the calibration phase. Due to the charge
leakage through the switch S 1 (which is implemented with a transmission gate or MOS tran-
sistor) we loose in accuracy on the gate voltage. We need to guarantee that the voltage drop is
accurate enough (which is specified by the wanted resolution of the DAC) until next time it is
calibrated. If the current sources are refreshed often enough the timing issue becomes a minor
problem. We should guarantee that the circuitry within the dashed lines are functioning as a
transparent current source.
The element calibration technique can be applied to any current-steering DAC structure with
proper designed unit (or equally) sized elements. It is though especially for the thermometer-
coded MSBs in for example a segmented DAC where we have a large number of elements
with the same value. The same applies in for example an R-2R ladder architecture where all
current sources are equally large. Alternatively, the resistors are trimmmed instead [112, 114].
The advantage of the technique is obviously that the influence of matching errors is further
reduced. The disadvantages are that additional switches are needed, which increases the lay-
out complexity and we need more digital circuits to control the calibration routine. This is to
be considered as a minor problem since the size of the digital circuits will be much smaller
than the analog anyway. For high resolutions we may need to calibrate a large number of ele-
ments. This implies that it will take longer time between every element becomes refreshed.
7.4 Dynamic Element Matching (DEM) Techniques

Unlike the calibration technique (Sec. 7.3) we use only digital circuits in dynamic element
matching (DEM) techniques. Other publications refer to DEM as operations also performed in
the analog domain, similar to that discussed in the previous section [9]. The digital input is
modified in such way that the matching errors become signal-independent, i.e., noise [10, 11,
117, 118, 119, 120, 121]. This improves the linearity significantly and as long as we use some
amount of oversampling we gain in SNDR as well. The gain in SNDR is in the order of
10 ⋅ log10 OSR dB, but if we use mismatch error shaping technique for the DACs we gain
even more [11].
First, we discuss in Sec. 7.4.1 a technique which we refer to as dynamic randomization. Using
this technique we randomly choose a set of X out of 2 N – 1 number of unit current sources to
represent the number X . To apply the DEM techniques we require that a thermometer code or
at least redundant codes are used. It is shown that by using a dynamic randomization tech-
nique we do not need to implement the binary-to-thermometer encoder.
In Sec. 7.4.2 we discuss some approaches where we combine the binary-to-thermometer
encoder with the randomization techniques. We refer to them as DEM with encoders although
they are very similar to those in Sec. 7.4.1. Due to the randomization of elements and there-
fore high switching activity, when using the DEM techniques, the glitch energy increases and
the SNDR is decreased. In Sec. 7.4.3 we describe some different methods to reduce this effect
eventhough an amount of randomization is still used.
Typically, the randomization techniques are used in lower-bit DACs and for example in the
feedback DACs in sigma-delta ADCs [10]. Related implementations illustrate the use of the
DEM technique in DACs with a larger number of input bits as well [115].
7.4.1 Dynamic Randomization

Although a careful layout strategy has been used, there will be matching errors causing distor-
tion. Since we want to keep the amount of analog circuits at a minimum, we want to cancel
the effect of the matching errors by using digital circuits only. With “cancel” we understand
that we want to change how the matching errors influence the output signal. The straightfor-
ward approach is to transform distortion into noise instead. This can be achieved if and only if
we use redundant codes in the DAC. The classical approach is to use the thermometer code
which is highly redundant, but there are other redundant codes as well. Some of these are dis-
cussed in Sec. 7.5.
The principle of dynamic randomization is sketched in Fig. 7.7. We have a binary-to-ther-
mometer encoder and a randomizer or scrambler before the thermometer-coded DAC. All
weights or elements of the thermometer-coded DAC has equal size or significance. If the
number X is to be converted, the randomizer should randomly select a set of X elements from
the total 2 N – 1 elements. With combinatorics, we see that this can be done in
( 2 N – 1 )!
 2 N – 1 = ------------------------------------------
- (7.16)
 X  X! ⋅ ( 2 N – 1 – X )!
different ways for the input X .
ctrl
N Binary-to-
thermometer Thermo.
X encoder DAC A(t)
Scrambler
Figure 7.7 Randomization of thermometer-coded bits in a DAC.

At every different sampling instant a new set of elements is reselected. The selection of sets
(with the ctrl signal in Fig. 7.7) can for example be determined by a pseudo-random binary
sequence (PRBS) generator [10], but even with a counter stepping through a number of fixed
sets good results can be achieved since the errors most likely will become uncorrelated with
the signal. If full randomization is needed, hence if each set of elements should be chosen
with equal probability, the size and complexity of the randomizer grow more than exponen-
tially with the number of bits, N . The largest number of sets to select is found at X = 2 N – 1
N
and this is a huge number, approximately 22 using Stirlings formula.
Nevertheless, in the following discussion consider the case with full randomization. Assume
that each element has a static, absolute mismatch error of δ k , k = 0, …, 2 N – 1 . With the
randomizer we will for the same input have different matching errors at different sampling
instants, e.g., with the input code X = 1 , we may get the output sequence of varying ampli-
tude levels; A ( n )(X = 1) = 1 + δ 10 LSB, A ( n + 1 )(1) = 1 + δ 31 LSB, etc. The effective long-
term matching error will be given by the average of all matching errors. For a fixed X we find
the time-average of the output amplitude as
M
1
A ( m )(X ) = lim -----
M → ∞M
∑ A ( m )(X ) . (7.17)
m=1
For full randomization, we will for e.g. X = 1 get the expected output
2N – 1
1
Em { A ( m )(1) } -⋅
= 1 + --------------
2N – 1 ∑ δ k LSB. (7.18)
k=1
For an arbitrary input X , we get

2N – 1 2N – 1
X  1 
E m { A ( m )(X ) } = X + --------------
N
2 –1
-⋅ ∑ k δ = X ⋅ -⋅
 1 + --------------
 N
2 –1 ∑ k = X ⋅ ( 1 + δ ) LSB,
δ
k=1 k=1
(7.19)
where δ is the mean matching error on all bits. From (7.19) we see that the average absolute
error is increasing with increasing input X , but the average relative error is kept constant.
Hence, we will transform the matching errors so that they in average will behave as a linear
gain error. Since there will be different amplitude levels at different sampling instants,
although the input code is the same, there will be additional noise.
In Fig. 7.8 we show the simulated averaged output spectra of an 8-bit DAC with randomly
distributed 10-% matching errors applied to the 255 unit elements. In (a) we find the original
output and in (b) the output with full randomization. The distortion terms are clearly sup-
pressed to the cost of a higher noise floor, i.e., the SFDR is improved, but not the SNDR up to
half the update frequency. However, the randomization technique is mostly used in an interpo-
lation or oversampling DAC where we only consider the bandwidth up to f u ⁄ ( 2 ⋅ OSR ) ,
where OSR is the oversampling ratio. Assuming ideal filtering, the improvement in SNDR
becomes more obvious and the gain is approximately 10 ⋅ log10 OSR dB.
Another observation is that with the randomizer we do not need to put too much effort on the
design of the binary-to-thermometer encoder. The encoder can be implemented as illustrated
in Fig. 7.9 for a 4-bit DAC, since the randomizer will scramble the bits anyway. The MSB is
Thermometer−coded DAC output Randomized thermometer−coded DAC output

0 0
−6 −6
PSD [dB/Hz]
PSD [dB/Hz]
−50 −50
0.55 1.1 0.55 1.1

(a) (b)
Figure 7.8 Averaged output spectra from an 8-bit thermometer-coded DAC (a) without and (b) with
randomization.
simply connected to 2 N – 1 inputs of the randomizer, the second MSB to 2 N – 2 inputs, etc.
b3
b2
b1
Figure 7.9 Simple binary-to-thermometer encoder to be used before the randomizer.
The randomizer can be implemented by using a number of multiplexers that are intercon-
nected and controlled by the PRBS as we see in the following sections. The PRBS determines
which input that should be mapped to a certain output, etc.
The randomization techniques increase the switching activity in the DAC and the glitching
increases. In fact, for the thermometer case, we basically destroy the low-glitch properties.
Hence we have to find a trade-off between the improvement in dynamic range and the
increased glitch energy. In Sec. 7.4.3 we present some techniques to introduce randomization
that keep the glitches at a minimum at the same time.
7.4.2 Dynamic Element Matching (DEM) with Encoder

In Fig. 7.9 we showed one way to relax the design of the encoder before the randomizer to a
minimum. However, still the randomizer has 2 N – 1 inputs and 2 N – 1 outputs which not is a
very hardware efficient implementation. The randomizer can be combined with the encoder in
a tree-like structure, similar to the one discussed in Sec. 5.3.3. In this section we discuss some
of these combined approaches. We will not show simulation results since these are presented
in related publications [115, 116] and the final results are similar to those presented in Fig.
7.8.
Full-randomization DEM (FRDEM)

The full-randomization dynamic element matching (FRDEM) structure generates a full ther-
mometer code (no segmentation) and all possible subsets of elements are chosen with equal
probability [10]. The structure is a straight-forward binary tree approach as shown in Fig.
7.10. We have an ( N + 1 ) -bit binary input word to the tree. These N + 1 bits consist of the
N -bit true input signal and an additional (“dummy”) LSB which is set to 0. At each node in
the tree there is a switching block, S n, k , where n = 1, …, N denotes the layer number and
k = 1, …, 2 n – 1 numbers the switching blocks in each layer, i.e., in the n -th layer of the tree
we have K = 2 n – 1 nodes or switching blocks. Each switching block generates two
( N – n + 1 ) -bit outputs from a single ( N – n + 2 ) -bit input. Each switching layer also
requires a set of control signals, s n, k . Hence in the last, N -th layer we have 2 N – 1 ⋅ 2 = 2 N
one-bit outputs, which is the thermometer code. These outputs are fed to the vector of one-bit
DACs whose outputs are summed and generating the desired amplitude level.
1-bit
N-1 2 DAC
SN,1
1-bit
S2,1 DAC
N
N-1
N+1 A(t)
X S1,1
0
N-1
N
S2,2 1-bit
2 DAC
N-1 SN,K
1-bit
DAC
Figure 7.10 Block view of a full randomization DEM architecture.
The purpose of the switching blocks is to distribute the generated bits through the tree and to
add the random properties to the signal. In Fig. 7.11 we show a switching block from the n -th
sn,k
MSB
N-n+2 N-n+1
LS
Bs
N-n+1
Figure 7.11 Switching block used in randomization trees.

layer in detail [10]. The MSB from the ( N – n + 2 ) -bit input is copied to the ( N – n + 1 ) -bit
output in one branch and the remaining N – n + 1 LSBs are copied to the other branch. The
control signal, s n, k , determines to which branch the MSBs should be copied, etc. If we let the
control signals be constant, e.g., 0, we have built a binary-to-thermometer encoder of the sim-
ple and inefficient kind as shown in Fig. 7.9. However, if we let the control signal be given by
a PRBS, the randomization is added to the tree and hence we have combined the randomizer
(or scrambler) with the encoding circuits.
For larger number of input bits the tree will become very large and hence we can use the con-
cept for the MSBs in a segmented DAC. Another option is to use DEM in an oversampling
DAC with sigma-delta modulator where the number of bits representing the signal is reduced.
A third approach is to limit the depth of the tree and use multi-bit DACs instead of the vector
of one-bit DACs.
Partial-randomization DEM (PRDEM)

The complexity of the encoding tree increases exponentially and for higher number of bits the
tree may become too large. Therefore, one solution is to use so called partial randomization
DEM (PRDEM) [10]. In this approach we terminate the tree at the L th layer and we use a
vector of 2 ⋅ 2 L – 1 ( N – L + 1 ) -bit DACs. See Fig. 7.12 for illustration of the limited tree.
N-L+1
(N-L+1)-bit
N-L DAC
N-1
SN,1
(N-L+1)-bit
S2,1 DAC
N N-L+1
N-1
N+1 A(t)
X S1,1
0
N-1
N
N-L+1
S2,2 (N-L+1)-bit
N-L DAC
N-1 SN,K
(N-L+1)-bit
DAC
N-L+1
Figure 7.12 Block view of a partial randomization DEM architecture.
The type of switching blocks can be identical to the ones used for FRDEM and as shown in
Fig. 7.11. If the switching sequence is kept constant, we will with L layers have implemented
a DAC with an L -bit segmentation. However, still of the kind shown in Fig. 7.9.
In this architecture a lower amount of randomization will be introduced since the DACs con-
tain more elements that cannot be dynamically matched internally. The lower number of lay-
ers, L , the less do the distortion terms become cancelled. However, with reasonably large
matching errors it can be shown that the distortion terms in for example a 14-bit DAC can be
reduced significantly by only using 3 or 4 layers [116].
Noise-shaping DEM (NSDEM)
The major advantage with the trees as shown in the previous is that we can add a smarter
switching sequence to the switching blocks. In fact, we may use a signal that is generated by a
sigma-delta modulator and well-chosen input signals. With this approach we are able to spec-
trally shape the error (or noise) power arising from the cancelling of the distortion. This is
referred to as noise-shaping DEM (NSDEM [11] and with this method the achievable SNDR
within the signal band can be increased dramatically. The switching tree is identical to the one
in Fig. 7.10, but the switching blocks differ [11]. The switching blocks can be generalized and
designed to realize an n th-order modulator. However, to perform the noise shaping we need
information on the signal for the switching bit (compare s k, n ) that is no longer chosen in a
completely random manner. This will therefore increase the hardware cost, since we require a
separate noise-shaping modulator for each single switching block. There are techniques sug-
gested for hardware efficient solutions [11, 117].
Performance comparison
In related work [115, 116] comparisons between the different approaches as described above
are been presented. It is shown that one problem with the PRDEM and FRDEM structures is
that they spread the noise throughout the frequency domain and since we do not gain in
SNDR we may actually get a worse result within a certain frequency range. This is since for
some frequencies the distortion terms will be outside the specific frequency range. It is shown
that only a few layers are required in a PRDEM structure to reach reasonable accuracy. For
example, for a 14-bit DAC with 1.5-% matching errors of the unit current sources, a 4-layer
PRDEM structure is enough to suppress the SFDR to not limit the 14-bit linearity. Further, it
is shown that the NSDEM structure has the best performance. This should also be the struc-
ture to choose when we have an oversampled DAC where the signal frequency is limited to a
small frequency range of the DAC. The disadvantage is the obvious cost in terms of hardware
and power due to the required sigma-delta for each switching block in the DEM tree.
7.4.3 Dynamic Randomization with Reduced Glitching

In terms of static linearity and resolution the previously described DEM techniques show
good behavior. However, due to the randomization the switching activity increases signifi-
cantly and hence the glitch energy increases. The good low-glitch property of the thermometer
code is destroyed. In order to both gain in randomization and keep the glitches at a minimum,
the encoder and randomizer need to consider the previous selected set of unit elements (or
multi-bit DACs) before it generates a new set. Assume that we have a 4-to-15 binary-to-ther-
mometer encoder with the randomizer. For the number X = 7 we may have generated the
vector
s 15, s 14, …, s 1 = 110010111001000 (7.20)
to the vector of one-bit DACs. If the code increases from X = 7 to e.g. X = 9 we do not
want to select 9 random bits out of all 15. Instead we only want to select 2 unit elements from
those who where not activated during the previous state. In this case we should therefore ran-
domly select from the set of
s 13, s 12, s 10, s 6, s 5, s 3, s 2, s 1 (7.21)
that was unused before the switching instant. In Fig. 7.13 we show a straightforward approach
to solve the problem [124]. The signal indicated by solid-dashed lines are thermometer-coded.
We take the input, X (n) , and subtract it from its previous value, X (n – 1) . This difference
( ∆X (n) ) is checked wheter it is larger or smaller than 0 (i.e., the sign bit is extracted) and we
also create the absolute difference value. The flag determining the sign of the error is fed to a
multiplexer that is selecting the old output value, Y (n – 1) , or its bitwise inverse. The absolute
difference value is used to control how many bits that should be scrambled (randomized). The
scrambler will randomly select ∆X (n) of the inputs that are set to “1” and feed these
through. All other outputs are set to “0”. The output of the scrambler is then XOR added with
the old output Y (n – 1) to generate the new output Y (n) .
X(n)
T |X| Scramble Bitwise
X(n-1) DX(n) inverter
Bitwise
XOR add
T
Y(n)
Figure 7.13 State-controlled DEM to minimize glitches.
Assume for example that we have a 3-bit converter and that the new input is X (n) = 3 and
the old was X (n – 1) = 5 . The previous thermometer output was Y (n – 1) = 1011101 . The
difference becomes negative with an absolute value of ∆X (n) = 2 . The multiplexer will
now select the noninverted input and the scrambler will select two of the bits that have non-
zero values. All others are set to “0”. Assume that the output becomes 1001000. This value
should then be added by bitwise XOR operation to the previous output and we get the final
output value Y (n) = 1001000 + 1011101 = 0001101 .
We understand that the circuit becomes large and complex for larger word lengths. Therefore,
we should seek ways to implement the circuit through a tree structure or similar. First, we
highlight the concept of generalized cubic networks (GCN).
Generalized cubic network (GCN)

One of the drawbacks with the DEM techniques described above are that they for low varia-
tions in the random signals work as the “simple” binary-to-thermometer encoder in Fig. 7.9.
Another drawback, especially for the PRDEM structure, is that to achieve a good immunity
towards graded matching errors the routing of interconnection wires becomes complex. One
approach to circumvent these obstacles is to use a structure similar to the iterative segmenta-
tion circuits shown in Fig. 5.17 and Fig. 5.18. In this context we discuss the generalized cubic
networks (GCN) [120, 121] and in Fig. 7.14 we show an example of a simplified GCN. We
have used a “simple” encoding circuit to generate a thermometer code at the input. The gener-
alized version allows a true thermometer coded input. Further we use a number of transmis-
sion gates (or the and-or pairs) in 2-to-2 muxes, S n, k , where the states of the muxes are
determined by a number of control signals, s n, k , where n = 1, …, N and k = 1, …, 2 N – 1 .
We can choose to apply equal control signal for each layer as well, i.e., c n, k = c n . If we let
the control signals be random (or pseudo-random), we get a random data path through the cir-
cuit. Since the bits will interleave through the tree more or less by them selves, we will have a
good immunity towards graded errors as well.
s1,1 s2,1 s3,1

0 t1
b0 t2
s1,2 s2,2 s3,2
b1 t3
t4
s1,3 s2,3 s3,3
b2 t5
t6
s1,4 s2,4 s3,4
t7
t8
Figure 7.14 Segmentation and scrambling 3-to-7 binary-to-thermometer encoding circuit implemented
by a GCN.
Dependent on implementation, we need not, unlike the DEM structures from the previous sec-
tions, to feed all bits through the entire tree (as in Sec. 5.3.3). We can also terminate the tree
“from the other direction” than in the PRDEM. Hence, we feed forward the K LSBs to layer
K + 1 and distribute them together with the MSBs to the muxes in an interdigitized way simi-
lar to that of Fig. 7.9. In terms of partial randomization we can choose to add the GCN for the
MSBs only.
Hardware Efficient dynamic randomization with reduced glitching

A hardware efficient approach to solve the problem with glitches is presented in related work
[123, 124]. The purpose with this approach is to combine the tree-structured encoder (as illus-
trated in Fig. 7.14), with the randomization, and glitch reduction. Instead of saving the states
of selected sets and comparing the consecutive codes as in the approach above, the objective
is now to save the data path through the tree. For this purpose, we modify the switching
blocks as is illustrated in Fig. 7.15 and each block follows a decision table as shown in
Table 7.1. Once again, we find in the figure the and-or pair and if no randomization is applied,
the outputs x n, k and y n, k are selected as a n, k and b n, k , respectively. The operation of the
block is simple; if the bit has changed its value, we use a random switch signal, s n, k , to
choose one of the outputs. In related work [122, 123, 124] simulation results show the
improvement with the two proposed techniques compared to other techniques.
sn,k
D
wn,k
zn,k
an,k xn,k
an,k
yn,k
bn,k bn,k
Figure 7.15 Hardware-efficient switching block for glitch reducing in DEM.
α β a b w z Comment on selection of x and y
Randomize paths, i.e.,

0 0 0 0 0 s
switch x and y according to z = s
Keep previous paths, i.e.,
0 1 0 1 1 z'
switch x and y according to old set value z = z'
Keep previous paths, i.e.,
1 0 0 1 1 z' switch x and y according to old random value
z = z'
Randomize paths, i.e.,
1 1 1 1 0 s
switch x and y according to z = s
Table 7.1. Decision table for hardware efficient DEM.
7.5 Special Codes in DACs

In this section we discuss some different codes in and aspects of DACs. As we have found in
previous chapters and discussions we need redundant codes to be able to randomize the
weights in order to suppress the distortion terms. Hence, we need a code where a number of
weights are equal or in generalized terms, we should be able to find two (or more) disjunct
subsets of the weights where their summed contributions are equal. Then, we have the possi-
bility to let the converter to randomly choose one of the subsets. For the further discussion in
this section we use the notation w m = w(m) for the weight corresponding to the m -th bit. We
consider different redundant representations for an N -bit binary input, hence we require that
Special Codes in DACs 209
M
∑ wm ≥ 2 N – 1 . (7.22)
m=1
One code that fulfils this relation with equality is the thermometer code, where w(m) = 1 for
m = 1, …, 2 N – 1 . We have a high degree of flexibility when chosing the subsets. Another
solution is to segment the input, hence, we have w(m) = 2 m – 1 for the K LSBs, but
w(m) = 2 K for the N – K MSBs. Further, we can point out the rather naive case of using two
parallel DACs where the two inputs are chopped, etc. A drawback with using the full ther-
mometer-code representation is that the digital hardware becomes large for higher resolutions.
To keep the amount of hardware low, we prefer segmentation instead. With shrinking dimen-
sions though, this cost measure becomes of minor interest. Still, however, we want to keep the
power dissipation low.
In terms of glitching, the thermometer code is optimal since the number of bits switching
between two consecutive samples as the input is ramped is minimum. In those terms, the
binary code shows the worst behavior. In between these two extremes, we once again find the
segmented code.
In Sec. 7.5.1 we present the studies on linear-coded DACs. We investigate a code that is some-
where in-between the full thermometer code and the binary code. The design issues are to
minimize glitches, to allow a fairly easy layout technique, and redundant code for randomiza-
tion techniques.
In Sec. 7.5.2 we discuss the commonly known signed-digit code which is suitable in for
example current-steering DACs where we can use both NMOS and PMOS current sources to
generate positive and negative output currents.
In an implementation of the current switches it is likely to get a switching time instant that is
dependent on the previous value applied to the switch. This switch memory, or dependency
can be reduced by using a return-to-zero code (R2Z) where the state of the switches is reset
each update period. This is further discussed in Sec. 7.5.3.
7.5.1 Linear-Coded DACs

In Chapter 2 we find a summary of different codes that are/can be used for D/A conversion
and in Chapter 3 we found some different techniques to realize the converters for different
codes. In our work, we have investigated some codes that are between the full thermometer
code and the binary code [32, 33, 34, 35]. The full thermometer code shows a high order of
redundancy whereas the binary code is not redundant at all. For the linear code, we have
w m = w(m) = m for m = 1, …, M . (7.23)
M must be large enough so that the inequality of (7.22) is met (to be able to represent a full-
scale signal). We get
M M
M ⋅ (M + 1)
∑ w(m) = ∑ m = ----------------------------- ≥ 2 N – 1 .
2
(7.24)
m=1 m=1
This gives the approximate value on M

N+1
2N + 3 – 7 – 1 -------------
M = ----------------------------------- ≈ 2 2 (7.25)
2
We require that M should be an integer, and to fulfil (7.22) we need
N+1
-------------
M = 2N + 3 – 7 – 1 = 2 2 . (7.26)
-----------------------------------
2
The linear code is obviously redundant. For example, we can represent the number 6 in four
different ways, e.g., 6 , 5 + 1 , 4 + 2 , or 3 + 2 + 1 . Hence, we can apply randomization tech-
niques. In Fig. 7.16 we illustrate the number of weights for different codes and varying num-
ber of input bits. We see that the number of weights for the linear code is lower than for the
thermometer and more than for the binary code. For a 14-bit input, the number of weights in
the linear-coded DAC becomes M = 181 .
Number of weights for different codes
4
10
er
et
om
m
er
3
Th
10
No. of weights
2
7−bit segm.
10 6−bit segm.
ar
Line
1
10
Binary
0
10
1 6 8 10 14
No. of binary bits
Figure 7.16 Total number of weights for different codes in DACs as function of the number of bits.
Weight distribution
Roughly, the issues of minimizing glitches, allowing regular layouts, and redundancy all end
up in a code that is as “dense” as possible. Hence, we do not want the weights, w m , to spread
to much between the MSB and LSB. If the weights are too unequal, there will be problems
with glitches and matching. The variance of the weights, σ w2 , gives us a measure on the den-
sity of the code
K
1
∑ ( wk – w ) 2
2
σw = ---- ⋅ (7.27)
K
k=1
where K is the number of weights and w is the mean weight as

K
1
w = ----
K ∑ wk . (7.28)
k=1
For the binary code, we get for example
N
1 2N – 1 2N
wB = ----
N ∑ 2 m – 1 = --------------- ≈ ------
N N
(7.29)
m=1
and
N
1 2 N 2
 2 m – 1 – ----- N–3
∑
2
σ wB = ---- - = 2 2N ⋅ ------------
-. (7.30)
N  N  3N 2
m=1
For the thermometer code, we get

2N – 1
1
∑
2
wT = --------------
N
- 1 = 1 and σ wT = 0 . (7.31)
2 –1
m=1
Since all weights are equally large, there is no spread and hence the variance is zero. For the
linear code, we get
M N–1
1 M ⋅ (M + 1) M + 1 M -------------
w L = -----
M ∑ m = ----------------------------- ≈ -------------- ≈ ----- ≈ 2 2
2M 2 2
(7.32)
m=1
and
M
1 M + 1 2
 m – ------------- ( M + 1 ) ⋅ ( M + 1 ⁄ 2 ) ( M + 1 )2 M 2 2N – 1
∑
2
σ wL = ----- - = -------------------------------------------------- – ---------------------- ≈ ------- ≈ ------------- . (7.33)
M  2  3 4 12 3
m=1
Comparing (7.33) with (7.30) tells us that the linear code for all number of bits has a lower (or
equal to for N = 1, 2 ) standard deviation. However, we can compare the result with the seg-
mented converter in stead. For thise case, we will for a K thermometer coded MSBs get the
average weight
N–K 2K – 1
1   2N – 1
w S = -----------------------------------
N – K + 2K – 1 
-  ∑ 2m – 1 + ∑ 2 N – K = -----------------------------------
 N – K + 2K – 1
- (7.34)
m=1 m=1
and the variance

N–K 2K – 1
1  
∑ ∑
2
σ wS = -----------------------------------
-  ( 2m – 1 – wS ) + 2
( 2 N – K – w S ) 2 ≈
N – K + 2K – 1  
m=1 m=1
N–K–2
≈ 2 2N – K ⋅ ----------------------------------
-. (7.35)
( N – K + 2K )2
For example, for a 14-bit converter, we would for the binary converter get a standard deviation
of 2326 and for the linear converter only 52. However, for a 6-bit segmentation we get 73, for
a 7-bit segmentation about 25. Hence, heuristically, for the 14-bit binary converter, we need to
segment at least 6 or 7 bits to achieve the same performance as the linear-coded converter. We
may also consider the number of weights in the different cases. For the binary case, we get 14
weights, for the linear code, we have 181, for the 6- and 7-bit segmentation, we get 61 and
134, respectively.
Encoder complexity
The complexity of the encoders for segmented circuits and thermometer circuits is to be con-
sidered as rather low. We can implement them with incremental trees and use straight-forward
pipelining, since there is no feedback loops.
For the linear code, the encoder becomes somewhat more complex. The selection of weights
can be done using the algorithm in Figure 3.12 on page 68. Consider the 4-bit (binary) case in
Fig. 7.17 (a) which for the linear code give 5 weights. (We have used circles to also illustrate
the use of several unit elements to create a weight, i.e., for weight w 4 = 4 we use four unit
weights). An un-filled circle denotes unused weights, whereas the filled circle indicates a used
weight. Using the algorithm from Chapter 3 will start by selecting the weights from MSBs
and down. For example, if we want to represent the number 10, the algorithm will start with
selecting the MSB, w 5 , then compare compare next weight, w 4 , with the residue 10-5 = 5,
etc. The result is found in Fig. 7.17 (b).
w5 w5
w4 w4
w3 w3
w2 w2
w1 w1
(a) (b)
Figure 7.17 Illustration of (a) the 5 linear-coded weights in a 4-bit converter and (b) representation of
the number 10. Un-filled circles represent unused unit weights.
The selection algorithm is an iterative solution, but it can be divided into subalgorithms to the
cost of more hardware. Further, it can be pipelined, which will introduce a delay through the
encoder. Especially, for larger number of weights (181 for the 14-bit converter) the delay will
be high as well as the occupied chip area and power consumption. Hence, it is not a very effi-
cient solution.
Another solution to the encoder involves the use another type of residues than for the case
above. It is described in related publications [125]. The approach requires a square-root circuit
and the number of gates is in the order of three times as many as for the corresponding 7-bit
segmentation solutions.
Glitch performance
To compare glitch performance of differently coded DACs, we approach the problem in two
ways. In the first case we ramp the input and investigate the largest glitch and in the second
case, we apply a DMT signal and investigate the normalized glitch power. As glitch model we
use a rough approximation where we have considered the absolute sum of the weights corre-
sponding to the bits that switch between consecutive values.
In Fig. 7.18 we show the simulated glitch for a ramped input for a (a) binary-weighed and (b)
linear-coded 14-bit DAC. Notice the different scales on the magnitude axes. We find the maxi-
mum glitches to be 16383 and 361, respectively. We see that for the binary-weighted DAC the
maximum glitch is around DC (8192) and for the linear-coded DAC the glitch at DC is in the
order of 220 to 260.
Glitches in 14−bit binary−weighted DAC Glitches in 14−bit linear−coded DAC
16384 361
Normalized glitch level

242
8192
122
4096
0 0
4096 8192 12288 4096 8192 12288
Input code Input code
(a) (b)
Figure 7.18 Simulated glitch behavior for a ramped input in (a) binary-weighted and (b) linear-coded
DAC.
The largest glitch for the binary case (with the given glitch model) is given by
2N – 1 ≈ 2N (7.36)
since we find the glitch around the DC level. For the linear code, the largest glitch is found
when the largest and second largest weight are turned on/off. Hence from 010...000 to
100...000. This glitch is given by
N+3
-------------
2M – 1 ≈ 2 2 . (7.37)
For the 14-bit converter, we get for the binary case a maximum glitch of approaximately
16000 and for the linear case, we get around 360. For a K -bit segmented DAC the largest
glitch must be given by
2 ⋅ 2N – K – 1 ≈ 2N – K + 1 . (7.38)
The binary-weighted has obviously a worse glitch behavior, but we should compare the seg-
mented with the linear-coded. Comparing (7.37) with (7.38) gives that the linear-coded DAC
has better glitching behavior as long as
N+3
------------- N+1 N–1
2 2 < 2 N – K + 1 ⇒ ------------- < N – K ⇒ K < ------------- . (7.39)
2 2
For example, if N = 14 and K < 6 , we have a better glitch performance in the linear-coded
DAC.
The ramped input is however not a typical signal for our intended applications. Instead, we
show in Fig. 7.19 the simulated normalized glitch power when a DMT signal has been applied
to binary-weighted, linear-coded and segmented DACs where the number of segmented bits
has been varied. The PAR is approximately 2.7 and the nominal resolution is 14 bits. Each
tone has a –27-dBFS amplitude. We find that the linear-coded DAC is better than the others,
as long as the number of segmented bits is lower than 7. We also find that above these limit
the gain in using more bits in the segmentation does not improve performance significantly.
Estimated glitch power with multi−tone input
0
Binary weighted
Normalized power [dB]
−6
Segmented
−12
Linear coded
−18
1 2 3 4 5 6 7 8
Number of segmented MSBs
Figure 7.19 Simulated normalized glitch power for different DAC configurations.
Dual linear-coded approach

Other solution to the encoder and glitch behavior is found by investigating the behavior of the
linear-coded DAC in Fig. 7.18 (b). We see that there is no symmetry around the DC level.
Symmetry can be achieved by also investigating the complementary weight selection algo-
rithm.
First, consider the representation of the number 10 shown in Fig. 7.20 (a). This set of selected
weights is found by using the dual selection algorithm, i.e., instead we find the representation
for the number X max – X and then invert all weights. In our case, we have X max = 15 and
X = 10 , and we let the algorithm find the number 5 instead. Notice that we now are able to
speed up our selection algorithm by a factor 2, since we can compare the input code X to half
the full-scale ( X max ⁄ 2 ) . If it is higher than this threshold, we choose the dual algorithm and
if it is lower, we use the original.
A symmetric transfer function can be achieved by constructing the DAC using two subcon-
verters. Both converters get equally many weights, but they use only one of the two different
selection algorithms. We let one of the subDACs get the input X' = ( X – 1 ) ⁄ 2 and the
other gets X'' = X ⁄ 2 . The outputs are summed. In Fig. 7.20 (b) we show the simulated
glitch magnitude when ramping the input for a 14-bit DAC. Now, the maximum glitch has
decreased from 361 to 242 instead and are centered around DC ( X = 8192 ) . Around DC the
glitches are in the order of 170 instead of 240.
Glitches in 14−bit dual linear−coded DAC
361
w5

w4 242
w3
w2
121
w1
0
4096 8192 12288
Input code
Figure 7.20 (a) Complementary or the dual representation of the number 10 and (b) simulated glitch
behavior for a ramped input in dual linear-coded DAC.
Layout consideration
Another reason for looking into the linear-coded DAC is the layout issues. The original ideal
with the linear code was to design a DAC with an encoded-matrix layout as examplified in
Sec. 5.2.3, but with less digital circuitry within the unit current cells. The usual approach
needs several wires and supply interconnections to realize the cells [59, 63]. This will provide
us with a nearly optimum flexibility since the matrix is encoded to a unit cell approach. We
understand that by leaving the unit cell approach and choosing a triangular structure, we can
skip some of the selection wires in the matrix. Therefore we can reduce the amount of
induced digital noise and the layout complexities (i.e. matching) since there are less wires to
route. However, leaving the unit-cell approach will increase glitches and in some sense limit
the achievable matching. Therefore the investigations in the previous subsections were needed
to understand the impact on performance.
7.5.2 Signed-Digit Coded DACs

We briefly study a DAC architecture were we have access to “negative” and “positive” cur-
rents (i.e. current sources and sinks), e.g., PMOS and NMOS current sources/sinks [9, 36, 64].
Consider the concept illustrated in Fig. 7.21 where we have the sources directing current from
the positive supply to the output, I + , and sinks directing the current to the negative supply, I – .
In this illustration, the converter is assumed to be thermometer coded since all current sources
are equally large. With K P sources and K N sinks we will allow the input X to be in the range
[ – K N , K P ] . The output current is defined as
I out = I + – I – = I u ⋅ ( X P – X N ) , (7.40)
where X P is the code applied to the sources and X N is the code applied to the negative
sources. Since negative values can be represented by only switching the NMOS current
sources and vice versa the signed-digit code is a natural choice [9, 64]. In that case, we have
one sign bit and the magnitude. With the sign digit we choose whether to use sources or sinks
and the magnitude determines the number of sources/sinks that should be connected to the
output.
Iu Iu Iu
I+ Iout
I-
Iu Iu Iu
Figure 7.21 Use of signed-digit coded DAC.
However, we can extend the use of the code since we have a higher degree of freedom in the
choice to convert the number X . For example, if we want to go from a larger value to a
smaller we can choose to either turn some sources off or turn additional sinks on. This is also
obvious from (7.40). This property allows a smarter switching sequence for reduced glitch
energy, especially if the sources/sinks are binary weighted. For example, if we want to reduce
the output by one LSB from the state
[ X P(n), X N (n) ] = [ 10…00, 00…00 ] (7.41)
we can choose
[ X P(n + 1), X N (n + 1) ] = [ 10…00, 00…01 ] (7.42)
instead of
[ X P(n + 1), X N (n + 1) ] = [ 01…11, 00…00 ] (7.43)
and in this case the glitch is reduced to a minimum. For larger number of bits the encoder will
however become complex, since we need to remember the previous states in a similar way as
was illustrated in Fig. 7.13.
Another issue is the output impedance of the converter which has shown to influence the sin-
gle-ended case. In our case, we have – analog to the discussion in Chapter 4 – from (7.40) that
the output conductance is given by the total amount of current sources connected in parallel.
Hence looking in at the output node, gives the total conductance of
G out = G u ⋅ ( X P + X N ) . (7.44)
If we do not use any coding like the ones described by (7.42) we will have a maximum output
conductance at the peak amplitude values, X N = K N and X P = K P , and minimum at the
DC. The maximum value will be G u ⋅ K P or G u ⋅ K N and the minimum will be zero. Approx-
imately, the output conductance will influence the result in a similar way as found in Chapter
4. Using the concept described by (7.42) implies that we can modify the output conductance
slightly and make it become distributed in a different way, but still the largest output conduc-
tance is found at the peak amplitude values.
7.5.3 Return-to-Zero Code

The behavior and characteristics of the current switch is naturally dependent on the voltage
applied to its gate, but also on previous sampling instants due to the memory function of e.g.
capactive elements. To reduce the effect of this effect, one can apply a return-to-zero (R2Z)
code [67, 121]. The signals controlling the switches will now be reset within each clock
period, e.g., the voltage on the gate is to one of the supplies. This is managed by for modulat-
ing the switching signals by a 1/0-sequence alternating at with the same speed as the clock.
Typically, this sequence is equal to the clock itself. We also have to design the DAC for higher
speed, since the requirements on settling, etc., increases. Since the output returns to a reset
voltage, we make the switches (and the DAC) less sensitive to settling errors that are depen-
dent on previous sampling instants. In Fig. 7.22 we have illustrated the concept. The latched
switching signal, φ , is multiplied by s R2Z and we get the R2Z output as the XOR of those
two
φ R2Z = φ ⊕ s R2Z . (7.45)
In the figure, we have skewed the signals slightly to illustrate the operation. As one realizes
from the operation, we can also consider the usage of an R2Z code as an interpolation by a
factor of two, since we increase the update frequency and pad a zero in-between each sample.
This will also give a lower sinc attenuation of the output spectrum.
clk sR2Z fR2Z f
f fR2Z
D
Figure 7.22 Illustration (a) of the return-to-zero code and (b) its effect on the output signal.
8 Appendices
8.1 Introduction
In these appendices we present some of the derivations of the expressions in mainly Chapter
4. In App. 8.2 we present the derivation in the gain by using noise shaping. In App. 8.3 we
deal with the models that consider output conductance of the unit current sources in the cur-
rent-steering DAC. We find formulas on the SNDR and SFDR as functions of the output con-
ductance for single-ended and differential outputs. App. 8.4 discusses how the waveforms of
the more significant bits for a sinusoid input have their Fourier components distributed
throughout the frequency domain. This is used to find the expression on the SFDR and SNDR
as function of the matching error.
8.2 Resolution Improvement Through Noise Shaping

We find that we can gain in performance by increasing the update frequency in a D/A con-
verter. In dB, this gain is in the order of 10 ⋅ log10 OSR where OSR is the oversampling ratio.
Some of the LSBs are thrown away and the increased truncation noise is spread throughout
the frequency domain. If the frequency range is large enough to suppress the noise PSD
within the signal band to the desired level, we can reach a higher performance by using a
lower-bit DAC. The resulting signal is a version of pulse code modulation, hence we represent
a certain amplitude level by the average of several amplitude levels. To reach very high reso-
lution the OSR needs to be extremely high and instead we prefer to use noise shaping where
the truncated signal (or the truncation error) is fed back in a filtering loop rather than “thrown
away”. This is done by a modulator and we assume that for an L th order modulator the ideal
noise transfer function (NTF) is given by
NTF(z) = ( 1 – z –1 ) L (8.1)
where L also is the order of the filtering function. In reality, we would require additional
zeros and poles that are not placed on the unity circle for higher-order modulators for stability.
The quantization noise power within the signal frequency band, from 0 to π ⁄ OSR , can be
found by investigating the magnitude function on the unity circly. We have
219
220 Appendices
π
-----------
OSR
π
P q( L )(-----------) =
OSR ∫ NTF(e jωT ) 2 dωT . (8.2)
0
Using (8.1) in (8.2) gives that

π
-----------
OSR
π ωT
P q( L )(-----------) = 2 2L ⋅ ∫ sin2L  -------- dωT . (8.3)
OSR  2 
0
From trigonometric formulas we know that
1 n–1
∫ sinn ax dx = – ------ ⋅ sinn – 1 ax ⋅ cos ax + ------------ ⋅ ∫ sinn – 2 ax dx .
na n
(8.4)
This can be applied to (8.3) where we let x = ωT
x 2 2L x x 2L – 1 x
2 2L ⋅ ∫ sin2L --- dx = – -------- ⋅ sin2L – 1 --- ⋅ cos --- + 2 2L ⋅ --------------- ⋅ ∫ sin2 ( L – 1 ) --- dx = …
2 L 2 2 2L 2
2 2L x x 2L – 1 x
… = – -------- ⋅ sin2L – 1 --- ⋅ cos --- + 2 2 ⋅ --------------- ⋅ 2 2 ( L – 1 ) ⋅ ∫ sin2 ( L – 1 ) --- dx = …
L 2 2 2L 2
2L – 1 x 2 2L x x
… = --------------- ⋅ 2 2 ( L – 1 ) ⋅ ∫ sin2 ( L – 1 ) --- dx – -------- ⋅ sin2L – 1 --- ⋅ cos --- . (8.5)
L⁄2 2 L 2 2
The equation in (8.5) can be written as an iterative function where L is the sequence index.
We get
(L) 2L – 1 ( L – 1 ) 2 2L x x
P q (x) = --------------- ⋅ P q (x) – -------- ⋅ sin2L – 1 --- ⋅ cos --- (8.6)
L⁄2 L 2 2
or
(L) 2L – 1 ( L – 1 ) 2 2L – 1
P q (x) = --------------- ⋅ P q (x) – --------------- ⋅ sin2 ( L – 1 ) x ⋅ sin x . (8.7)
L⁄2 L
With x = π ⁄ OSR we get
(L) π 2L – 1 ( L – 1 ) π 22( L – 1) π π
P q (-----------) = --------------- ⋅ P q (-----------) – ------------------ ⋅ sin2 ( L – 1 ) --------------- ⋅ sin ----------- . (8.8)
OSR L⁄2 OSR L⁄2 2OSR OSR
This allows us to derive the noise power for a certain modulator order using the known noise
power for a modulator of lower order.
SNDR and SFDR as Functions of Output Conductance 221
8.3 SNDR and SFDR as Functions of Output Conductance

In equations (4.65) and (4.66) we have the expressions on the positive and negative output
currents in the static case. The currents can be written as
+ 1 + x̃ – 1 – x̃
I out = I DC ⋅ ------------------------ and I out = I DC ⋅ ------------------------ . (8.9)
1 + ρ' G ⋅ x̃ 1 – ρ' G ⋅ x̃
where I DC and ρ' G are the normalized DC current and conductance ratio from (4.36), and x̃
is the normalized AC part of the input. We now investigate how the error behaves as a func-
tion of the conductance ratio as we apply a sinusoid at the input. For the single-ended signal
+ . Further, we are considering a sinusoid input and the amplitude is less than
we set I out = I out
its DC value, hence
X AC X AC
x̃ = ---------- ⋅ sin α < ---------- < 1, (8.10)
X DC X DC
where α = n ⋅ ωT and n is the sequence index and ωT is the normalized angular frequency.
Since the factor in (8.10) is less than 1, we can write the expression in (8.9) with a converging
Taylor series. To simplify the notation, we let
1 + x̃
I out = I out ⁄ I DC = ------------------------ (8.11)
1 + ρ' G ⋅ x̃
and we get
∞
I out = ( 1 + x̃ ) ∑ ( –1 ) k ⋅ ( ρ'G ⋅ x̃ ) k (8.12)
k=0
We rearrange the expression so that we get

∞ ∞
1
I out = ∑ ( –1 ) k ⋅ ( ρ' G ⋅ x̃ ) k – -------
ρ' G ∑ ( –1 ) k + 1 ⋅ ( ρ'G ⋅ x̃ ) k + 1 (8.13)
k=0 k=0
We reorder the sums according to

∞ ∞
I out = ∑ ( – 1 ) 2k + 1 ⋅ ( ρ' G ⋅ x̃ ) 2k + 1 + ∑ ( –1 ) 2k ⋅ ( ρ'G ⋅ x̃ ) 2k – …
k=0 k=0
∞ ∞
1 1
… – -------
ρ' G ∑ ( – 1 ) 2k + 1 ⋅ ( ρ' G ⋅ x̃ ) 2k + 1 – -------
ρ' G ∑ ( –1 ) 2k + 2 ⋅ ( ρ'G ⋅ x̃ ) 2k + 2 . (8.14)
k=0 k=0
Further, we get
∞ ∞
=  1 – ------- ∑ + ------- +  1 – ------- ∑ ( –1 ) 2k ⋅ ( ρ'G x̃ ) 2k .
1 1 1
I out ( – 1 ) 2k + 1 ⋅ ( ρ' G x̃ ) 2k + 1
 ρ' G ρ' G  ρ' G
k=0 k=0
(8.15)
We denote
222 Appendices
X AC 1
A = ρ' G ⋅ ---------- and B = 1 – ------- . (8.16)
X DC ρ' G
(8.15) is now rewritten as

∞ ∞
I out = 1 – B – B ∑ A 2k + 1 ⋅ sin2k + 1 α +B ∑ A 2k ⋅ sin2k α (8.17)
k=0 k=0
We know that
k–1
( –1 ) k
=   ⋅ ------- ∑ ( –1 ) n ⋅  n  ⋅ cos ( 2 ( k – n )α )
2k 1 2k
sin2k α + -------------
- (8.18)
 k  2 2k 2 2k – 1
n=0
and
k
( –1 ) k
∑ ( –1 ) n ⋅ 
2k + 1
sin2k + 1 α = ------------
- ⋅ sin ( ( 2 ( k – n ) + 1 )α ) . (8.19)
2 2k n 
n=0
We now have a method to express the error by a number of harmonics. (8.18) and (8.19)
inserted in (8.17) gives
∞
A 2k
 2k ⋅  ---
I out = 1 – B + B ∑  k   2
–
k=0
∞ k
A 2k + 1  2k + 1
– 2B ∑ ∑ ( – 1 ) n + k ⋅  --- ⋅ ⋅ sin ( ( 2 ( k – n ) + 1 )α ) +
 2  n 
k = 0n = 0
∞ k–1
A 2k 2k
+ 2B ∑ ∑ ( – 1 ) n + k ⋅  --- ⋅   ⋅ cos ( 2 ( k – n )α ) (8.20)
 2  n
k = 0n = 0
From this expression, we find identify the constant terms, the odd-order harmonics (sin) and
even-order harmonics (cos). We can reorder the sums to find the proper harmonics, for exam-
ple, the first harmonic, H 1 , is found when we set 2 ( k – n ) + 1 = 1 ⇒ n = k in the first dou-
ble sum in (8.20), hence it must be given by
∞ 2k + 1
 ---
A
⋅
2k + 1
H 1 = 2B ∑  2  k 
⋅ sin α . (8.21)
k=0
The second harmonic is found when we set 2 ( k – n ) = 2 ⇒ n = k – 1 in the second double

sum in (8.20)
∞ 2k
∑  ---2  ⋅
A 2k 
H 2 = – 2B cos 2α . (8.22)
 k – 1
k=1
Also notice from (8.22) that we have to start the summation from k = 1 . We may now for
example find the SFDR as the power ratio between the fundamental and the second harmonic.
We have that the SFDR must be
PH 1
SFDR = --------- (8.23)
PH 2
where P H 2 is the power of the harmonic from (8.22), and P H 1 is the signal power with the
first error harmonic overlayered. We get
∞ 2 ∞ 2
A 2k + 1  2k + 1 A 2k + 1  2k + 1
--- ⋅ 2B ∑  ---  ---
1
2  2
⋅
 k  ∑  2 ⋅
 k 
k=0 k=0
SFDR = -------------------------------------------------------------------------------
- = ----------------------------------------------------------------
- (8.24)
∞ 2k
2 ∞ 2k
2
--- ⋅ 2B ∑  --- ⋅  2k   ---
A
⋅
1 A 2k 
2  2   k–1  ∑  2   k – 1
k=1 k=1
The sums express hypergeometric distributions and it can be shown that (8.24) equals
2
1 + 1 – A2
SFDR =  ----------------------------- . (8.25)
 A 
Substituting back A from (8.16) into (8.25) gives the SFDR expressed by the amplitude levels
as
2
2
1 1 1 + X DC ⋅ ρ G ( 1 + X DC ⋅ ρ G ) 2
SFDR = ------------------- + --------------------------2- – 1 = ------------------------------
- + --------------------------------------
2
-–1 .
X AC X
 ----------ρ'
AC  X AC X
----------ρ' G AC
X DC  X DC G
(8.26)
For the differential output, we use the difference between the currents in (8.9). We get
1 + x̃ 1 + x̃ 2x̃
I diff = I DC ⋅ ------------------------ – I DC ⋅ ------------------------ = I DC ⋅ ( 1 – ρ' G ) ⋅ ------------------------------2- . (8.27)
1 + ρ' G ⋅ x̃ 1 + ρ' G ⋅ x̃ 1 – ( ρ' G ⋅ x̃ )
To simplify the notation, we normalize this expression as
ρ' G ⋅ I diff ρ' G ⋅ x̃

I diff = ------------------------------------------ = ------------------------------
-. (8.28)
2 ⋅ I DC ⋅ ( 1 – ρ' G ) 1 – ( ρ' G ⋅ x̃ ) 2
Using the same methods as above (8.12) gives that (8.28) can be written as
∞ ∞ ∞
I diff = ( ρ' G ⋅ x̃ ) ∑ ( ρ'G ⋅ x̃ ) 2k = ∑ ( ρ'G ⋅ x̃ ) 2k + 1 = ∑ A 2k + 1 ⋅ sin2k + 1 α (8.29)
k=0 k=0 k=0
Using the trigonometric description from (8.19) in (8.29) gives

∞ k
A 2k + 1  2k + 1
I diff = 2 ∑ ∑ ( – 1 ) n + k ⋅  --- ⋅ ⋅ sin ( ( 2 ( k – n ) + 1 )α ) . (8.30)
 2  n 
k = 0n = 0
Now, we notice, as expected for differential signals, that the even-order harmonics are can-
224 Appendices
celled. Instead the third-order harmonic will determine SFDR. As before, we get the first har-
monic for k = n and the third harmonic as k = n + 1
∞ 2k + 1
 ---
A
⋅
2k + 1
H1 = 2 ∑  2  k 
⋅ sin α (8.31)
k=0
and
∞ 2k + 1
∑  ---2  ⋅
A 2k + 1
H 3 = –2 ⋅ sin 3α . (8.32)
 k–1
k=1
The SFDR is found by taking the power ratio between the expressions in (8.31) and (8.32):
∞ 2k + 1
2
∑  ---2  ⋅
A 2k + 1
 k  2
SFDR = ----------------------------------------------------------------2- = 1 – -----2- ⋅  1 + -----------------
k=0 2 1–A
(8.33)
∞ A  A 
A 2k + 1  2k + 1
 ---
∑  2 ⋅
 k–1
k=1
It is somewhat more tricky to find the SNDR. For the single-ended case we found in (8.20)
∞ k–1 2k
∑ ∑ ( –1 ) n + k ⋅  ---2  ⋅   ⋅ cos ( 2 ( k – n )α ) –
A 2k
I out = J DC + 2B
 n
k = 0n = 0
∞ k 2k + 1
∑ ∑ ( –1 ) n + k ⋅  ---2  ⋅
A 2k + 1
– 2B ⋅ sin ( ( 2 ( k – n ) + 1 )α ) , (8.34)
 n 
k = 0n = 0
where J DC is the DC term. The output error will be given by the expression above minus the
signal, i.e. by also considering the scaling factor, we get
X DC ⋅ I LSB
I err = I out – -------------------------- ⋅ ( 1 + x̃ ) = I out – ( 1 + ρ G ⋅ X DC ) ⋅ ( 1 + x̃ ) (8.35)
I DC
and
∞ k–1
A 2k 2k
I out = J' DC + 2B ∑ ∑ ( – 1 ) n + k ⋅  --- ⋅   ⋅ cos ( 2 ( k – n )α ) –
 2  n
k = 0n = 0
∞ k
A 2k + 1  2k + 1
– 2B ∑ ∑ ( – 1 ) n + k ⋅  --- ⋅ ⋅ sin ( ( 2 ( k – n ) + 1 )α ) –
 2  n 
k = 0n = 0
X AC
– ( 1 + ρ G ⋅ X DC ) ⋅ ---------- ⋅ x̃ . (8.36)
X DC
We will, however, use the approximation that the first harmonic is equal to the signal power
although there is an overlayered error term. As an expression on the SNDR, we will use the
THD where we use some of the first harmonics, i.e.,
PH 1 PH 1 ⁄ PH 2 SFDR
SNDR ≈ ------------------------------------------------------ = -----------------------------------------------
- = ------------------------------------------------ (8.37)
PH 2 + PH 3 + PH 4 + … PH 3 PH 4 PH 3 PH 4
1 + --------- + --------- + … 1 + --------- + --------- + …
PH 2 PH 3 PH 2 PH 3
The second harmonic, H 2 , was found in (8.22), H 3 is found by setting n = k – 1 in the sec-
ond sum in (8.34), H 4 is found by setting n = k – 2 in the first sum, H 5 by setting
n = k – 2 in the second sum, etc.
∞ 2k + 1 ∞ 2k
 ---
A
⋅
2k + 1  ---
A
⋅
2k 
H 3 = 2B ∑  2  k–1
⋅ sin 3α , H 4 = 2B ∑  2  k – 2
⋅ cos 4α ,
k=1 k=2
∞ 2k + 1
 ---
A
⋅
2k + 1
H 5 = – 2B ∑  2  k–2
⋅ sin 5α . (8.38)
k=2
We now have a number of hypergeometric distributions in the denominator of (8.37). It can

for example be found that
PH 3 2 P 2
1 – 1 – A2
--------- =  ---------------------------- , --------- =  -----2- ⋅ ( 1 – 1 – A 2 ) – 1 , and
H4 2
PH 2  A  PH 2 A 
2
PH 5 4 – 3 A 2 + ( A 2 – 4 ) ⋅ 1 – A 2
--------- =  --------------------------------------------------------------------- , etc. (8.39)
PH 2  A3 
We may for example find the SNDR (or THD) with respect to the first three terms
8( A2 – 1 ) + 4 1 – A2 ⋅ ( A2 – 2 ) – A4
SNDR ≈ -----------------------------------------------------------------------------------------
-, (8.40)
A2 ⋅ ( A2 – 4 )
where A was defined in (8.16). This equation only contains few of the tones and it will not
hold as a good approximation on the SNDR. Instead, we will for the SNDR derivations go
back to the “original” expressions. Consider the current error
I LSB ⋅ X ρG ⋅ X 2
∆I (X ) = Ĩ out ( X ) – I out ( X ) = I LSB ⋅ X – ------------------------ = I LSB ⋅ ------------------------ =
1 + ρG ⋅ X 1 + ρG ⋅ X
ρ G ⋅ ( X DC + X̃ ) 2 ρ' G ⋅ ( 1 + x̃ ) 2
= I LSB ⋅ ----------------------------------------------- = I LSB ⋅ X DC ⋅ -------------------------------- . (8.41)
1 + ρ G ⋅ ( X DC + X̃ ) 1 + ρ' G ⋅ x̃
From Chapter 2 we remember the discussion on quantization or truncation noise. The expres-
sion in (8.41) was compared to an ideal continuous-time current, which is given by a ramped
input. The error power, P e , is given by the difference between the continuous-time current
and the piece-wise linear output current and hence the error power is also dependent on the
code applied to the converter
226 Appendices
T ⁄2 2
2 – I LSB ∆I (X ) t 3 T ⁄2
∆I (X ) –  --- ⋅ I LSB dt = ------------- ⋅  -------------- – ---
1 t
P e(X ) = ---
T ∫ T  3  I LSB T 
–T ⁄ 2
= …
–T ⁄ 2
2
I LSB
- + [ ∆I (X ) ] 2 ,
… = --------- (8.42)
12
where T is the update period. From (8.42) we identify the quantization noise power
2
I LSB
P q = ---------
-. (8.43)
12
We find the time-average error power (the expected output power) to be
P e( X ) = P e = P q + P ε , (8.44)
where P ε is the time-averaged power of the error current introduced by the degraded con-
verter is denoted
P ε = [ ∆I ( X ) ] 2 . (8.45)
Let the input signal be a sinusoid
X (n) = X DC + X AC ⋅ sin ( ωT ⋅ n ) + ν , (8.46)
where X DC is the DC level of the signal, X AC is the amplitude of the sinusoid, ωT is the
normalized angular frequency, n is the sequence index, and ν corresponds to the quantization
error which is considered to be white for higher-resolution converters. The AC power of the
sinusoid at the output is given by
2
X AC 2
P s = ---------- ⋅ I LSB . (8.47)
2
The error can be approximated as
ρ' G ⋅ ( 1 + x̃ ) 2 2
P ε = [ ∆I (X ) ] 2 = I LSB ⋅ X DC ⋅ -------------------------------- ≈ [ I LSB ⋅ X DC ⋅ ρ' G ⋅ ( 1 + x̃ ) 2 ] 2 =
1 + ρ' G ⋅ x̃
= ( I LSB ⋅ X DC ⋅ ρ' G ) 2 ⋅ ( 1 + x̃ ) 4 = ( I LSB ⋅ X DC ⋅ ρ' G ) 2 ⋅  1 + --- x 2 + --- x 4

6 3
(8.48)
 2 8 
From (8.4) we know that

2n 2(n – 1)
X AC T 2n – 1 X AC
- ∫ sin2n  ------t dt = X AC ⋅ --------------- ⋅ ------------------
- ∫ sin2 ( n – 1 )  ------t dt .
2π 2 T 2π
--------- (8.49)
T 0 T  2n T 0 T 
From (8.49) we find the iterative expression on the power for a sinusoid to the power of 2n :
( 2n ) 2 2n – 1
P = X AC ⋅ --------------- ⋅ P ( 2n – 2 ) , where P ( 0 ) = 1 . (8.50)
2n
Hence, we get
1 2 3 4 5 6
P ( 2 ) = --- ⋅ X AC , P ( 4 ) = --- ⋅ X AC , and P ( 6 ) = ------ ⋅ X AC . (8.51)
2 8 16
Further on, we neglect the DC error, since this is of less importance for us. Therefore, we get
X AC 2 1 X AC 4
P ε = 3 ( I LSB ⋅ X DC ⋅ ρ' G ) 2 ⋅  ---------- + --- ⋅  ---------- (8.52)
 X DC 8  X DC
Now, we find the signal-to-noise-and-distortion ratio (SNDR) as a function of the output

impedance by combining , , and , hence
2
P Ps X AC ⁄ 2
SNDR = -----s = -----------------
- = ---------------------------------------------------------------------
-. (8.53)
Pe Pq + Pε  X 4 
1 2
------ + 3ρ' G ⋅  X AC 2 +1 AC
--- ⋅ ---------- -
12  8 X DC  2
From (8.27) we get the differential output current and the differential error current must be
given by
2x̃
I derr = Ĩ diff – I diff = I LSB ⋅ X DC ⋅ 2x̃ – I DC ⋅ ( 1 – ρ' G ) ⋅ ------------------------------2- =
1 – ( ρ' G ⋅ x̃ )
2 2
2I LSB ⋅ X̃ ⋅ ρ G ⋅ ( 2X DC – ρ G ⋅ ( X DC – X̃ ) )
= ----------------------------------------------------------------------------------------------------------- (8.54)
( 1 + ρ G ⋅ ( X DC – X̃ ) ) ⋅ ( 1 + ρ G ⋅ ( X DC + X̃ ) )
To calculate the error power, we once again approximate the denominator with one. Since we
are considering the differential error, we will not have any DC error in the expression. We get
the approximation of (8.54) as
2 2
I derr ≈ 2I LSB ⋅ X̃ ⋅ ρ G ⋅ ( 2X DC – ρ G ⋅ ( X DC – X̃ ) ) (8.55)
The error power is
2 2 2 2 2 2
P ε = I derr = 4I LSB ⋅ X̃ 2 ⋅ ρ G ⋅ ( 2X DC – ρ G ⋅ ( X DC – X̃ ) ) . (8.56)
In this expression we will not have any odd-order powers of X̃ due to the differential mode.
We get
2 3
4X DC 2  4X DC 4X DC 4 
⋅ X̃ – X̃ ⋅  -------------
- + 2X DC + X̃ ⋅  -------------
2 4 6 4 2
Pε = 4I LSB ⋅ ρG - + -------------- + X DC . (8.57)
 ρG   ρ 2 ρG 
G
Thereby, we get the power from (8.57) as

6 4 2 2 3
5X AC 3X AC  4X DC X AC  4X DC 4X DC 4 
- – -------------- ⋅ -------------- + 2X DC + ---------- ⋅  -------------
2 4 2
Pε = 4I LSB ⋅ ρG ⋅ ------------- - + -------------
- + X DC
16 8  ρG  2  ρ G2 ρG 
(8.58)
228 Appendices
We approximate the expression as
6 4 2
2 4 5X AC 3X AC X DC 2 2X DC
Pε = 4I LSB ⋅ ρG ⋅ -------------
- – -------------- ⋅ ---------- + X AC ⋅ -------------
- (8.59)
16 2 ρG ρ G2
We get the SNDR in the differential case as
( 2X AC ⋅ I LSB ) 2
Ps ------------------------------------
2
SNDR = ------------------ ≈ ------------------------------------------------------------------------------------------------------------------------------------------- =
Pq + Pε 2 6 4 2
I LSB 2 4 5X AC 3X AC X DC 2 2X DC
---------- + 4I LSB ⋅ ρ G ⋅ -------------- – -------------- ⋅ ---------- + X AC ⋅ ------------- -
12 16 2 ρG ρ G2
2
2X AC
= --------------------------------------------------------------------------------------------------------------------------
-. (8.60)
6 4 2
1 4 5X AC 3X AC X DC 2 2X DC
------ + 4 ⋅ ρ G ⋅ ------------- - – -------------- ⋅ ---------- + X AC ⋅ ------------- -
12 16 2 ρG ρ G2
For cases where the quantization noise is not dominating, we get the approximate relation
1
SNDR ≈ ----------------------------------------------------------------------------------------------- . (8.61)
4 2 2
4 5X AC 3X AC X DC 2X DC
2 ⋅ ρ G ⋅ -------------- – -------------- ⋅ ---------- + ------------- -
16 2 ρG ρ G2
8.4 Fourier Series Coefficients for the MSBs of Sinusoid

Inputs
In Fig. 8.1 we repeat the plot from Chapter 4 showing the transient behavior of the voltage
waveforms for the MSBs of a 14-bit FS sinusoid. The bits are given by
b k(m) for m = 0, …, M – 1 and k = 1, …, N , (8.62)
where we have assumed that M is an even integer expressing the period of the signal and k is
the bit index. From the figure above and the intuitive conclusion we find that
M
b N (m) = 1 for m = 0, …, ----- – 1 and b N (m) = 0 else. (8.63)
2
For the second MSB we have that the signal goes to 1 for (within the first half of the period)
when
2 N – 1 ⋅ 1 + sin  2π ⋅ ----- ≥ 2 N – 1 + 2 N – 2 ,
m
(8.64)
 M
We have that
m 1
2π ⋅ ----- ≥ sin–1 --- (8.65)
M 2
Fourier Series Coefficients for the MSBs of Sinusoid Inputs 229
Characteristic bit waveforms in 8−bit DAC
MSB
Amplitude level
LSB
0 0.25 0.5 0.75 1

Length of period
Figure 8.1 Transient behavior of the individual bits when applying a full-scale sinusoid.
and hence
π m 5π
--- ≤ 2π ⋅ ----- ≤ ------ (8.66)
6 M 6
giving
1 5
------ ⋅ M ≤ m ≤ ------ ⋅ M (8.67)
12 12
Hence, we have
M 5M 7M 11M
b N – 1(m) = 1 for m = ------, …, --------, --------, …, ----------- and b N (m) = 0 else. (8.68)
12 12 12 12
In the expression above, we have also assumed that M can be expressed as an integer times
12. The derivations in the following will only give minor changes if so would not be the case.
In general, the Fourier series coefficients for each bit are given by
M–1 m
1 – j2π ⋅ ----- ⋅ f
C f, k = ----- ⋅
M ∑ b k (m ) ⋅ e M . (8.69)
m=0
From Fig. 8.1 we find that
M
b k(m) = 1 – b k(m + -----) (8.70)
2
and
M M
b k(----- + m) = b k(----- – m) . (8.71)
4 4
Then (8.69) may be rewritten together with (8.70) as
230 Appendices
M⁄2–1 m M–1 m
– j2π ⋅ ----- ⋅ f – j2π ⋅ ----- ⋅ f
M ⋅ C f, k = ∑ b k(m) ⋅ e M + ∑ b k(m) ⋅ e M =
m=0 m = M⁄2
M⁄2–1 m M⁄2 M⁄2–1 m
– j2π ⋅ ----- ⋅ f – j2π ⋅ ------------ ⋅ f – j2π ⋅ ----- ⋅ f
∑ ∑
M
= b k(m) ⋅ e M + e M ⋅ b k(m + -----) ⋅ e M =
2
m=0 m=0
M⁄2–1 m
– j2π ⋅ ----- ⋅ f
∑
M
= b k(m) + b k(m + -----) ⋅ ( – 1 ) f ⋅ e M =
2
m=0
M⁄2–1 m
– j2π ⋅ ----- ⋅ f
= ∑ [ b k(m) + ( 1 – b k(m) ) ⋅ ( –1 ) f ] ⋅ e M . (8.72)
m=0
Using (8.63) we have the coefficients for the MSB

M
----- – 1 M⁄2
M–1 m 2 m – j2π ⋅ ------------ ⋅ f
1 – j2π ⋅ ----- ⋅ f 1 – j2π ⋅ ----- ⋅ f 1 1–e M
C f, N = -----
M ∑ b N (m) ⋅ e M = -----
M ∑ e M = ----- ⋅ ---------------------------------------
M 1
– j2π ⋅ ----- ⋅ f
- =
m=0 m=0 M
1–e
π
– j --- ⋅ f
πf πf
sin ------ sin ------ – jπf  1--- – ----1-
1 e 2 2 1 2  2 M
= ----- ⋅ ---------------- ⋅ -------------- = ----- ⋅ -------------- ⋅ e (8.73)
M πf
– j ------ πf M πf
e M sin ----- M
- sin ------
M
The normalized power of the tone is given by
πf 2 πf
sin ------ sin2 ------
1 2 2
C f, N 2 = ----- ⋅ -------------- ≈ ---------------
-. (8.74)
M πf ( πf ) 2
sin ------
M
For odd f we have that
1
C f, N 2 ≈ ------------2- (8.75)
( πf )
and for even f the coefficients are
C f, N 2 = 0. (8.76)
For the second MSB, we have

M–1 m
– j2π ⋅ ----- ⋅ f
M ⋅ C f, N – 1 = ∑ b N – 1(m) ⋅ e M =
m=0
5M ⁄ 12 – 1 m 7M ⁄ 12 – 1 m M–1 m
– j2π ⋅ ----- ⋅ f – j2π ⋅ ----- ⋅ f – j2π ⋅ ----- ⋅ f
= ∑ e M + ∑ e M + ∑ e M =
m = M ⁄ 12 m = M⁄2 m = 11M ⁄ 12
Fourier Series Coefficients for the MSBs of Sinusoid Inputs 231
M M 11M M
----- – 1 ----- ----------- ------ – 1
M ⁄ 12 3 m 2 12 12 m
– j2π ⋅ --------------- ⋅ f – j2π ⋅ ----- ⋅ f – j2π ⋅ ----- ⋅ f – j2π ⋅ ----------- ⋅ f – j2π ⋅ ----- ⋅ f
= e M
∑ e M + e M + e M ⋅ ∑ e M =
m=0 m=0
π M⁄3–1 m 11π M ⁄ 12 – 1 m
– j --- ⋅ f – j2π ⋅ ----- ⋅ f – j --------- ⋅ f – j2π ⋅ ----- ⋅ f
= e 6 e ∑ M + e – jπ f + e 6 ⋅ ∑ e M =
m=0 m=0
π 2π 11π π
– j --- ⋅ f – j ------ ⋅ f – j --------- ⋅ f – j --- ⋅ f
⋅ 1 – e 3  ⋅ 1 – e 6 
1
= ----------------------------f- ⋅ e 6 + e – jπ f + e 6 =
– j2π ⋅ -----
   
1– e M
π 11π 5π 7π
 e – j --6- ⋅ f + e – j -------- 6
-⋅ f
 –  e – j ----- 6
-⋅ f – j ------ ⋅ f
+ e 6  + ( e – jπ f – 1 )
   
= -------------------------------------------------------------------------------------------------------------------------------
f
--------- =
– j2π ⋅ -----
1–e M
π π π π
 e j --2- f – e – j --2- f  ⋅  e j --6- ⋅ f + e – j --6- ⋅ f  – 1 π
    – j --- f
= ----------------------------------------------------------------------------------------------
f
- ⋅e 2 =
– j2π ⋅ -----
1–e M
πf fπ
sin ------ – j ------
2 πf e 2
= -------------- ⋅ 2 cos ------ – 1 ⋅ ----------- - (8.77)
πf 6 – j
πf
-----
-
sin ------ e M
M
Hence, we have the Fourier series coefficients given by
πf
sin ------ – jπf  --- – -----
1 1
1 2 πf  2 M
C f, N – 1 = ----- ⋅ -------------- ⋅ 2 cos ------ – 1 ⋅ e (8.78)
M πf 6
sin ------
M
The normalized power of the tones is given by
πf 2 πf
sin ------ sin2 ------
1 2 πf 2  πf 
2
C f, N – 1 2 = ----- ⋅ -------------- ⋅ 2 cos ------ – 1 ≈ ---------------
- ⋅ 2 cos -----
- – 1 (8.79)
M πf
sin ------
6 ( πf ) 2  6 
M
For odd f we have that
 2 cos πf
2
------ – 1
 6 
C f, N – 1 2 ≈ ----------------------------------- (8.80)
( πf ) 2
and for even f the coefficients are zero
C f, N – 1 2 = 0. (8.81)
For f = 3 we have
232 Appendices
2 1 2 1
C 3, N = -------------2- and C 3, N – 1 = -------------2- . (8.82)
( 3π ) ( 3π )
These values now express the power of the errors in the third tone and they are compared to
the signal power to form the SFDR and SNDR.
References
[1] W.Y. Chen, DSL Simulation Techniques and Standards. Development for Digital
Subscriber Line Systems, Maxmillan Technical Publishing, Indianapolis, IN, USA, 1998,
ISBN 1-57870-017-5.
[2] T. Starr, J.M. Cioffi, and P.J. Silvermann, Understanding Digital Subscriber Line
Technology, Prentice Hall, Upper Saddle River, NJ, USA, 1999, ISBN 0-13-780545-4.
[3] “American National Standard for Telecommunications – Network and Customer
Installation Interfaces – Assymetric Digital Subscriber Line (ADSL) Metallic Interface,”
in draft American National Standard for Telecommunications, ANSI T1E1.4/97-007R6,
Jan. 1998.
[4] Future Mobile Standards, private communication, Ericsson Microelectronics AB.
[5] J. Rabaey, Digital Integrated Circuits – A Design Perspective, Prentice Hall, Upper
Saddle River, NJ, USA, 1996, ISBN 0-13-394271-6.
[6] N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design – A Systems
Perspective, 2nd ed., Addison-Wesley, New York, NY, USA, 1994, ISBN 0-201-53376-
6.
[7] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, New
York, USA, 1997, ISBN 0-471-14448-7.
[8] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, New York, NY,
USA, 2000, ISBN 0-07-238032-2.
[9] R. J. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters,
Kluwer Academic Publishers, Boston, MA, USA, 1994, ISBN 0-7923-9436-4.
[10] H. T. Jensen and I. Galton, “A Low-Complexity Dynamic Element Matching DAC for
Direct Digital Synthesis,” IEEE Trans. on Circuits and Systems II, vol. 45, no. 1, Jan.
1998, p. 13-27.
[11] I. Galton, “Spectral Shaping of Circuit Errors in Digital-to-Analog Converters,” IEEE
Trans. on Circuits and Systems II, vol. 44, no. 10, Oct. 1997, p. 808-17.
[12] J. Yuan and C. Svensson, “New Single-Clock CMOS Latches and Flipflops with
Improved Speed and Power Savings,” IEEE J. of Solid-State Circuits, vol. 32, no. 1, Jan.
1997, p. 62-9.
233
References 234
[13] M. Ismail and T. Fiez, Analog VLSI: Signal and Information Processing, McGraw-Hill,
New York, NY, USA, 1994, ISBN 0-07-113387-9.
[14] M. Gustavsson, J.J. Wikner, and N. Tan, CMOS Data Converters for Communications,
Kluwer Academic Publishers, Boston, MA, USA, Jan. 2000, ISBN 0-7923-7780-X.
[15] S. Haykin, Digital Communications, John Wiley & Sons, New York, USA, 1988, ISBN
0-471-62947-2.
[16] T.M. Cover and J.A. Thomas, Elements of Information Theory, John Wiley & Sons, New
York, USA, 1998, ISBN 0-471-06259-6.
[17] Analog front-end for DSL, Private communication, Ericsson Microelectronics AB.
[18] Echo cancellation techniques, Private communication, Ericsson Microelectronics AB.
[19] F. Sjöberg, M. Isaksson, P. Deutgen, R. Nilsson, P. Ödling, and P.-O. Börjesson,
“Performance Evaluation of the Zipper Duplex Method,” in Proc. IEEE 1998 Intern.
Conf. on Communications, ICC’98, vol. 2, 1998, p. 1035-9.
[20] D.G. Mestdagh, M.R. Isaksson, and P. Ödling, “Zipper VDSL: a Solution for Robust
Duplex Communication over Telephone Lines,” IEEE Communications Magazine, vol.
38, no. 5, May 2000, p. 90-6.
[21] I. Koren, Computer Arithmetic Algorithms, Prentice-Hall, Englewood Cliffs, NJ, USA,
1993, ISBN 0-13-151952-2.
[22] A. Pacut and K. Hejn, “Analog-to-Digital Converters: Towards a Generalization of
Widrow’s Theorem,” in Proc. IEEE 1998 Conf. on Instrumentation and Measurement
Technology, IMTC’98, vol. 2, 1998, p. 1190-7.
[23] P. Hendriks, “Specifying Communication DACs,” IEEE Spectrum, vol. 34, no. 7, July
1997, p. 58-69.
[24] Analog Amp Linearity Characterization via Probability Weighted Mutlitone Power Ratio,
AN9718, Application note, Intersil, Apr. 1997.
[25] J.J. van de Beek, P. Ödling, S.K. Wilson, and P.O. Börjesson, “Orthogonal Frequency-
Division Multiplexing (OFDM),” in Review of Radio Science 1996-99, Intern. Union of
Radio Science (URSI), Oxford University Press, UK, 1999.
[26] R.A. Witte, Electronic Test Instruments – Theory and Applications, HP Professional
Books, Prentice Hall, Englewood Cliffs, NJ, USA, 1993, ISBN 0-13-253147-X
[27] J. C. Candy and G. C. Temes, Oversampling Delta-Sigma Data Converters, IEEE Press,
New York, NY, USA, 1992, ISBN 0-87942-281-5.
[28] S. Chu and C.S. Burrus, “Multirate Filter Design Using Comb Filters,” IEEE Trans. on
Circuits and Systems I, vol. 31, no. 11, Nov. 1988, p. 913-24.
[29] S.R. Norsworthy, R. Schreier, and G.C. Temes, Delta-Sigma Data Converters: Theory,
Design, and Simulation, IEEE Press, NY, USA, ISBN 0-78031-045-4, Nov. 1996.
[30] R. Unbehauen and A. Cichocki, MOS Switched-Capacitor and Continuous-Time
Integrated Circuits and Systems, Springer-Verlag, 1989, ISBN 0-387-50599-7.
[31] S. Wang, M.O. Ahmad, and B.B. Bhattacharrya, “A Novel Cyclic D/A Converter,” in
Proc. IEEE 1993 Symp. on Circuits and Systems, ISCAS ’93, vol. 2, May 1993, p. 1224-7.
[32] J.J. Wikner and M. Vesterbacka, “D/A Conversion Method and D/A Converter,” Swedish
patent, 9903500-8, 1999.
[33] J.J. Wikner and M. Vesterbacka, “D/A conversion with Linear-Coded Weights,” in Proc.
IEEE 2000 Southwest Symp. on Mixed-Signal Design, SSMSD’00, San Diego, CA, USA,
Feb. 2000, p. 61-6.
235 References
[34] J.J. Wikner and M. Vesterbacka, “Characteristics of Linear-Coded D/A Converters,” in
Proc. IEEE 2000 Southwest Symp. on Mixed-Signal Design, SSMSD’00, San Diego, CA,
USA, Feb. 2000, p. 67-72.
[35] M. Vesterbacka and J.J. Wikner, “Characteristics of Linear-Coded D/A Converters,” in
Proc. IEEJ 4th analog VLSI workshop, AVLSIWS’00, Stockholm, Sweden, June 2000.
[36] C. Toumazou, J. B. Hughes, and N. C. Battersby, Switched-Currents: an Analogue
Technique for Digital Technology, IEE Press, Peter Peregrinus, Stevenage, UK, 1993,
ISBN 0-86341-294-7.
[37] C. Toumazou, F.J. Lidgey, and D.G. Haigh, Analogue IC Design: the Current-Mode
Approach, IEE Press, Peter Peregrinus, Stevenage, UK, 1990, ISBN 0-86341-215-7.
[38] B.J. Tesch and J.C. Garcia, “A Low Glitch 14-b 100MHz D/A Converter,” IEEE J. of
Solid-State Circuits, vol. 32, no. 9, Sept. 1997, p. 1465-9.
[39] C.G. Martinez and S. Simpkins, “A Monolithic 12-Bit Multiplying DAC for NTSC and
HDTV Applications, “ in Proc. IEEE 1989 Bipolar Circuits and Technology Meeting,
1989, p. 52-5.
[40] P.K. Oborn and D.T. Comer, “A New Digital to Analog Converter Resistor String
Architecture,” in Proc. IEEE 10th Annual Intern. ASIC Conf. and Exhibit, 1997, p. 304-7.
[41] M.J.M. Pelgrom, “A 50 MHz 10-bit CMOS Digital-to-Analog Converter with 75Ω
Buffer,” in Digest of Technical Papers 37th IEEE Intern. Solid-State Circuits Conf.,
ISSCC’90, 1990, p. 200-1, 290, San Fransisco, CA, USA.
[42] V.F. Dias, J.E. Franca, and J.C. Vital, “High-speed Digital-to-Analogue Convertor Using
Passive Switched-Capacitor Algorithmic Conversion,” Electronics Letters, vol. 24, no.
17, Aug. 1988, p. 1063-5.
[43] M.S. Piedade and A. Pinto, “A New Multiplier-Divider Circuit Based on Switched
Capacitor Data Converters,” in Proc. IEEE 1990 Intern. Symp. on Circuits and Systems,
ISCAS’90, vol. 3, 1990, p. 2224-7.
[44] H. Träff, T. Holmberg, and S. Eriksson,”Application of Switched Current Technique to
Algorithmic DA- and AD-Converters,” in Proc. IEEE Intern. Symp. on Circuits and
Systems, ISCAS’91, June 1991, p. 1549-52.
[45] P. Riffaud-Desgreys, E. Garnier, Ph. Roux, and Ph. Marchegay, “New Structure of
Algorithmic DAC in Switched Current Technique,” in Proc. 3rd Intern. Conf. on
Advanced A/D and D/A Conversion Techniques and their Applications, Glasgow,
Scotland, July 1999, p. 111-4.
[46] AD9774, Data sheet, Analog Devices Inc., 2000.
[47] N. Tan, E. Cijvat, and H. Tenhunen, “Design and Implementation of High-Performance
CMOS D/A Converter,” In Proc. IEEE 1997 Intern. Symp. on Circuits and Systems,
ISCAS’97, Hong Kong, vol. 1, May 1997, p. 421-4.
[48] C.A.A. Bastiaansen, D.W.J. Groeneveld, H.J. Schouwenaars, and H.A.H. Termeer, “A
10-b 40-MHz 0.8-mm CMOS Current-Output D/A Converter,” IEEE J. of Solid-State
Circuits, vol. 26, no. 7, July 1991, p. 917-21.
[49] C.H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,” IEEE J. of
Solid-State Circuits, vol. 33, no. 12, Dec. 1998, p. 1948-58.
[50] S.-Y. Chin and C.-Y. Wu, “A 10-b 125-MHz CMOS Digital-to-Analog Converter (DAC)
with Threshold-Voltage Compensated Current Sources,” IEEE J. of Solid-State Circuits,
vol. 29, no. 11, Nov. 1994, p. 1374-80.
[51] I.H.H. Jørgensen and S.A. Tunheim, “A 10-bit 100MSamples/s BiCMOS D/A
Converter,” Analog Integrated Circuits and Signal Processing, vol. 12, 1997, p. 15-28.
References 236
[52] N. Tan, “A 1.5-V 3-mW 10-bit 50 MS/s CMOS DAC with Low Distortion and Low
Intermodulation in Standard Digital CMOS Process,” in Proc. IEEE 1997 Custom
Integrated Circuits Conf., CICC’97, Santa Clara, CA, USA, May 1997, p. 599-602.
[53] J.M. Fournier and P. Senn, “A 130-MHz 8-b CMOS Video DAC for HDTV
Applications,” IEEE J. of Solid-State Circuits, vol. 26, no. 7, July 1991, p. 1073-6.
[54] A. Fraval and F. Dell’ova, “A 10-bit 70MHz 3.3V CMOS 0.5um D/A Converter for
Video Applications,” IEEE Trans. on Consumer Electronics, vol. 41, no. 3, Aug. 1995,
p. 875-9
[55] D.A. Mercer, “Two Approaches To Increasing Spurious Free Dynamic Range in High
Speed DACs,” in Proc. IEEE 1993 Bipolar/BiCMOS Circuits and Technology Meeting,
1993, p. 80-3.
[56] D. Birru and E. Roza, “Video-Rate D/A Converter Using Reduced Rate Sigma-Delta
Modulation,” in Proc. IEEE 1998 Custom Integrated Circuits Conf., CICC’98, 1998,
p. 241-4.
[57] B.J. Tesch, P.M. Pratt, K. Bacrania, and M. Sanchez, “A 14-b 125 MSps Digital-to-
Analog Converter and Bandgap Voltage Reference in 0.5um CMOS,” in Proc. IEEE
Intern. Symp. on Circuits and Systems 1999, ISCAS’99, Orlando, FL, USA, June 1998, p.
452-5.
[58] A. Van den Bosch, M. Borremans, J. Vandenbussche, G. Van der Plas, A. Marques,
J. Bastos, M. Steyaert, G. Gielen, and W. Sansen, “A 12 bit 200 MHz Low Glitch CMOS
D/A Converter,” in Proc. IEEE 1998 Custom Integrated Circuits Conf., CICC’98, San
Fransisco, CA, USA, 1998, p. 249-52.
[59] A. Marques, J. Bastos, A. Van den Bosch, J. Vandenbussche, M. Steyaert, and
W. Sansen, “A 12b Accuracy 300MSample/s Update Rate CMOS DAC,” in Proc. IEEE
1998 Intern. Solid-State Circuits Conf., ISSCC’98, San Fransisco, CA, USA, 1998, p.
216-7, 440.
[60] J. Vandenbussche, G. Van der Plas, A. Van den Bosch, W. Daerns, G. Gielen,
M. Steyaert, and W. Sansen, “A 14b 150MSample/s Update Rate Q2 Random Walk
CMOS DAC,” in Proc. IEEE 1999 Intern. Solid-State Circuits Conf., ISSCC’99, San
Fransisco, CA, USA, 1999, p. 146-7
[61] K. Falaksahi, C.-K. Ken Yang, and B.A. Wooley, “A 14-bit, 5-MHz Digital-to-Analog
Converter Using Multi-bit Sigma-Delta Modulation,” in Proc. IEEE 1998 Symp. on VLSI
Circuits, 1998, p. 164-5.
[62] AD9764, Data sheet, Analog Devices Inc., 2000
[63] T.-Y. Wu, C.-T. Jih, J.-C. Chen, and C.-Y. Wu, “A Low Glitch 10-bit 75-MHz CMOS
Video D/A Converter,” IEEE J. of Solid-State Circuits, vol. 30, no. 1, Jan. 1995, p. 68-72.
[64] D.W.J. Groeneveld and H.J. Schouwenaars, “A Dual 3.4V Bitstream Continuous
Calibration CMOS D/A Converter with 110 dB Dynamic Range,” in Proc. 2nd Intern.
Conf. on Advanced A-D and D-A Conversion Techniques and their Applications, UK,
1994, p. 42-7,
[65] D. Mercer, “A 16-b D/A Converter with Increased Spurious Free Dynamic Range,” IEEE
J. of Solid-State Circuits, vol. 29, Dec. 1994, p. 1180-5.
[66] M.J.M. Pelgrom and M. Roorda, “An Algorithmic 15-bit CMOS Digital-to-Analog
Converter,” IEEE J. of Solid-State Circuits, vol. 23, no. 6, Dec. 1988, p. 1402-5.
[67] A.R. Bugeja, B.-S. Song, P.L. Rakers, and S.F. Gillig, “A 14-b, 100-MS/s CMOS DAC
Designed for Spectral Performance”, IEEE J. of Solid-State Circuits, vol. 34, no. 12, Dec.
1999, p. 1719-32.
237 References
[68] M.J.M Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matching Properties of MOS
Transistors,” IEEE J. of Solid-State Circuits, vol. 24, no. 5, Oct. 1989, p. 1433-9.
[69] T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, Y. Horiba, “An 80 MHz 8-bit
CMOS D/A Converter,” IEEE J. of Solid-State Circuits, vol. 21, Dec. 1986, p. 983-8.
[70] J. Bastos, M. Steyaert, A. Pergoot, and W. Sansen, “Mismatch Characterization of
Submicron MOS Transistors,”, Analog Integrated Circuits and Signal Processing,
vol. 12, no. 2, Feb. 1997, p. 95-106.
[71] H. Tuinhout, M.J.M. Pelgrom, R. Penning de Vries, and M. Vertregt, “Effects of Metal
Coverage on MOSFET Matching,” in Proc. Intern. Electron Devices Meeting, IEDM’96,
San Fransisco, CA, USA, Dec. 1996, p. 735-8.
[72] H.J. Schouwenaars, D.W.J. Groeneveld, and H.A.H. Termeer, “A Low-Power Stereo 16-
bit CMOS D/A Converter for Digital Audio,” IEEE J. of Solid-State Circuits, vol. 23,
Dec. 1988, p. 1290-7.
[73] J.J. Wikner and N. Tan, “Modeling of CMOS Digital-to-Analog Converters for
Telecommunication,” IEEE Trans. on Circuits and Systems II, vol..46, no. 5, May 1999,
p. 489-99.
[74] K.O. Andersson and J.J. Wikner, “Characterization of a CMOS Current-Steering DAC
using State-Space Models,“ in Proc. IEEE Midwest Symp. on Circuits and Systems 2000,
MWSCAS’00, Lansing, MI, USA, Aug. 2000.
[75] K.O Andersson, N.U. Andersson, and J.J. Wikner, “Spectral Shaping of DAC
2001 Intern. Symp. on Circuits and Systems, ISCAS’01, Sydney, Australia, May 6-9,
2001.
[76] J.J. Wikner and N. Tan, “Influences of Circuit Imperfections on the Performance of
DACs,” Analog Integrated Circuits and Signal Processing, no. 1, Jan. 1999.
[77] J.J. Wikner and N. Tan, “Modelling of CMOS Digital-to-Analog Converters for
Telecommunication,” in Proc. IEEE Symp. on Circuits and Systems 1998, ISCAS’98,
Monterey, CA, USA, May/June 1998, p. 25-8.
[78] K.O. Andersson and J.J. Wikner, “Modeling of the Influence of Graded Element
Matching Errors in CMOS Current-Steering DACs,” in Proc. 17th NorChip Conf., Oslo,
Norway, Nov. 8-9, 1999.
[79] J. Vandenbussche, G. Van Der Plas, G. Gielen, and W. Sansen, “Behavioral Model of
Reusable D/A Converters,” IEEE Trans. on Circuits and Systems II, vol. 46, no. 10, Oct.
1999, p. 1323-6.
[80] N.J. Fliege, Multirate Digital Signal Processing: Multirate Systems, Filter Banks,
Wavelets, John Wiley & Sons, Chichester, West Sussex, England, 1994, ISBN 0-471-
93976-5.
[81] L. Wanhammar, DSP Integrated Circuits, Academic Press, 1998, ISBN 0-127-34530-2.
[82] B.G. Henriques and J.E. Franca, “High-speed D/A Conversion With Linear Phase Sin x/
x Compensation,” in Proc. IEEE Symp. on Circuits and Systems 1993, ISCAS’93, vol. 2,
1993, p. 1204-7.
[83] G. Eriksson, Interpolation Filters in OSDACs for DSL Applications, Master Thesis,
LiTH-ISY-EX-3151, Linköping University, 2001.
[84] M. Lövgren, Sigma-delta Modulators in DACs, Master Thesis, LiTH-ISY-EX-3152,
Linköping University, 2001.
[85] J.J. Wikner, Y. Gao, and N. Tan, “D/A Conversion Interface Design for DMT-ADSL
Applications,” IEEE Magazine of Circuits & Devices, vol. 1, no. 6, Nov. 1998, p. 7-13.
References 238
[86] C. Dunn and M. Sandler, “Adaptive Sigma-Delta Modulation for use in DACs,”
Electronics Letters, vol. 32, no. 10, May 1996, p. 867-8.
[87] Y. Matsuya, K. Uchimura, A. Iwata, and T. Kaneko, “A 17 bit Oversampling D-A
Conversion Technology Using Multistage Noise Shaping,” IEEE J. of Solid-State
Circuits, vol. 24, no. 4, Aug. 1989, p. 969-75.
[88] Y. Zhou and J. Yuan, “An 8-bit, 100 MHz Low Glitch Interpolation DAC,” in Proc. 18th
NorChip Conf., Turku, Finland, Nov. 2000.
[89] D.K. Su and B.A. Wooley, “A CMOS Oversampling D/A Converter with a Current-
Mode Semi-Digital Reconstruction Filter,” in Proc. IEEE 1993 Intern. Solid-State
Circuits Conf., ISSCC’93, San Fransisco, CA, USA, Feb. 1993, p. 230-1.
[90] B.G. Henriques and J.E. Franca, “A High-Speed Programmable CMOS Interface System
Combining D/A Conversion and FIR,” IEEE J. of Solid-State Circuits, vol. 29, no. 8, Aug.
1994, p. 972-7.
[91] Matlab Reference Manual, Mathworks, Dec. 1999.
[92] Y. Gao, J. J. Wikner, and H. Tenhunen, “Design and Analysis of an Oversampling D/A
Converter for DMT-ADSL Systems,” in Proc. IEEJ 3rd Analog VLSI Workshop,
AVLSIWS’99, Taiwan, May, 1999.
Converter in DMT-ADSL Systems,” to appear in Analog Integrated Circuits and Signal
Processing J., 2001.
[94] J.-W. Kim, B.-M. Min, J.-S. Yoo, and S.-W. Kim, “An Area-Efficient Sigma-Delta DAC
with a Current-Mode Semidigital IFIR Reconstruction Filter,” in Proc. 1998 IEEE Intern.
Symp. on Circuits and Systems, ISCAS’98, Monterey, CA, USA, May/June, 1998, p. 344-
7.
[95] K.-H. Ryu, K.S. Yoon, and H.K. Min, “Design of a 3.3 V 12 bit CMOS D/A converter
with a high linearity,” in Proc. IEEE 1998 Midwest Symp. on Circuits and Systems,
MWSCAS’98, 1998, p. 538-41.
[96] Y. Cong and R.L. Geiger, “Switching-Sequence Optimization for Gradient Error-
Compensation in Thermometer-Decoded DAC Array,” IEEE Trans. on Circuits and
Systems II, vol. 47, no. 7, July 2000, p. 585-95.
[97] R.J. Romanczyk and B.H. Leung, “BiCMOS Circuits for High Speed Current Mode D/A
Converters,” IEEE J. of Solid-State Circuits, vol. 30, no. 8, Aug. 1995, p. 923-34.
[98] A. van den Bosch, M. Steyaert, and W. Sansen, “The Extraction of Transistor Mismatch
Parameters: The CMOS Current-Steering D/A Converter as a Test Structure,” in Proc.
IEEE 2000 Intern. Symp. on Circuits and Systems, ISCAS’00, vol. 2, Geneva,
Switzerland, May 2000, p. 745-8.
[99] M. Otsuka, S. Ichiki, T. Tskuada, T. Matsuura, and K. Maio, “Low-Power, Small-Area
10bit D/A Converter for Cell-Based IC,” in Proc. 1995 IEEE Symp. on Low Power
Electronics, 1995, p. 66-7.
[100] B. E. Jonsson, “Design of Power Supply Lines in High-Performance SI and Current-
Mode Circuits,” in Proc. 15th Norchip Conf., Tallinn, Estonia, Nov. 10-11, 1997, p. 245-
50.
[101] www.nallatech.com, Product information, Dec. 1999.
[102] AD6644, Data sheet, Analog Devices Inc., 2000.
[103] K. Kitamura and K. Rondo, “Distortion Compensation Characteristics of Pre-Distortion
Circuit for Private Mobile Radio,” Electronics Letters , vol. 36, no. 20, Oct. 2000,
p. 1675-6.
239 References
[104] J.-H. Han and S. Nam, “Power Amplifier Linearisation Using Post-Distortion Error
Canceller Based on Complex Envelope Transfer Characteristics,” Electronics Letters ,
vol. 36, no. 19, Sept. 2000, p. 1665-6.
[105] A. Bauer and W. Schwarz, “Circuit Analysis and Optimization with Automatically
Derived Volterra Kernels,” in Proc. IEEE 2000 Intern. Symp. on Circuits and Systems,
ISCAS’00, vol. 1, Geneva, Switzerland, 2000, p. 491-4.
[106] P. Wambacq, G.G.E. Gielen, P.R. Kinget, and W. Sansen, “High-Frequency Distortion
Analysis of Analog Integrated Circuits,” IEEE Trans. on Circuits and Systems II, vol. 46,
no. 3, March 1999, p. 335-45.
[107] S. Orcioni, “Approximation and Analog Implementation of Nonlinear Systems
Represented by Volterra Series,” in Proc. 6th IEEE Intern. Conf. on Electronics, Circuits
and Systems, 1999, ICECS’99, vol. 2, 1999, p. 1109-13.
[108] M. Karlsson Rudberg, “ADC Offset Identification and Correction in DMT Modems,” in
Proc. IEEE 2000 Intern. Conf. on Circuits and Systems, ISCAS’00, vol. 4, Geneva,
Switzerland, 2000, p. 677-80.
[109] J.-E. Eklund and M. Karlsson Rudberg, “Correction of Static Errors in ADCs,” Swedish
patent, 9902000-0, May 1999.
[110] D.P. Scholnik and J.O. Coleman, “Vector Delta-Sigma Modulation with Integral Shaping
of Hardware-Mismatch Errors,” in Proc. IEEE 2000 Intern. Symp. on Circuits and
Systems, ISCAS’00, Geneva, Switzerland, 2000, p. 677-80.
[111] K.O. Andersson, N.U. Andersson, and J.J. Wikner, “Spectral Shaping of DAC
2001 Intern. Symp. on Circuits and Systems, ISCAS’01, Sydney, Australia, May, 2001.
[112] A. Biman and D. G. Nairn, “Trimming of Current Mode DACs by Adjusting Vt,” in Proc.
1996 IEEE Intern. Symp. on Circuits and Systems, ISCAS’96, vol. 1, Atlanta, GA, USA,
May 1996, p. 33-6.
[113] S. Boiocchi, S. Brigati, G. Caiulo, and F. Maloberti, “Self-Calibration in High Speed
Current Steering CMOS D/A Converters,” in Proc. IEE 2nd Intern. Conf. on ‘Advanced
A-D and D-A Conversion Techniques and their Applications’, London, UK, 1994, p. 148-
52.
[114] B. Vargha and I. Zoltan, “Calibration Algorithm for Current-Output R-2R Ladders,” in
Proc. IEEE 17th Instrumentation and Measurement Technology Conf. 2000, IMTC 2000,
vol. 2, 2000, p. 753-8.
[115] N.U. Andersson and J.J. Wikner, “A Strategy of Implementing Dynamic Element
Matching in Current-Steering DACs,“ in Proc. IEEE 2000 Southwest Symp. on Mixed-
Signal Design, SSMSD’00, San Diego, CA, USA, Feb. 2000, p. 51-6.
[116] N.U. Andersson and J.J. Wikner, “Comparison of Different Dynamic Element Matching
Techniques for Wideband CMOS DACs,” in Proc. 17th NorChip Conf., Oslo, Norway,
Nov. 1999.
[117] H. Lin, J. Barreiro da Silva, B. Zhang, and R. Schreier, “Multi-Bit DAC with Noise-
Shaped Element Mismatch,” in Proc. 1996 IEEE Intern. Symp. on Circuits and Systems,
ISCAS’96, vol. 1, Atlanta, GA, USA, May 1996, p. 235-8.
[118] R.T. Baird and T.S. Fiez, “Linearity Enhancement of Multibit Delta-Sigma A/D and D/A
Converters Using Data Weighted Averaging,” IEEE Trans. on Circuits and Systems II,
vol. 42, no. 12, Dec. 1995, p. 753-62.
[119] A. Keady and C. Lyden, “Tree Structure for Mismatch Noise-Shaping Multibit DAC,”
Electronics Letters, vol. 33, no. 17, Aug. 1997, p. 1431-2.
References 240
[120] J.W. Bruce and P. Stubberud,“Generalized Cube Networks for Implementing Dynamic
Element Matching Digital-to-Analog Converters,” in Proc. IEEE 1998 Midwest Symp. on
Circuits and Systems, MWSCAS’98, 1999, p. 522-5.
[121] R. Adams, K.Q. Nguyen, and K. Sweetland, “A 113-dB SNR Oversampling DAC with
Segmented Noise-Shaped Scrambling,” IEEE J. of Solid-State Circuits, vol. 33, no. 12,
Dec. 1998, p. 1871-8.
[122] N.U. Andersson, M. Vesterbacka, J.J. Wikner, and M. Karlsson Rudberg, "Improvement
of Segmented DACs", Swedish patent 0001917-4 pending, May 2000
[123] M. Karlsson Rudberg, M. Vesterbacka, N.U. Andersson, and J.J. Wikner, “Glitch
Minimization and Dynamic Element Matching in D/A Converters,” in Proc. IEEE 7th
Intern. Conf. on Electronics, Circuits, and Systems, ICECS’00, Beirut, Lebanon, Dec.
2000.
[124] M. Vesterbacka, M. Karlsson Rudberg, J.J. Wikner, and N.U. Andersson, “Dynamic
Element Matching in D/A Converters with Restricted Scrambling,” in Proc. IEEE 7th
Intern. Conf. on Electronics, Circuits, and Systems, ICECS’00, Beirut, Lebanon, Dec.
2000.
[125] M. Vesterbacka and J.J. Wikner, "Design of Encoders for Linear-Coded D/A
Converters". Submitted to IEEE 2001 Intern. Symp. on Circuits and Systems, ISCAS’01,
Sydney, Australia, May 2001.
[126] A. van den Bosch, M. Steyaert, and W. Sansen, “SFDR-Bandwidth Limitations for High
Speed High Resolution Current Steering CMOS D/A Converters,” in Proc. 6th IEEE
Intern. Conf. on Electronics, Circuits and Systems, vol. 3, 1999, p. 1193-6.
Index
A DMT, Discrete multi-tone 13, 180
Admittance ratio 109 DNL, Differential nonlinearity 37, 99
ADSL, Asymmetric digital subscriber line 11 DSL, Digital subscriber line 11
AFE, Analog front end 12 Duplex 11
Dynamic element matching
B FRDEM, Full-randomization 203
Bias current 148 NSDEM, Noise-shaping 205
PRDEM, Partial-randomization 204
C Reduced glitching 205
Calibration technique 197 Dynamic randomization 200
CAP, Carrierless amplitude phase modulation 11
Capacitance ratio 91 E
CFT, Clock feedthrough 47, 141 Echo cancelling 13
Common-centroid layout 87 Element matching 84
Conductance ratio 91, 128 ENOB, Effective number of bits 51
Converter
Digital-to-analog 26 F
Crest factor 54 FEXT, Far-end crosstalk 22
Crosstalk 22 Filter
FEXT,Far-end 22 Image-rejection 56
NEXT, Near-end 22 FIR, Finite-length impulse response 58
Current source matching 137 Full-duplex 11
D G
D/A converters Gain error 35
Algorithmic 71 GCN, Generalized cubic network 206
Binary-weighted 68 Glitch 45, 123, 212
Charge-redistribution 74 Graded mismatch 85
Current-steering 73, 128
Direct encoded 69 H
Dual linear-coded 214 Half-duplex 11
Hybrid 70 HD, Harmonic distortion 50, 100, 118
Interpolating 57
Linear-coded 70, 209 I
Nyquist-rate 56 IFIR, interpolated FIR 58
One-bit 174 IIR, Infinite-length impulse response 58
Oversampling 62 Image-rejection filter 27, 56, 177, 184
Pipelined algorithmic 72 IMD, Intermodulation distortion 52
R-2R ladder 74 Impedance ratio 109
Resistor-string 75 INL, Integral nonlinearity 37, 99
Segmented 131 Interdigitized layout 87
SI algorithmic 75 Interpolated FIR filter 176
Signed-digit coded 215 Interpolating D/A converters 57
Thermometer-coded 68 Interpolation 57
DAC, Digital-to-analog converter 26 Interpolator 164
dBFS 48 IPF, Interpolation filter 57, 164, 180
DEM, Dynamic element matching 199 IQ diagram 9
i
Index ii
M Post-distortion circuit 192
Measurement 150 PR, Power ratio 97
Miller effect 47 PRBS, Pseudo-random binary sequence 201
Mismatch 113, 129, 148 Pre-distortion circuit 192, 193
Graded 85 Prefix 19
Stochastic 86 PSD, Power spectral density 57
Mixed-signal design 145
Modulation 9 Q
DMT, Discrete multi-tone 13 QAM, Quadrature amplitude modulation 9
PAM, Pulse-amplitude modulation 26 Quantization
QAM, Quadrature amplitude modulation 9 Noise 31
Modulator Non-uniform 40
Error-feedback 63, 169 Uniform 32
MASH, Multi-stage 173
MF, Multiple-feedback 65, 171, 182 R
Multi-bit 64, 170 R2Z, Return-to-zero 143, 217
Noise-shaping 62, 169, 182
One-bit 64, 170 S
Signal-feedback 62, 169 Scrambler 200
Monotonicity 39
Semi-digital FIR filter 175, 184, 185
Moving average filter 167 Settling-time error 95
MSB segmentation circuit 144 SFDR, Spurious-free dynamic range 51, 105, 120,
MTPR, Multi-tone power ratio 51 122
Multi-rate filtering 165 Signed-digit code 215
Multi-stage interpolation 165 Simplex 11
Sinc filter 167
N SNDR, Signal-to-noise-and-distortion ratio 50,
NEXT, Near-end crosstalk 22 102, 116, 122, 227
Noise 110 SNR, Signal-to-noise ratio 33, 50, 112
Noise bandwidth 110 Splitter filter 12
Noise-shaping modulators 62 SQNR, Signal-to-quantization noise ratio 33
NTF, Noise transfer function 62, 171 STF, Signal transfer function 62, 171
Nyquist-rate D/A converters 56 Stochastic mismatch 86
SUFR, Signal-to-update frequency ratio 46
O Switch memory 143
Offset error 34 Switch on-conductance 88
OSDAC, Oversampling D/A converters 62 Switch on-resistance 139
OSR, Oversampling ratio 58, 164 Switch signal generator 142
P T
PAM, Pulse-amplitude modulation 26 THD, Total harmonic distortion 50
PAR, Peak-to-average ratio 15, 54 Time ratio 92
Parasitic resistance 107 Twisted-pair 20
Performance
Dynamic 42 U
Static 31 Unit current source 134, 147, 187, 198
Poissons formula 26
Dissertations
Division of Electronics Systems
Linköpings universitet
Sweden
Vesterbacka, M.: On Implementation of Maximally Fast Wave Digital Filters,

Linköping Studies in Science and Technology, Diss. No. 487, Linköpings Uni-
versity, Sweden, June 1997.
Johansson, H.: Synthesis and Realization of High-Speed Recursive Digital Fil-
ters, Linköping Studies in Science and Technology, Diss. No. 534, Linköpings
University, Sweden, May 1998.
Gustavsson, M.: CMOS A/D Converters for Telecommunications, Linköping
Studies in Science and Technology, Diss. No. 552, Linköpings University, Swe-
den, Dec 1998.
Palmkvist K.: Studies on the the Design and Implementation of Digital Filters,
Linköping Studies in Science and Technology, Dissertation. No. 583, Linköping
University, Sweden, June 1999.

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Linköping Studies in Science and Technology

Dissertation No. 667

Department of Electrical Engineering

Department of Electrical Engineering

Copyright © 2001 J Jacob Wikner

Department of Electrical Engineering

ISBN 91-7219-910-5 ISSN 0345-7524

BER Bit error rate

CAP Carrierless amplitude and phase

EDGE Enhanced data for GSM evolution

FDM Frequency-division multiplexing

GCN General cubic network

IFFT Inverse fast Fourier transform

NEXT Near-end crosstalk

OFDM Orthogonal frequency division multiplexing

PAM Pulse-amplitude modulated

QAM Quadrature amplitude modulation

TDM Time-division multiplexing

ULSI Ultra-high large-scale integration

VDSL Very high data rate DSL

WCDMA Wideband CDMA

xDSL All/Any DSL

ωT normalized angular frequency, sometimes also referred to as the angle

For relative errors, we use ε and δ for absolute errors.

1.1 Integrated Circuits and the Digital/Analog Interface 4

2 Introduction to D/A Conversion . . . . . . . . . . . . 25

2.4 Dynamic Performance 42

3 D/A Converter Architectures . . . . . . . . . . . . . 55

4 Behavioral-Level Models for Current-Steering,

5 Current-Steering D/A Converters . . . . . . . . . . 127

5.1 Introduction 127

5.4 CMOS Current-Steering DACs for VDSL Applications 147

6 Oversampling D/A Converters. . . . . . . . . . . . 161

6.1 Introduction 161

7 Special Techniques for Enhanced D/A Conversion 191

7.1 Introduction 191

8.1 Introduction 219

2 Introduction to D/A Conversion

3 D/A Converter Architectures

4 Behavioral-Level Models for Current-Steering, Nyquist-Rate D/A Con-

5 Current-Steering D/A Converters

6 Oversampling D/A Converters

7 Special Techniques for Enhanced D/A Conversion

2 Introduction to D/A Conversion

3 D/A Converter Architectures

4 Behavioral-Level Models for Current-Steering, Nyquist-Rate D/A Con-

5 Current-Steering D/A Converters

6 Oversampling D/A Converters

7 Special Techniques for Enhanced D/A Conversion

1.1 Integrated Circuits and the Digital/Analog Interface

1.1.1 Digital Circuits

1.1.2 Analog Circuits

where g m is the small-signal transconductance of the amplifier. Typically, g m ∼ V GS – V T and

where n ≈ 1.5 is a process-dependent constant, q is the electron charge, k is the Boltzmann

2V EFF – V DS > V EFF ⇒ V EFF > V DS , (1.11)

Sub-threshold Linear Saturation

Small-signal voltage gain V DS 2

1.1.3 Mixed-Signal Circuits

1.2 Communication Circuits

Source Channel Modulator

Figure 1.3 Illustration of a communication system.

1.2.1 Modulation Schemes