MVD Training Sept-09

Course description

STM32 MICROCONTROLLER IMPLEMENTATION

Ref : 004692A Duration : 4 days

OBJECTIVES PREREQUISITES
• The course details the hardware implementation of the STM32 • A basic understanding of microprocessors and microcontrollers is
microcontroller recommended
• The boot sequence and the clocking are explained • A basic understanding of digital logic or hardware / ASIC design
• The course focuses on the low level programming of the Cortex- issues would be useful but not essential
M3 CPU • A basic understanding of assembler or C programming would be
• Practical labs on integrated peripherals are based on I/O function useful but not essential
package provided by ST
• The various options of communication controllers are explained,
particularly the USB and CAN controllers, so that drivers can be PRACTICAL LABS
adapter to application needs • For on-site courses, labs can be run under the following
environments : Keil µVision, or IAR Workbench
• For open courses, labs are run under IAR Workbench
RELATED COURSES
• USB training (Ref.002606A)
• CAN training (Ref.002601A) Contact
• Ethernet training (Ref.003367A)
Tel : +33 (0)5 62 13 52 32
• ARM Cortex-M3 System Design (Ref.004581A)
Fax : +33 (0)5 61 06 72 60
training@mvd-fpga.com
PARTNERS Course also available
• MVD Training is a ST MCU Certified Training Partner customized
• MVD Training is an ARM Approved Training Centre

Next sessions, see : http://www.mvd-fpga.com/en/formationsCalend.html

• Low voltage detectors
TOPICS
• Clocking
• Selection of the boot mode through external pins
INTRODUCTION TO STM32 • Reset causes
• Start-up sequence, fetch of the first instruction
• ARM Cortex-M3 core based architecture • Low power modes
• The main three blocks : platform, core and input / output • I/O Ports
peripherals

THE CORTEX-M3 CPU ADVANCED CONTROL TIMER AND GENERAL

• Presentation of the core, architecture and programming model PURPOSE TIMER
• Icode, Dcode and system buses • 16-bit timers, block diagram, clock selection and prescalers
• Branch prediction mechanism • Output compare and input capture capabilities, force compare
• Thumb-2 instruction set modes
• Access to memory-mapped locations, addressing modes • One pulse mode
• Conditional execution • Output PWM mode
• Bit-banding • Input PWM mode, pulse measurement
• Memory map • DMA start event
• C-to-Assembly interface
• Exception mechanism DMA CONTROLLER
• System tick timer
• System Control Block • Request priority management between the 16 channels
• linker parameterizing • Circular buffer operation
• Embedded software development with Keil • Memory-to-memory, peripheral-to-memory , memory-to-
• Debug facilities peripheral and peripheral-to-peripheral transfers
• Error management

INFRASTRUCTURE
ANALOG-TO-DIGITAL CONVERTER
• AHB/APB Bridges, split transactions, error handling
• Bus Matrix, round-robin arbitration scheme • High impedance-analog input configuration
• Internal 20 KB SRAM • ADC features : 12-bit resolution, 0 to 3.6 V range
• 128-KB Flash memory • One-shot or continuous conversion
• Program and erase sequences • Dual ADC mode
• External interrupt/event controller, wake-up event management • Conversion on external trigger
• System timers : Real Time Clock, Window Watchdog timer • Utilization of a DMA channel
• Backup registers, tamper detection, RTC calibration
I2C INTERFACE
HARDWARE IMPLEMENTATION
• I2C protocol basics
• Power supplies, external 3.3V, internal generation of 1.8V, • Slave mode vs master mode
related pins
MVD Training - 106 avenue des guis - 31830 Plaisance du Touch - France
Tel : +33 (0) 5 62 13 52 32 - Fax : +33 (0) 5 61 06 72 60 - www.mvd-fpga.com
SIRET : 510 766 066 00029 - Tax Id : FR 74510766066 - NAF : 8559A
Training center registration: 73 3105366 31
 MVD Training Sept-09

Course description

• Transmit and receive sequences FLEXIBLE STATIC MEMORY CONTROLLER

• NOR / PSRAM interface
SERIAL PERIPHERAL INTERFACE [SPI] • NAND / PC CARD interface
• SPI protocol basics • Memory bank mapping
• Queue mode operation • Address mapping and chip select signals
• Transfer sequence • LCD module interface

USART
ETHERNET MAC
• Queue operation mode
• Hardware flow control • Automatic CRC
• Transmit and receive sequences • Flow control
• LIN mode • DMA transfers
• Smartcard interface • Address filtering
• IEEE 1588 PTP
• MII interface
CAN • RMON/MIB
• CAN protocol basics • LAN Wakeup frames / Magic packet
• CAN controller organization • VLAN tags
• Filtering of received messages, acceptance filters
• FIFO mode management DIGITAL-TO-ANALOG CONVERTER
• Test modes : loop back / silent modes
• Configuring the bit timing • DAC implementation
• DMA capability
• External triggers
USB OTG FULL SPEED INTERFACE
• USB protocol basics SDIO
• Buffer description block, buffer descriptor table
• DMA controller used to move data between buffers and • Compliance
EndPoints • Implementation
• Endpoint initialisation • DMA requests
• Suspend / resume events

DOCUMENTATION
Training manuals will be given to attendees during training in print.

MVD Training - 106 avenue des guis - 31830 Plaisance du Touch - France
Tel : +33 (0) 5 62 13 52 32 - Fax : +33 (0) 5 61 06 72 60 - www.mvd-fpga.com
SIRET : 510 766 066 00029 - Tax Id : FR 74510766066 - NAF : 8559A
Training center registration: 73 3105366 31