(IJCNS) International Journal of Computer and Network Security, 15

Vol. 1, No. 3, December 2009

Design of a 2.2-4.0 GHz Low Phase Noise and Low

Power LC VCO
Namrata Prasad1, R. S. Gamad2 and C. B. Kushwah3
1
Electronics & Instrumentation Engineering Department,
SGSITS, 23, Park Road, Indore, M.P., India – 452003
namrata.prasad7@gmail.com
2
Electronics & Instrumentation Engineering Department,
SGSITS, 23, Park Road, Indore, M.P., India – 452003
rsgamad@gmail.com
3
Electronics & Instrumentation Engineering Department,
SGSITS, 23, Park Road, Indore, M.P., India – 452003
chandrabhansingh4@gmail.com

Abstract: This paper reports a design of an integrated Voltage

Controlled Oscillator (LC-VCO) with high oscillation frequency,
Low power consumption and Low Phase noise. For obtaining the
performance parameters, the design was simulated in 0.18µm
CMOS technology. Results of the present deign shows that the Figure 1. Ideal voltage controlled oscillator
oscillation frequency of VCO is 2.2GHz to 4.0 GHz; the power
consumption of the VCO at oscillation frequency of 2.2GHz is Wout can be calculated as follows:
16.13 mw and phase noise-143 mdb/HZ. In addition at 3.3 GHz
and 4.0 GHz is 15.76 mW and 15.31mW with phase noise -151 Wout = Wo + Kvco. Vcont (1)
mdb/Hz and -207mdb/Hz respectively. We have compared the
results of the present design with earlier published work and is
presented in table 1. Where, Wo is the Intercept, Kvco is the gain\sensitivity and
Vcont is the controlled voltage
Keywords: LC-VCO, Low power consumption, low phase
noise, cadence.

1. Introduction
VCO is an important component of Phase Locked Loop
(PLL) which itself is a main block in the Transceiver.
Requirements of the VCO are its ability for a high frequency
operation, low Power consumption, Low Phase noise and
small area. It is strongly recommended to design
monolithically integrate all these blocks on a single chip [1].
A CMOS VCO can be built using ring structures, LC
resonator circuits and relaxation circuits [2]. A low supply Figure 2. Ideal curve of VCO for output frequency and
voltage integrated CMOS Voltage-controlled oscillator controlled voltage.
(VCO) with on chip digital VCO calibration control system
[3]. Recently work has been reported for the design of the
VCO with low power consumption, low phase noise and
high Speed [4-6]. Most application requires that oscillators 2. VCO Design and Analysis
be tunable and their output frequency is a function of a
control input, usually a voltage.
An ideal VCO is a circuit whose output frequency is a linear
function of its controlled Voltage. Figure 1 shows the block
representation of the ideal VCO and Fig.2 shows the ideal
curve of VCO for output frequency and controlled voltage
[7].

Figure 3. Circuit diagram of LC Tank

16 (IJCNS) International Journal of Computer and Network Security,
Vol. 1, No. 3, December 2009

quality factor of the tuned circuit, F is noise factor, K is

In designing of an oscillator is to choose a circuit topology
or type to reduce losses. Figure 3 is considered those losses
which is associated with the inductor. In practical there
would also be losses associated with the variable capacitors
(varactors) and the Metal Oxide Semiconductor Field Effect
Transistors (MOSFETs). It is the active devices. In
experimental integrated VCOs the inductors are on-chip
spiral inductors with low quality factor that dominates the
losses of the VCO tank. It can be shown that the oscillation
frequency of the circuit shown in Fig. 3.
Assuming ideal varactors and MOSFETs is given:
Boltzmann's constant in J/K, T is temperature in K, Pav is
average power at oscillator output, R is the equivalent noise
resistance of the varactor and Kvco is oscillator voltage
gain in Hz/V. From equation (6), Kvco dominates the phase
noise performance in the modified Lesson's formula, thus
phase noise performance can be improved by reduction
Kvco.
Maximum d.c. power dissipation = Vsupply. Ibias (7)
Tuning range can be determined as follows:

(8)
(2)

where,
W o max is the maximum frequency of operation, Wo min is the
It can also be shown, under the same set of assumptions that minimum frequency of operation and Wo is the frequency of
the gm of each MOSFET is given by: operation.

(3)

The main design of this paper is presented in Fig. 4. In this

differentially tuned LC-VCO is used to reduce the power
consumption of VCO, here PMOS and NMOS are cross
coupled to provide better phase noise. The cross-coupled
pairs (M1 and M2) provide the negative resistances to
compensate the parasitic resistance of an LC-resonator to
have better quality factor.
The quality factor Q of the inductor is given by:

(4)

Where,
wo is the oscillation frequency [rad/s]
L is the value of the inductance [H]
R is inductor’s equivalent series resistance
Q is the Quality Factor

The oscillation frequency of oscillator is given by:

(5)

Where, L is the inductance of LC-tank and C is the

capacitance.
To achieve low phase noise and low power consumption, we
have used complementary cross-coupled structure. Phase Figure 4. Schematic view of the VCO
noise can be modeled by the modified Lesson's formula [8].

L(FM)=10log (6)
3. Simulation Result

This work is carried under the environment of cadence

Where, L (FM) phase noise in dBc/Hz, Fm is the frequency software and schematic editor is used for design entry. In
offset from the carrier in Hz, f0 is central frequency in Hz, fc this design we have used specter RF simulator for
is flicker noise corner frequency in Hz, Q is the loaded Simulation, by using TSMC 0.18µ technology. The applied
 (IJCNS) International Journal of Computer and Network Security, 17
Vol. 1, No. 3, December 2009

voltage is 2v at different center frequencies. Simulation

results are obtained with better improvement as compare to
earlier work done and is shown in table 1 and output
analysis are presented in Fig. 5 and 6. Phase noise
simulation of this design is given in Fig.7.

Figure 7. Result of the phase noise

Table 1: Comparison of present work with earlier work

Figure 5. Simulation response of the output published work:

Ref. Technology Center Power Tuning Phase

(CMOS) freque- consu- Range noise
ncy mption mdB/H
(GHz) (mw) z)

[4] 0.18µm 4.4 4.9 41% -110

[7] 0.35µm 6 18 17% -100.2

[8] 0.18µm 2 15 10% -131.9

0.18µm 2.2 16.13 3.86% -143

This
0.18µm 3.3 15.76 3.207 -151
%

0.18µm 4.0 15.31 3.25% -207

Figure 6. Simulation a.c. response of the output voltage
4. Conclusion
In this paper, we have presented a differential tuned LC-
VCO with a tuning range of 3.207% at the operating of
3.3GHz and the phase noise of -151mdB. In addition we
have also obtained results with higher and lower range
center frequency as shown in table 1. Results are presented
18 (IJCNS) International Journal of Computer and Network Security,
Vol. 1, No. 3, December 2009

in table 1 have got improvement over the other recently Authors Profile
reported work. We observed from table 1, when center
frequency is increasing power consumption, phase noise and Namrata Prasad received the B.E. Degree
tuning ranges are improved. This VCO design is best for the in Electronics and communication
applications where the low power consumption and low Engineering.from S.A.T.I. Vidisha in 2008
phase noise are the main requirements. and pursuing M.Tech degree in
Microelectronics and VLSI Design from
S.G.S.I.T.S. Indore. Recently she is working
Acknowledgment with a project on VCO design and analysis.

This work has been carried out in SMDP VLSI laboratory of

the Electronics and Instrumentation Engineering
department of Shri G. S. Institute of Technology and
Science, Indore, India. This SMDP VLSI project is funded R. S. Gamad received the B.E. in
by Ministry of Information and Communication Electronics & Communication Engineering
Technology, Government of India. Authors are thankful to from V. University, India in 1995 and M.E.
degrees in Digital Techniques &
the Ministry for the facilities provided under this project.
Instrumentation Engineering with honours
from Rajiv Ghandhi Technical University
References Bhopal, India in 2003. He has been working
in teaching and research professions since
[1] W. Shing, T. Yan, and H. C. Luong, “A 900MHZ 1996. He is now working as Asst. Prof. in
CMOS low phase-noise voltage controlled ring Department of Electronics & Instru. Engineering of S. G. S. I. T. S.
oscillator,” IEEE Transactions on circuits and systems Indore, India. His interested field of research is Dynamic testing of
-2: Analog and Digital signal processing, Vol.48, pp. A/D Converter, Design of an A/D converter.
216-221, Feb. 2001.
[2] Thomas H. Lee, & Ali Hajimiri, “Oscillator Phase
Noise: A Tutorial” IEEE Journal of Solid State C. B. Kushwah received the B.E. in
Circuit” Vol. 35, No.3 March 2000. Electronics & Telecommunication
[3] Jongsik kim, Jaewook Shin, Seungsoo kim & Hynchol Engineering from Institute of Technology &
Shin, “A Wide Band LC VCO With Linearized Coarse Management (ITM), Gwalior, India in 2002
Tuning Characteristics”, IEEE Transactions on circuit and M. Tech. in Microelectronics and VLSI
& Systems 2.Vol. 55,No.5 May 2008. Design from Shri G. S. Institute of
[4] LU Peiming, Huang Shizhen, Song Lianyi,Chen Run Technology & Science, Indore, India in 2009.
During 2002-2007 he was with DCNPL, Indore as BTS Engineer
“Design of A 2GHZ LOW Phase Noise LC VCO”
and worked as a Lecturer in MPCT, Gwalior. He is now working
International Multi Conference Of Engineers and as a Lecturer under SMDP-II (VLSI) project in Electronics &
Computer scientists 2009 Vol. 2., IMECS 2009, March Instrumentation Engineering Department of Shri G. S. Institute of
18-20, 2009, Hong Kong. Technology & Science. He is interested in analog circuit design,
[5] Paavo Vaananen, Nikomikkola,& Petri Helio, “VCO A/D converters and digital front end design.
Design With On-Chip Calibration System” IEEE
Transactions On Circuit & System–I: Regular Papers,
Vol. 53. No.10, October 2006.
[6] T. Y. Lin, T. Y. Yu, L. W. Ke, G.K. Dehng, “A low
Noise VCO with a constant Kvco foGSM/GPRS/EDGE
Applications” Media Tek Inc,No.1, Dusing Rd.,
Hsinchu Science Park, Hsinchu, Taiwan 300,R.o.c.
IEEE 2008.
[7] B. Razavi, “A Study of Phase Noise in CMOS
Oscillators” IEEE Journal of Solid-State circuit Vol.31
March 1996.
[8] R. M. Weng and J. Y. Lin “A 2.4GHz Low Phase noise
Voltage Controlled Oscillator” Department of
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