Understand essentials
in high-speed PCB designs
By William Sun
Principal Services AE
Cadence Design Systems Inc.
E-mail: wanping@cadence.com
The rapid development of su-
per-large-scale IC and com-
puter technologies leverages
the system design trend toward
high-speed devices and minia-
turization, as well as empha-
sizes the problems of signal in-
tegrity, power supply integrity
and electromagnetic compat-
ibility (EMC/EMI) in the PCB
design. The cause of these prob-
lems is the development of IC
techniques that make the con-
version speed of the IC port sig-
nal become faster.
Figure 1: The voltage-level parameters are input to the constraint
manager of the Cadence PCB SI 610, which carries out the layout routing.
In digital systems design,
the signal transmission on the
PCB is affected by parasitic pa-
rameters (capacitance, induc-
tance and resistance) of the
transmission paths or the
printed circuit line. Receiving
a severely distorted digital sig-
nal causes instability or system
abnormality. Signal integrity,
power supply integ rity and
EMC/EMI problems should be
considered in high-speed sys-
tem design. After considering
and analyzing signal integrity
in the design, simulation re-
sults may differ a lot from the
actual, primarily because
analysis parameters in the tools
do not match the actual PCB
parameters. There are five
steps engineers should take in
dealing with high-speed PCB
design:
1. Fully identify the technology
and the AC/DC characteris-
tic of the devices, IBIS model
collection and verification.
2. Fully identify the basic pro-
cessing technology of the
PCB and define its cascade
parameters.
3. Research thoroughly on the
topological structure of the
signal cable, confirm the ter-
minal connection strategies
and define the constraint
rules of the signal cable.
4. Drive the layout routing ac-
cording to the constraint
rules of the signal cable.
5. Perform sufficient verifica-
tion analysis after routing.
High-speed digital circuit
design gives emphasis on the
characteristics of passive de-
vices, which include connec-
tion lines between the devices’
I/O ports, PCBs and physical
encapsulations of the devices. If
the digital signal switch oper-
ates at a low speed, the passive
devices are the only carriers of
the signal. These passive de-
vices will not affect transmis-
sion quality of the digital signal.
Tflt_clkA
Tco_clkA
Clk
Clk in
Tco_data
Tco_clkB
Clk
Tflt_clkB
Figure 2: Shown here is a synchronous clock example. Computing
methods involved are not the same for different data signal timing modes.
Figure 3: Reference parameters will be input to the constraint manager
of the Cadence PCB SI 610, and the system will compute automatically.
As the switch speed becomes
faster, the high-frequency har-
monics of digital signals make
passive devices become com-
plex carriers. This is due to the
parasitic parameters that cre-
ate a complicated passive net-
work on the signal transmission
path. High-speed digital design
should focus on the effects on
the signal transmission quality
in passive devices (ringing and
reflection), as well as crosstalk
and EMI.
Device characteristics
The first essential step for engi-
neers dealing with high-speed
PCB design is to understand the
manufacturing and material
technology of the digital IC they
will use, such as CMOS, TTL,
Chipset (receiver)
Qc Output from core
clk
Dc
Tflt
Qp
clk Dp Input from core
Processor (driver)
LVTTL, GTLP and ECL. It is
important to know the charac-
teristic parameters of digital IC
devices and high-speed PCB de-
signs such as the voltage mar-
gin—the difference between the
output of the digital IC device
driver and the sensitivity of the
digital IC devices receiver in the
worst condition. It is also the ba-
sis in setting the noise margin of
the digital IC devices receiver in
the process of high-speed PCB
design. The rise/fall time of the
output signal would also help
confirm the existence of high-
speed effects in the system.
DC characteristics are im-
portant references when defin-
ing the noise margin and up/
down overshoot. We may obtain
some related reference param-
eters such as VIL (low-level in-
put voltage), VIH (high-level in-
put voltage), VOL (low-level out-
put voltage) and V OH (high-
level output voltage) from the
datasheet, which are needed to
compute the noise margin and
up/down overshoot.
When computing for the
noise margin, we need to know
the minimum V IL and the
maximum V IH thresholds of
the digital device’s receiver,
and the minimum VOH and the
maximum V OL of the driver.
Because the input terminals of
digital logic circuits always
have two switch margins in the
process of the high-low level
conversion:
Low-level input switch mar-

Figure 4: If the port driving ability choice is ignored in the FPGA applica-
tion, there can be problems such as additional high-speed effects.
gin = max. VIL threshold – min.
VIL threshold
High-level input switch mar-
gin = max. VIH threshold – min.
VIH threshold
The logic input signal could
be identified in the worst condi-
tion. The following are used to
compute for the theoretical
value of the high- and low-level
noise margins of special devices:
High-level noise margin =
min. VOH - max. VOH threshold > 0
Low-level noise margin =
min. VIL threshold – max. VOL > 0
However, the minimum VIL
threshold and maximum V IH
threshold are not provided in
the datasheet and appear as a
high-/low-level input range
Pulse type reflection
4 0
3
Voltage (V)
VDD + 0.3V
Down overshoot = V IL_MIN
= 0.3V
The parameters will be di-
rectly input to the constraint
manager of the Cadence PCB SI
610, which will carry out the
layout routing (Figure 1).
AC characteristics of the
digital IC devices will guide us
in system timing control, timing
parameters computation and
timing margin definition. We
need to understand the AC tim-
ing parameters in the device
datasheet to know which param-
(Table 1). eters are needed by the PCB tool.
In the datasheet: The device datasheet shows
VIL_MAX = max. VIL threshold the waveform relation between
VIH_MIN = min. VIH threshold the functions and timing pa-
rameters, as well as the AC pa-
When applied in the rameters related to the I/O tim-
computations: ing of the device. The measure-
High-level noise margin ment of the AC parameters is
(MIN_NOISE_MARGIN) = done in a special testing load
VOH_MIN - VIH_MIN = 2.4V - 2V condition. Also, the IC device
= 0.4V manufacturer gives the rela-
Low-level noise margin ted testing condition in the
(MIN_NOISE_MARGIN) = datasheet. The timing param-
VIL_MAX - VOL_MAX = 0.8V - 0.4V eters provided in the device
= 0.4V datasheet usually include two
parts: one created by the inner
The computation of the up/ logic delay of the device, the
down overshoot index is com- other created by the output
monly based on the VIH_MAX and driver. Signal-integrity analysis
VIL_MIN found in Table 1; then tools deal with the interaction
we obtain: between the output driver and
Up overshoot = V IH_MAX = the transmission lines. We must
Pulse type reflection
5
give a uniform reference point
between the AC parameters of
the device and the signal-integ-
rity analysis results to precisely
analyze the transmission delay
caused by the line connection.
When analyzing the timing,
we are primarily concerned
about the following timing
parameters:
• TCYCLE—Clock frequency;
• TCO_MAX—After the clock sig-
nal uprising edge takes ef-
fect, the data signal out-
put will take effect after de-
laying the maximum TCO_MAX
(driver);
• TCO_MIN—After the clock sig-
nal uprising edge takes ef-
fect, the data signal output
will be of no effect after delay-
ing the minimum T CO_MIN
(driver);
• T Setup_min —Minimum setup
time of the data signal receiv-
ing (receiver);
• THold_min—Minimum holding
time of the data signal receiv-
ing (receiver).
In Table 2: TCO_MAX = tCD,
TCO_MIN = tCDC, the data signal
output maximum and mini-
mum delay.
In Table 3: TSetup_min = tSA or
tHD, the minimum setup time in
receiving the data signal;
Thold_min = tHA or tHD, the mini-
mum holding time in receiving
the data signal.
While defining the system
data signal timing, we usually
pay attention to whether we will
adopt a synchronous or asyn-
chronous clock, since the com-
puting methods involved are

4
Voltage (V)

2 3 different. An example for the

1 2 synchronous clock is shown in
1
Figure 2. We first ascertain the
0 clock topological structure and
0
data signal direction to help
-1 -1
0 10 20 30 0 10 20 30 with the computation of the
Time(ns) Time (ns) timing parameters with the fol-
Design 102.1 Design 102.1 lowing formula:

TFLT ≥ THO_MAX + TCLK_SKEW – TCO_MIN + TADI

Figure 5: Results show that the right choice of driving ability of the I/O port will reduce high-speed effects.
(Compute the setup time)
Parameter condition Symbol Min Max Units Notes
TFLT ≤ TCYCLE + TCLK_SKEW – TCLK_JITTER –
Supply voltage Vdd , VddQ 3 3.6 V
– TCO_MAX – TSU_MIN – TADI
Input high voltage: Logic 1; All inputs Vh 2 Vdd + 0.3 V 22
(Compute the holding time)
Input low voltage: Logic 0; All inputs VIL -0.3 0.8 V 22
Input leakage current: Any input 0V ≤ Vin ≤ Vdd IL -5 5 A
Reference parameters such
(All other pins not under test = 0V)
as T CYCLE , T CO_MAX , T CO_MIN,
Output leakage current: DQs are disabled; Ioz -5 5 A
T Setup_min , T Hold_min from the
0V ≤ Vout ≤ VddQ
datasheet will be input to the
Output levels: Voh 2.4 - V
constraint manager of the Ca-
Output high voltage (Iout = -4mA)
VOL - 0.4 V dence PCB SI 610, and the sys-
Output low voltage (Iout = 4mA)
tem will compute automatically
Table 1: The minimum low-level input voltage threshold and maximum high-level input voltage threshold (Figure 3).
appear as high- and low-level input ranges in the datasheet. The IBIS model is the core of

Figure 6: The actual signal frequency can be used to compute for the characteristic impedance needed.
high-speed design analysis. The
accuracy and veracity of the
model will decide the correct-
ness of the design. It is an inter-
national standard describing
the IC device’s I/O characteris-
tics. Commonly-used IBIS
model standards are versions
1.0, 2.1 and 3.2. Versions 1.0
and 2.1 are commonly applied
in early IC devices, while ver
3.2 is used for new IC devices.
The IBIS model describes the
characteristics of the digital IC
I/O units and pins in the form
of I/V and V/T tables. Most
digital IC manufacturers pro-
vide the corresponding IBIS
model for the chips.
The IBIS model librar y
should be updated regularly as
digital IC manufacturers often
amend their IBIS model accord-
ing to the changes in the IC
manufacturing technology.
Adopting the old IBIS model
may produce problems in the
design results.
There may be some inaccu-
racies in the IBIS model pro-
vided by manufacturers, so
verification should be carried
out before simulation analysis.
Because of the wide applica-
tion of FPGAs, more board-
level high-speed effects occur
on the PCBs. The reason for
this is that FPGA chip manu-
facturers want to widen the ap-
plication range by working on
either low or high frequency to
obtain good adaptability. The
driving ability of the I/O ports
is prog rammable according
to different applications and
interfaces.
The I/O ports of Altera’s
Cyclone series have different
voltage levels, such as 1.5-,
1.8-, 2.5- and 3.3V that are
implemented for various inter-
face technologies, such as
LVCMOS, LVTTL, SSTL, PCI,
LVDS and RSDS. The interface
application with LVCMOS and
LVTTL has a variety of port
driving ability choices such as
2-, 4-, 8-, 12-, 16- and 24mA.
Different port drive abilities
reflect different I/O character-
istics—weak driving ability with
low working frequency, and
strong driving ability with the
high working frequency. The
switch speed parameters of the
LVCMOS 3.3V with port-driv-
ing abilities of 2mA and 8mA
are as follows:
2mA:
[Ramp]
dV/dt_r 8.050e-001/
1.266e-009 5.180e-001/
1.646e-009 9.473e-001/
8.862e-010
dV/dt_f 6.822e-001/
1.646e-009 4.561e-001/
2.279e-009 9.083e-001/
1.393e-009
8mA:
[Ramp]
dV/dt_r 1.262e+000/
1.520e-010 1.153e+000/
2.280e-010 1.769e+000/
1.520e-010
dV/dt_f 1.578e+000/
2.660e-010 1.256e+000/
4.180e-010 1.713e+000/
1.900e-010
With the above parameters,
the up/down switch speed of an
I/O port with an 8mA driving
ability is larger than that of an
I/O port with a 2mA driving
ability. If the port driving abil-
ity choice is ignored in the
FPGA application, there would
be problems such as additional
high-speed effects and effects
on stability and reliability. We
can construct the point-to-
point topological structure
with the port of LVCMOS 3.3V,
2mA and 8mA driving ability
(Figure 4), with the working
frequency set at 50MHz and
2,000mil transmission lines
(50Ω impedance). The receiv-
ing waveforms with 2mA and
8mA driving abilities are shown
in Figure 5.
Simulation results show that
the right choice of the driving
ability of the I/O port shall
avoid and reduce the high-
speed effects of PCBs. But in
many applications of chips
similar to FPGA, selection of
the driving ability of the I/O
port is usually neglected when
using default values provided
by chip manufacturers.
In the process of high-speed
PCB design, we usually have to
consider matching the transmis-
sion line impedance. The dis-
tance between the transmission
line and the reference plane, and
the width of the transmission
line shall determine the target
impedance. Computed results,
however, usually differ from the
measurement of the transmis-
sion lines of the actual PCBs.
This is mainly due to lack of
understanding of the PCB pro-
cess technology, as well as igno-
rance of the error brought by
the process.
Because of the tolerable
manufacturing error in the pro-
cess, the results of the formula
(simplified model) are not pre-
cise. The materials used in
manufacturing have different
thicknesses, tolerances and di-
electric constants. The thick-
ness of the material changes
before and after laminating it.
There is a change in the dielec-
tric constant when different
materials are mixed. There is
also a difference between the
real etch line width and the de-
sign line width. The thickness
increase of the microstrip (top
and bottom layer) changes after
manufacturing and shaping.
These will all affect the preci-
sion of the impedance calcula-
tion. At present, the usual ma-
terials of the PCBs are FR4, the
dielectric constant of which
changes with the signal fre-
quency. It is important to know
the manufacturing technology
of the PCBs and obtain the
changes in material manufac-
turing parameters. Also, dur-
ing analysis, the simulation cas-
cade parameters set by the ana-
lyzers do not take into account
the manufacturing error, re-
sulting in a big difference in
terms of precision in the simu-
lation and actual results.
In the process of high-speed
PCB design, we should under-
stand the technology, the lami-
nating type of the PCB manu-
facturers, the PCB specifica-
tions, the parameter change

AC electrical characteristics (Vdd = 2.5V +/-5%, Ta = 0 to 70°C)

225MHz 200MHz 166MHz 150MHz 133MHz 100MHz
Symbol Parameter Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Output parameters
__ __ __ __ __ __
ICD Clock high to valid data 3.0 3.2 3.5 3.8 4.2 5 ns
__ __ __ __ __ __
ICDC Clock high to data change 1.0 1.0 1.0 1.5 1.5 1.5 ns

Table 2: TCO_MAX is equal to tCD, while TCO_MIN is equal to tCDC, the data signal output maximum and minimum delay.
before and after the process,
the relative parameter between
the dielectric constants, char-
acteristic impedance and the
working frequency. Process the
design with actual signal fre-
quency in an entirely same
setup as the PCB cascade in the
Allegro PCB Design 610 or PCB
SI 610 design environments
and then compute for the char-
acteristic impedance needed.
The simulation environment
result is close to the actual situ-
ation (Figure 6).
Signal cables
In the process of PCB design, we
primarily consider key signals
such as clock, data, address and
read-write signals. Before rout-
ing the layout, we should pro-
cess the topological structure
research on key signal lines, de-
fine the constraint rules of the
key signal cable properly, and
input instructions in the layout-
routing tool. There are several
connection modes for the key
signal lines such as point-to-
point, point-to-multipoint and
multipoint-to-multipoint. No
matter which connection mode
is used, the connection conduc-
tors between the input and the
output are no longer simple
conductors, but are now trans-
mission lines. When signals
switch between high and low
states or come across imped-
ances that do not match the
transmission line impedance,
signal integrity problems occur.
After realizing the cause of
the signal integrity problems,
we have to choose methods to
eliminate these high-speed ef-
fects. Problems can be identi-
fied by analysis with the point-
to-multipoint multimode—Ad-
dress signal: highest frequency
= 62.5MHz; four receivers con-
nected, characteristic imped-
ance = 60Ω; topological struc-
ture = daisy-chain.
Although the characteristic
impedance of the transmission
lines is 60Ω, this does not
match the input impedance of
the receivers. In the waveform
distortions of the signals at the
four receivers, the problems are
overshoot, attenuation, oscilla-
tion, non-monotonous signal
edge and delay of the receiver
signal. When signals are de-
layed in the transmission pro-
cess, source signals overlap the
reflection signal, which then
causes the waveform distortion
of the receiver signals. These
problems can be solved by
changing the topological struc-
ture of the signals.
After changing the topologi-
cal structure of the signals in the
symmetric routing, we can ob-
tain an improvement in wave-
form quality—problems of high-
speed effects are almost elimi-
nated. Proper topological struc-
ture analysis and definition of
the signal cable are very impor-
tant because they define the lay-
out-routing rules.
Lastly, layout-routing rules
can be def ined in the con-
straint manager. In this pro-
cess, the constraint manager
can help the designer ensure
that the devices are in proper
position. With the symmetry
topological-structure routing
modes defined in the process
of the topological structure
analysis, there should be
enough routing room in the
layout, since it needs more
than the daisy-chain topologi-
cal structure. When routing,
the DRC online check in the
PCB edit environment should
be opened. The constraint
manager will then ensure that
the routing matches the rules.
Post-routing verification
Verification analysis after rout-
ing is a necessary part of high-
speed design. The transmission
line assumes no dielectric loss,
but the signal transmission is
processed on actual PCBs that
have transmission lines with
dielectric loss.
Consequently, we need to de-
fine the topological structure of
the key signal router after rout-
ing, then analyze and verify if
the constraint rules and the pa-
rameter setup of the virtual PCB
environment meet the analysis
requirements. The topological
structure after the address line
routing and the simulation
waveform match the results
of the analysis, satisfying the
design requirements.