Interrupts Handling

Chapter 5
Interrupt Handling Mechanism

Interrupt Interrupt Interrupt
Source Flag Service
Identification Routine
Interrupt Interrupt
Disabling Interrupt Servicing
(masking) Enabling Priority
Interrupt
Structure
Ch05L1-"Microcontrollers....", Raj
Kamal, from Pearson Education,
2005
Lesson 1
Interrupt Identification, Service

Enabling and Allocating priorities
2005
Outline
• Why are interrupts important?
• Identification of interrupt source
• Mask/ Enable interrupts
• Priority of interrupts
2005
Phone ring Importance
Instance of a phone call event is not known.
We can continue our schedule and
attend to phone on an interrupt-event
(ringing).
2005
Interrupt Structure Importance
Instance of occurrence of an interrupt event
is not known.
Interrupt handling when event occurs, saves
wait period of the processor for that event.
Processor can execute foreground program
till an interrupt-event starts a service routine.
Enables servicing of multiple sources of
interrupt events.
2005
Outline
• Why interrupts important?
2005
OV flag
Overflow
An MCU set
Input
InCap flag
Timer capture
set
Device Transmitted a
character Tx flag set
Serial
Device Received - a Rx flag
character set
Interrupt Source Events
2005
Interrupt Source Event Identification
by flag bit
Each interrupt source of each device can
be assigned a flag. Flag(s) shows the
device status
A flag is reset at the start.
A device event sets the flag.
The flag, when sets, shows the need to
service the interrupt (need of executing
the service routine associated with that
interrupt occurrence).
2005
Interrupt Source Event Service Need
Identification by pending Bit
Some MCUs show a service need for

executing a service routine for an interrupt
source of each device by a pending bit.
A device event sets the bit when service
need arises.
Service routine execution resets the
interrupt pending bit.
2005
Outline
2005
MCU
Non
Maskable
interrupts
Maskable
interrupts
2005
Examples- Maskable Interrupt Sources
Timer overflow
Serial Transmitter buffer empty
Serial Receiver buffer full
Serial Receiver FIFO half full
ADC conversion over
Real time clock ticks
2005
Examples- Nonmaskable Interrupt
Sources
Illegal opcode
Software interrupt
RAM parity check error
Clock failure
2005
Software can mask servicing of the
Maskable interrupt event so that the
current routine continues when mask
bit set or enable bit reset
2005
Primary level mask
Software can enable all or disable all

services to all the Maskable interrupt
events by setting enable all bit (EA =
0) or resetting EA bit, called primary
level mask bit.
2005
Secondary level Mask
Software can enable or disable a

service to a specific maskable
interrupt event by setting a specific
enable bit or resetting bit, called
secondary level mask.
2005
• Primary mask bit disables services
of all maskable interrupts
• Secondary mask bit disables
service for an individual maskable
interrupt event
2005
8051/52 Interrupt Enable Register
IE Primary mask bit

Interrupt masks Enable all
IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0
EA - ET2 ES ET1 EX1 ET0 EX0
2005
1 Primary mask bit EA Enable All
0 Disable T2 ET2 Enable T2
1 Enable SI ES Enable SI
1 Enable T1 ET1 Enable T1
0 Disable INT1 EX1 Enable INT1
0 Disable T0 ET0 Enable T0
0 DisableINT0 EX0 Enable INT0
Interrupt Enable when a bit
enable/disable bits sets and when EA =1
2005
Event(s) Identify
Check service need for executing a

service routine, if primary mask
MCU
reset
Check secondary mask, service if

mask reset
Execute Interrupt Service routine

2005
Outline
2005
An MCU Interrupt
event
MCU Assigned
Internal Priority
User Assigned new
priority
2005
MCU Internally Assigned Priorities
2005
8051 Interrupts Defaults Priorities
High
INT0 INT0 pin interrupt
T0 T0OVF interrupt
INT1 INT0 pin interrupt
T1 T1OVF interrupt
RI and TI RI and then Tx
T2 complete
T2EX pin-ve edge
SI Synch capture/reload interrupt
mode Synchronous Serial Device mode
interrupt
Low Ch05L1-"Microcontrollers....", Raj
2005
User Assigned Priorities
2005
I interrupt Priority Register
8051 P
IP.7 IP.6 IP.7 IP.6 IP.7 IP.6 IP.7 IP.6
- - PT2 PS PT1 PX1 PT0 PX0
2005
Assigning Serial Device and INT1 interrupts
Higher priority for service
=0 Low PT2 Priority T2
1 High PS Priority SI
0 Low PT1 Priority T1
1 High PX1 Priority INT1
0 Low PT0 Priority T0
0 Low PX0 Priority INT0
User assigned IP Priority Set/Reset

register bits bits
2005
Check mask and service needs
First Service an interrupt

MCU event whose software and
hardware priorities highest
Lastly service the one that has

lowest software and lowest
hardware priority
2005
Software assigned priority overrides
the hardware priority
2005
Summary
2005
• Interrupts from Devices and events
are important
• Flag identifies an interrupt
• Primary mask bits disables services of
all maskable interrupts
• Secondary mask bit disables service
for an individual maskable interrupt
event
• Hardware assigns default priorities
• Software priority override a hardware
priority
2005
End of Lesson 1
Interrupt Identification, Service

Enabling and Allocating priorities
2005
THANK YOU
2005

Interrupts Handling

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Interrupts Handling

Uploaded by

Copyright:

Available Formats

Chapter 5

Interrupt Handling Mechanism

Interrupt Identification, Service

Interrupt Source Events

Some MCUs show a service need for

Software can enable all or disable all

Software can enable or disable a

IE Primary mask bit

Check service need for executing a

Check secondary mask, service if

Execute Interrupt Service routine

User assigned IP Priority Set/Reset

First Service an interrupt

Lastly service the one that has

Interrupt Identification, Service

You might also like