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IDEAS FOR DESIGN

Circle 520 resistance. With the given 0.1-Ω


value, the output current is limited to

High-Voltage Power 50 A. In a short-circuit situation, ca-


pacitor C1 can be fully (and safely)
discharged in the PowerFET. Re-

Pulse Circuit verse voltages caused by inductive


loads are eliminated by D1. When the
circuit isn’t operating, R14 dis-
R.N. SCHOUTEN charges C1 for safety reasons.
Faculty of Applied Physics, DIMES, Delft University of Technology, Circuit layout is very
P.O. Box 5046, 2600A Delft, The Netherlands. importanta groundplane is needed
to keep inductance low. C1 must be a

F
ast rise-time high-voltage pulses and D1 (see the figure). A 0-V control low-inductance pulse capacitor. Even
have many uses ranging from signal keeps the PowerFET Q1 in the the FET driver IC2 needs a low-in-
EMC testing to device characteri- off state. A 5-V signal on the control ductance layout and decoupling. Dur-
zation.The simple, low-cost circuit de- input operates the driver IC2, from ing the leading-edge gate currents,
scribed here deals with the latter. It’s which a 12-V signal is presented on up to 2 A are needed to charge the
able to generate 0- to 1000-V pulses the gate of the PowerFET Q1, bring- FET input capacitance. Resistors R1
with currents up to 50 A, and a rise ing it into conductance. The output of and R2 have to be made of at least 10
time of 100 ns for 800 V/30 A. The out- the circuit becomes −HV volts as the paralleled discretes to get a low se-
put can withstand short circuits, and negative terminal of C1 is now ries inductance. R4 and C3 compen-
capacitive and inductive loads. Pulse grounded. The pulse ends by making sate for the remaining inductance in
length and repetition rate are deter- the control signal 0 V. Useful pulse R2 (the value of C3 can be changed
mined by an optically isolated TTL-in- length is limited by he voltage drop for this). C2, R5, R6, and R7 form a
put signal. Commercial equipment like during the pulse (caused by discharg- snubber network to protect the FET
pulse/function generators or a PC can ing C1) and by the 100-µs/64-A save against voltage spikes. The values for
be connected to this input. The pulse’s limit of the PowerFET. For the val- the voltage and current monitor lev-
amplitude is set by the HV supply; a ues shown, the circuit voltage drop is els are given for a 50-Ω load.
low-cost photomultiplier-type supply 10 V for a 1-µs, 10-A pulse. Higher currents can be obtained
(0, 5 ..5 mA) can be used when repeti- The short-circuit and overload pro- by duplicating the IC2-Q1-R1 stage
tion rates are below 20 Hz. tection is based on R1. When the out- and connecting them in parallel. R1
The circuit operates as follows: put current is rising, the effective helps to equalize the current for each
when applying the HV supply, C1 is gate-source voltage of the Power- stage. A 100-A pulser has been suc-
charged up to a voltage HV via R1 FET diminishes, enlarging the FET cessfully built in this manner.

HV Pulse output
+12 V STE16N100
C6 SGS-Thomson
IC1 100 nF
6N135 C1
Q1 R8 1 mF R11
0/+5 V 2k 1 kV 330
1 8
C2
Control In 10 nF
2 7 R17 1 kV
5.6k R9 R12 R2 R3
R16 IC2 0.02 4.7k
200 2k 330
3 6 MAX626
D2 R5
1N4148 R1
1 8 0.1 33 C3
4 5 22 nF
R10 R13
2k 330 Voltage R4 Current
2 7 monitor 47 monitor
R6
ELECTRONIC DESIGN / DECEMBER 1, 1997

+12 V HV suppl 33 R15


3 6 D1 56 1 mV/V 10 mV/A
RURP8100
Harris
4 5 C4 C5 R18 R7 R14
100 nF 10 mF 10M 33 2.2
1200 V

Fast risetime pulses of 0 to 1000 V, with currents up to 50 A, can be generated by this simple, low-cost high-voltage power pulse circuit.

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