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KAMARAJ COLLEGE OF ENGINEERING AND TECHNOLOGY, VIRUDHUNAGAR

DEPARTMENT OF INFORMATION TECHNOLOGY
KEY FOR C 3270(May/Jun 2007)
Subject : IT1353, Embedded Systems

Part A

1) Define System on Chip (SoC) with an example.

Nowadays embedded systems are designed in a single silicon chip, called System on chip. It is a
design innovation. SoC is a system on a VLSI chip that has all necessary anolog as well as
digital circuits, processors and software. E.g. A mobile phone.

2) Give any two uses of VLSI designed circuits.

(i) To design SoC (ii) To design microprocessors and microcontrollers.

3) Expand and explain HDLC.

When data are communicated using the physical devices on a network, synchronous serial
communication may be used. HDLC (High Lecvel Data Linnk Control) is an international
standard protocol for a data link network. It is used for linking data from point to point and
between multiple points. It is used in telecommunication and communication networks. It is a bit
oriented protocol. The total number of bits is not necessarily an integer multiple of a byte or a
32-bit integer. Communication is full duplex.

4) What are the characteristics of PCI bus?

Characteristics of PCI bus
(i) It is a Synchronous parallel bus.
(ii) It is platform independent.
(iii) Its clock rate is nearest to the submultiples of system clock. It provides three types of
synchronous parallel interfaces. 32/33 MHz, 64/66 MHz, PCI-X 64/100 MHz, PCI
Super V2.3 264/528 Mbps 3.3 V (on a 64-bit bus), 132/264 (on 32-bit bus) and PCI-X
Super V1.01a for 800Mbps 64-bit bus 3.3 V.
(iv) 32-bit data bus extensible to 64 bits.

5) Why do you need a cross compiler?

Cross compilers are needed to compile the source code in one machine which has the cross
compiler to give the executable file to run on another machine.

6) What are the advantages of building ISR queues?

When there are multiple ISRs, a high priority ISR is executed first and the lowest priority in the
end. It is possible that function calls and statements in any of the higher priority interrupts may
block the execution of low priority ISR and there may be deadline miss for the low priority ISR.
Solution:
Using ISR queues we can avoid deadline misses.

7) Explain the objective of a kernel.

Objectives of Kernel
Process management:
Creation and deletion
Process structure maintenance
Processing resource requests
Scheduling
IPC
Services memory management: File management
Allocation and allocation Device Management
Device Driver
IO management
Interrupts control mechanism

8) What are the uses of semaphores?

(i) Semaphore facilitates IPC for notifying (through a scheduler) a waiting task section
change to the running state upon event at presently running code section at an ISR or
task.
(ii) A semaphore as binary semaphore is a token or resource key.
(iii) The OS also provides mutex access to a set of codes in a task (or thread or process).
The use of mutex is such that the priority inversion problem is not solved in some
OSes while it solves in others OSes.
(iv) The OS provides for counting semaphores.
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9) What is the meaning Task Service Functions?

Task service functions are used to create task, suspend and resume tasks. The functions used are:
OSTaskCreate ( ), OSTaskSuspend( ), OSTaskResume ( ).

10) What are the queue related functions?

OSQCreate ( ) OSQPend ( ) OSQFlush ( )
OSQPost ( ) OSQPostFront ( ) OSQQuery ( )

Part B
11) (a) (i) Explain the various forms of memories present in a system ? (8)
In a system there are various types of memory. The figure shows a chart for various forms of
memory that are present in systems.
Fig 1.4
1. Internal RAM of 256 or 512 bytes in microcomputer for registers, temporary data and
stack.
2. Internal ROM/PROM/EEPROM for about 4 kB to 64 kB of program (in case of
microcontrollers).
3. External RAM for temporary data and stack (in most systems) or internal caches in the
case of certain micro processors).
4. Internal flash (in many systems the results of processing can be saved in nonvolatile
memory: for example, system status periodically and images songs or speeches after
suitable format expression).
5. Memory stick (or card): video, images, songs, or speeches and large storage in digital
camera and mobile systems. Sony memory stick Micro (M2) is of size 15 x 12.5 x 1.2
mm and has a flash memory of 2 GB. It has a data transfer rate of 160 Mbps (mega bits
per second) and PRO-HG 480 Mbps and 120 Mbps write.
6. External ROM or PROM for embedding software (in almost all system other than
microcontroller-based system.
7. RAM memory buffers at ports.
8. Caches (in pipelined and superscalar microprocessors).
Functions of memories in a system Table 1.1

(a) (ii) List the hardware units that must be present in the embedded systems.(8)
Embedded hardware units and devices in a system
Power source
Most of the system has a power supply of its own. The network interface card (NIC) and
graphic accelerator are examples of embedded systems that do not have their own power supply
and connect to pc power supply lines. The supply has specific operation range or a range of
voltages. Various units in an embedded system operate in one of the following four power
ranges: 5.0V 0.25V, 3.3V 0.3V, 2.0V 0.2V and 1.5V 0.2V.There is generally an inverse
relationship between propagation delay in the gates and operational voltage. Therefore, the 5
Volt system processor and units are used in most high performance systems.
Certain systems do not have a power source of their own: they connect to external power
supply or powered by the use of charge pumps (made up of diode and capacitor that accumulate
charge from the bus signals through which they connect or network to the host or from wireless
radiation.
Low voltage operations
1. In portable or hand-held devices such as a cellular phone[when compared to 5V, a CMOS
2V circuit power dissipation reduces by one-sixth,~(2V/5V)3 .This also increases the time
intervals needed for recharging a battery by a factor of six.].
2. in a system with smaller overall geometry, low voltage system processors and IO circuits
generate lesser heat and thus can be packed into a smaller space.
A power supply source or a charge pump is essential in every system.

Clock oscillator circuit and clocking units

The clock controls the time for executing an instruction. After the power supply, the
clock is the basic unit of a system. A processor needs a clock oscillator circuit. The clock
controls the various clocking requirements of the CPU, of the system timers and the CPU
machine cycles. The machine cycles are not for fetching codes and data from memory and then
decoding and executing them at the processor and for transferring the results to memory.
For processing units, a highly stable oscillator is required and the processor clock-out
signal provides the clock for synchronizing all systems units with the processor.
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System timers and real time clocks

A timer circuit is suitably configured as the system-clock, which ticks and generates
system interrupts periodically; for example, 60 times in 1s.The interrupt device service routines
then perform the required operation.
A timer circuit is suitably configured as the real-time clock (RTC) that generates systems
interrupts periodically for the schedulers, real-time programs and for periodic saving of time and
date in the system.
The RTC or system timer is also used to obtain software controlled delays and timeouts.
An RTC functions driver for software timers (SWTs)
Micro controllers also provide internal timer circuits for counting and timing devices.
To schedule the various tasks and for real time programming, an RTC or system clock is
needed. The clock also drives the timers for various timing and counting need in a system.

Reset circuit, Power-up Reset and watchdog-Timer reset

The program counter holds the address from where the instruction is to be fetched for
execution. In 80x86 processors, the instruction pointer (IP) holds that address. A code segment
register (CS) holds the base address of the code memory segment. The CS address equals the
code starting address when the IP=0 at the start of the code segment. The IP increments when the
program executes the codes.
Reset means that the processor begins the processing of instructions from a starting
address. That address is one that is set by default in processor PC(or IP and CS in x86
processors) on a power-up. From that address in memory, program instructions are fetched
following the reset of the processor. A program that is reset and runs on a power-up can be one
of the following: (i) A system program that executes from the beginning. (ii)A system boot-up
program.(iii)A system initialization program
In certain processors, for example.68HC11 and HC12, there are two startup addresses.
One is based on the power-up reset vector and the other on the reset vector after the reset
instruction or after a time-out (for example from a watch dog timer).The processor fetches the
bytes for the PC from the first power-up reset vector on power-up. The processor fetches the
bytes for the PC from the second reset vector on the watchdog timer timing out or on executing
the reset instruction.
The reset circuit activates for a fixed period (a few clock cycles) and then deactivates.
The processor circuit keeps the rest pin active and then deactivates to let the program proceed
from a default beginning address. The reset pin or the internal reset signal. The reset pin or the
internal rest signal, if connected to the other units (for example, the IO interface or the serial
interface) in the system, is activated against by the processor; it becomes an outgoing pin to
enforce a rest state in other sister units of the system. On deactivation of the reset that succeeds
the processor activation, a program executes from a start up address.
Reset can be activated by an external reset circuit that activates on power up, on
switching – on reset of the system or on detection of a low voltage (e.g. <4.5 when what is
required is 5v on the system supply rails). This circuit output connects to a pin called the reset
pin of the processor. This cicuit may be a simple RC circuit, an external IC circuit or a custom
built IC. Examples of IC’s are MAX 6314 and Motorola MC 34064.
Alternatively it can also be activated by any one of the following: (i) Software
instruction; (ii) time – out by a programmed timer known as a watchdog timer (or an internal
signal called COP in 68HC11 and 68HC12 families); (iii) A clock monitor detecting a slowdown
below certain frequencies.
The watchdog timer is a timing device that resets the system after a predefined timeout. It
is activated within the first few clock cycles after power –up. It has a number of applications. In
many embedded systems reset, a watchdog timer is very essential because it helps in rescuing the
system if a fault develops and the program gets suck. On restart, the system functions normally.
Most micro controllers have on-chip watchdog timers.
Consider a system controlling temperature. Assume that when the program starts
executing, the sensor inputs work all right. However, before the desired temperature is achieved,
the sensor circuit develops some fault. The controller will continue delivering the current non-
stop if the system is not rest. Consider another example of a system for controlling a robot.
Assume that the interfacing motor control circuit in the robot arm develops a fault during the run.
In such cases, the robot arm may continue to move unless there is a watchdog timer control.
Otherwise, the robot ill break its own arm!

Input, Output and IO ports, IO buses and IO interfaces:

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The system gets inputs from physical devices through the input ports, Examples are as
follows:
1. A system gets inputs from the touch screen, keys in a keyboard or keypads, sensors and
transducer circuits.
2. A controller circuit in a system gets input from the sensor and transducer circuits.
3. A receiver of signals or a network card gets the input from a communicating system. [A
communication system could be a fax or a modem, or a broadcasting service.]
4. Ports receive inputs from a network or peripheral.
Consider the system in an automatic chocolate vending machine. It gets input from a port
that called that a child inserts.
Consider the system in a mobile phone. A user inputs the mobile number through the
buttons, directly or indirectly (through recall of the number from its memory). Keypad keys
connect to the system through input port.
A processor identifies each input port by its memory buffer addresses, called port
addresses. Just as a memory location holding a byte or word is identified by an address, each
input port is also identified by the address. The system gets the input by the read operations at
the port addresses.
The system has output ports through which it sends output byte to the real world.
Examples are as follows.
 Output may be sent to an light emitting diode (LED), liquid crystal display (LCD) or
touch screen display panel. For example, a calculator or mobile phone system sends the
output-numbers or an SMS message to the LCD display.
 A system may send the output to a printer.
 Output may be sent to a communication system or a network.
 A control system sends the outputs to alarms, actuators, furnaces or boilers.
 A robot is sent output for its various motors.
Each output port is identified by its memory – buffer addresses (called port addresses). The
system sends the output by a write opreration to the port address.

There are also general – purpose ports for both the input and output operations.
For example a mobile phone system sends output as well as get input through a wireless
communication channel. A mobile computing system touch screen system sends output as well
as gets input when a user touches the menu displayed or key on the screen.
Each IO port is also identified by an address to which the read and write operations both
take place.
Ports can have serial or parallel communication with the system address and data buses.
In serial communication, a one-bit data line is used and bits are sent serially in successive time
slots. Universal asynchronous receiver and transmitter (UART) is a popular communication
protocol for serial communication. In parallel communication, several data lines are used and
bits are sent in parallel.
A system port may have to send output to multiple channels. A multiplexer or de-
multiplexer is then used.
A demultiplexer is a digital circuit that sends digital output at any instance to one of the
provided channels. The channel to which the output sent is the one that is addressed by the
channel address bits at the demultiplexer input.
A demultiplexer takes the input and transfers it to a select channel output among the
multiple output channels.
A multiplexer is a digital circuit that receives the digital inputs at any instance from
multiple channels and sends data output only from a specific channel at an instance. The channel
address bits are at multiplexer input. The multiplexer takes the input from one among the
multiple input channels and transfers a selected channel input to the output.
A system unit (for example, memory unit or IO port or device) may have to be selected
from among the multiple units in the system and activated. A decoder circuit when used as
addres decoder decodes the input addresses and activates the selected output channel from
among the many outputs. For example, eight units of which one has to be selected. An address –
select input of three bits is input to the decoder based on the input address the output select line
among the eight activates. If the input address bit is 000 then the 0th output is active and the 0th
unit activates. If the input address bit is then the 7th output is active and the seventh unit
activates.

Bus:
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A system might have to be connected to a number of other devices and systems. A

bus consists of a common set of lines to connect multiple devices, Hardware units and systems
for communication between any two of these at any given instance. A bus communication
protocol specifies how signals communicate on the bus. A bus may be a serial or parallel bus that
transfers one or multiple data bits at an instance, reapectively. The protocol also specifies the
following; (i) Ways of arbitration when several devices need to communicate through the bus;
(ii) Ways of polling bus requirement from each device at an instance; (iii) Ways of daisy
chaining the devices so that the bus is granted to a device according to the device – priority in the
chain
For networking the distributed units or system, there are different types of serial
and parallel bus protocol; I2C, CAN, USB, ISA, EISA and PCI. For wireless networking and
system there are 802.11, IrDA, Bluetooth and ZigBee protocols.
A ystem connects to external physical devices and systems through parallel or
serial I/O ports. Demultiplexers and multiplexers facilitate communication of signals from
multiple channels through a common path. A system often networks to other devices and
systems through an I/O bus: For example I2C, CAN, USB, ISA, EISA and PCI bus.

DAC using a PWM and an ADC

DAC is a circuit that converts digital 8 or 10 or 12 bits to the analog output. The analog
output is with respect to the reference voltage. When all the input bits are equal to 1, then the
analog output is the difference between the positive and negative reference pin voltages; when all
inputs equal 0, then the analog output refernce equals negative reference pin voltage(usually 0
volt).
Suppose a system needs to give to the analog output of a control circuit for automation.
The analog output may be to the power system for d.c.motor or furnace.
A pulse width modulator (PWM) with an interior circuit is used for the DAC. A PWM
unit in the microcontroller operates as follows:Pulse width width is made proportional to the
analog output needed. PWM inputs are from 00000000 to 11111111 for an 8-bit DAC operation.
The PWM unit outputs to an external integrator which provides the desired analog output. From
this information, the formula to obtain the analog output from the bits in a given PWM register
with bits ranging from 00000000 to 11111111 is as follows:Analog output V=K.pw where K is
the constant and pw is the pulse width.
Suppose a circuit (external to the micro controller) gives asn output of 1.024V when the
pulse widthis 50% of the total pulse time period, and 2.047V when the width is 100%. When the
width is made 25%, by reducing by half the value in the PWM output control register, the
integrator output will become 0.512V. the constant K depends on the integrator amplifier gain.
Assume the integrator operates with a dual (plus –minus) supply. The PWM unit in the
microcontroller operates by another method, wqhich is as follows. Assume that when an
integrator circuit gives an output of 1.023V, the pulse width is 100% of the total pulse time
period and of -1.024V when the width is 0%. When the width is made 25% by reducing by half
the value in an control register, the integrator output will be 0.512V at 50% the output will be
0.0V. From this information the formula to obtain the analog output from the bits in a given
PWM register ranging from 00000000 to 11111111 in both the situations is as follows: analog
output V=0.001k’(pw-50) where k’ is constant and pw is pulse width time in percentage with
respect to pulse time period. K’ depends on integrator amplifier gain.

Analog to digital converter

ADC is a circuitthat converts the analog input to digital 4,8,10 or12 bits.The analog input
is applied between the positive and negative pins and it is converted with respect to the reference
voltage. When input is equal to difference of reference positive and negative voltages, then all
output bits equal 1;when equals negative reference voltage (usually 0V), then all output bits
equal 0.
The ADC in the system microcontroller may be used in many applications such as data
acquisition systems (DAS), digital cameras, analog control systems and voice digitizing systems.
Suppose a system gets the analog inputs from sensors of temperature, pressure, heartbeats and
other sources in a DAS. Suppose a system gets the analog inputs from a digital camera. It has
CCD (charge Couple Device) which has tiny pixels that charge up on exposure to light. The
charging of each pixel depends upon the light intensity at that point in the image. The analog
inputs to the system generate from each pixel. Each pixel’s analog input has to be converted into
bits to enable processing in the next stage.
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Suppose a system needs to read an analog input from a sensor or transducer circuit. If
converted to bits by the ADC unit in the system, then these bits after processing can also give an
output. This provides control for automation by a combined use of ADC and DAC features.
The converted bits can be given to the port meant for digital display. The bits may be
transferred to a memory address, a serial port or a parallel port.
A processor may process the converted bits and generate a Pulse Code Modulated (PCM)
output. PCM signals are used to digitize voice into a digital format.
Important points about the ADC are as follows:
1. Either a single or dual analog reference voltage-source is required in the ADC. It sets
either the analog input’s upper limit or the lower and upper limits both. For a single
reference source, the lower limit is set to 0 V (ground potential). When the analog input
equals the lower limit, the ADC generates all bits as 0s, and when it equals the upper
limit it generates all bits as 1s. [As an example, suppose in an ADC the upper limit
reference voltage is 2.255 V. Let the lower limit reference voltage be 0.255 V. The
difference in the limit is 2 V. therefore the resolution will be 2/256 V. If the 8-bit ADC
analog input is 0.255 V., the converted 8 bits will be 00000000. when the input is 0.255
V +1.000 V, the converted bits will be =1.255 V, the biots will be 10000000. whwn the
analog input is 0.255 V + 0.50 V, the converted bits will be 01000000. [ From this
information, finding a formula to obtain converted bits for a given analog input = V volt
is as follows: Binary number n bits after conversion in an n-bit ADC corresponds to
decimal number N, then N-v. (Vref+-Vref-)/2n. Here, Vref+ is the reference voltage that
gives all the bits that are equal to 1 and Vref- is the reference voltage that gives all the bits
that are equal to 0.]
2. An Adc may be of 8, 10, 12 or 16 bits depending upon the resolution needed for
conversation.
3. The start of the conversion (STC) signal or input initiates the conversion to 8 bits. In a
system, an instruction or timer signals the STC.
4. There is an rnd of conversion (EDC) signal. A flag in a register is set to indicate the end
of conversion and the ADC generates an interruot ; the ISR reads the ADC bits and saves
them in the memory buffer.
5. There is a conversion time limit in which the conversion is definite.
6. A Sample and Hold (S/H) unit is used to sample the input for a fixed time and hold till
converstion is over.
An ADC unit can be repeatedly used after the intervals equal to the conversion time.
Therefore, one can digitizes the DAS sensor signals, voice, music or video signals in different
systems. An ADC unit in an embedded system microcontroller may have multichannels. It can
then take the input in succession from the various pins interconnected to different analog
sources.

For automatic control and signal processing applications, a system provides necessary
interfacing circuit and software for the digital to analog conversion (ADC) unit. A DAC
operation is done with the help of a combination of a PWM unit in the microcontroller and an
external integrator chip. ADC operations are required for data acquisition, image processing,
voice processing, video processing, instrumentation and automatic control systems.

LCD, LED and Touch screen Displays

A system requires an interfacing circuit and software to display the status or message for
a line, for multilane displays, or for flashing displays. An LCD screen may show up a multilane
display of characters are also show a small graph or icon (called a program). A recent innovation
in the mobile phone system turns the screen blue to indicate an incoming call. Third generation
system phones have both images and graphics. An LCD needs little power. A supply or battery
(A solar panel in the calculator) powers it. The LCD is a diode that absorbs or emits light and 3
to 4 V and 50 to 60 Hz pulse with currents less the 50 µA are required. The pulses are applied
with same polarity with the same polarity on the crystal front and back plane for no light, and
with opposite polarity for light. Here, polarity means logic 1 or 0. A display-controller is often
used in case of matrix displays.
To indicate the ON status of the system, there may be an LED that glows. A flashing
LED may indicate that a specific task is under completion or is running or in wait status. The
LED is a diode that emits yellow, green, red or infrared light in a remote controller on
application of forward voltage between 1.6-2 V. it needs current up to 12 mA above 5 mA (less
in flashing diode mode). It is much brighter than the LCD, making it suitable for flashing
displays and for displays limited to few digits.
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A touchscreen is an input as well as an output device, which can be used to enter a

command, a chosen menu or to give a reply. The information is input by physically touching at a
screen position using a finger or a stylus.
A stylus is a thin pencil-shaped object. It is held between the fingers and used just like a
pen. The screen displays the choices or commands, menus, dialog boxes and icons. The display-
screen display is similar to a computer video display unit screen. Newer touchscreen senses the
fingers even from the proximity, for example, in Apple iPhone.

Keypad/ keyboard
The keypad or keyboard is an important device for getting user inputs. The system
provides the necessary interfacing and key debouncing circuit as well as the software for the
system to receive input from a set of keys, from a keyboard, keypad or virtual keypad. A
touchscreen provides for virtual keypad in a mobile computing system. A virtual keypad is a
keypad displayed on the touch screen where the user can enter the keys using a stylus or finger.
A keypad has upto a maximum of 32 keys. A keyboard may have 104 keys or more. The
keypad or keyboard may interface serially or parallelly to the processor directly through ports or
through a controller. Mobile phones may have a T9 keypad. A T9 keypad has 16 keys and four
up-down right-left menu keys. Using 0 to 9 keys text messages, such as SMS messages, are
generated.

Pulse Dialer, Modem, and Transceiver

For user connectivity through the telephone line, wireless or a network, as system
provides necessary interfacing and circuits. It also oprovides the software for pulse dialing
through the telephone line, for modeminterconnection for fax, for internet packets routing and
for transmitting and connecting to a wireless cellular system or personal area wireless network.
A transceiver is a circuit that can transmit as well as receive byte stream.

Interrupt handler
A timer device sends a time-out interrupt when a preset time elapses or sends a compare
interrupt when the present-time equals the preset time. Assume that data have to be transferred
from a keyboard to a printer. A port peripheral generates an interrupt on receiving the input data
or when transmitting buffer becomes empty. Each action generates an interrupt. A system may
possess a number of devices and the system processor has to control and handle the requirements
of each device running an appropriate ISR (interrupt service routine) for each. An interrupt-
handling mechanism must exist in each system to handle interrupt from various processes and for
handling multiple interrupts simultaneously pending for service. Important points regarding the
interrupts and their handling by the program are as follows:
1. There can be a number of interrupt services and groups of interrupt services in a
processor. An interrupt may be hardware signal that indicates an occurrence of an
event.[For Example: a real-time clock continuously updates a value at a specified
memory address; the transaction of that value is an event that causes an interrupt]. An
interrupt may also occur through timers, through an interrupting instruction of the
processor program or through an error during processing. The error may arise due to an
illegal opcode fetch, a division by zero result or an overflow or underflow during an ALU
operation. An interrupt can also arise through a software timer. A software interrupt
may arise in an exceptional condition that may have developed while running a program.
2. The system may prioritize sources and services them accordingly.
3. Certain sources are not maskable and cannot be disabled. Some are assigned higher
priority during processing.
4. The processor’s current program has to divert to a service routine to complete that task on
the occurrence of the interrupt. For example; if a key is pressed, then an ISR reads the
key and stores the key value in the processor memory address. If a sequence of key is
pressed, for instance in a mobile phone, then an ISR reads the keys and also calls a task to
dial the mobile number.
5. There is a programmable unit on-chip for the interrupt handling mechanism in a
microcontroller.
6. The operating system is expected to control the handling of interrupts and running of
routines for the interrupts in a particular application. The system allows gives priority to
the ISRs over the task of an application.
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(b) (i) Explain the different program layers in the embedded software and also the
process of converting a ‘C’ program into the file for ROM image with suitable block
diagrams. (8)
The different program layers in the embedded software
Since the coding in assembly language is very time consuming in most cases, software is
developed in a high level language, ‘C’ or ‘C++’ or visual ‘C++’ or ‘visual Java in most cases.
‘C’ is usually the preferred language. The programmer needs to understand only the hadware
organization when coding in high level language.
As an example, consider the following problem.
Add 127, 29 and 40 and print the square root. An exemplary C language program for all
the processes is as follows:
(i) #include <stdio.h>
(ii) #include <math.h>
(iii) void main (void)
{
(iv) int i1,i2,i3;float result;
(v) i1 = 127; i2 = 29; a = i1 + i2 + i3; result = sqrt (a);
(vi) printf (result);
}
The coding for the sqrt will need many line of codes and can be done only an expert
assembly language programmer. To write the program in a high level language is very simple
compared to writing it in assembly language. The ‘C’ programs has a feature that adds the
assembly instructions when using certain processor-specific features and coding for a specific
section, for e.g, a port device driver.
Figure 1.7
The figure shows the different programming layers in a typical embeeded’C’ software.
These layers are as follows:
(i) Processor commands (ii) main function (iii) interrupt sevice routine (iv) Multple
tasks, say 1 to N. (v) kernel and scheduler (vi) Standard library functions, protocols
handling and stack functions.
Figuire 1.8
Figure 1.8 shows the process of converting a C program into the ROM image file. A
compiler generates the object codes. It assembles the codes according to the processor instruction
set and other specifications. The C compiler for the embedded systems must, as a final step of
compilation, use a code-optimizer that optimizes these before linking. After compilation, the
linker links the object codes with other needed codes. For example, the linker includes the codes
for the functions printf and sqrt codes. Codes for device and driver (Device control codes)
management also link at this stage; For example, printer device management and driver codes.
After linking, the other steps for creating a file for ROM image are the same as for the step in
obtaining the ROM image for an assembly language program.

(b)(ii) Give a brief note on exemplary applications of each type of embedded system.
Explain any one of the three categories of the embedded systems.
i. Small scale embedded system -5
ii. Medium scale embedded system -5
iii. Sophisticated embedded system -6
12. (a) (i) What are the characteristics taken into consideration when interfacing a
device and a port? (8)
The characteristics taken into consideration when interfacing a device and a port
1. A device port may have multi-byte data input buffers and data output buffers.
Suppose there is an eight bit buffer, assuming that a device (as in the 80196
microcontroller) can generate three interrupts one on receiving a byte, one on receiving
the fourth byte and the one when the buffer is full, then the deadline for serving these
interrupt increases up to 8 times compared to the case when there is a single byte register
instead of buffer.
2. A port may have a DDR (Data Direction Register) (as in the 68HC11 microcontroller).
This is an advantage since each bit of the port is now programmable.
3. Port LSTTL-driving capability and port-loading capability are important characteristics.
A port may be OD (Open drain) port. It has zero driving capability unless the drain
connects the positive supply voltage. If the given port has OD gates, an appropriate pull-
up resistance or transistor is connected to each port pin to provide the driving capability.
The drain or collector connects to the supply voltage to provide the pull-up.
 9

4. If a given port is quasi bi-directional (as in 80196), then the port pins have limited driving
capability, which suffices for a period of one or a few clock cycle and drives a LSTTL
gate for that period. when this device port connect to more than one LSTTL, then an
appropriate pull-up circuit will be required for the port pins.
5. there may be multiple or alternate functionality in the port pins; for example, 80196 input
port pins. Each pin of P2 has an alternative use as multi-channel analog input facility for
eight analog inputs. Another example is 8051 two ports P0 and P2. these ports also have
an alternate function in that they bring out when needed the internal multiplexed buses
for the external program and memories whenever the internal memory is insufficient.
Each pin of P3 in 8051 has multiple uses. These are used during serial communication,
timer-counter signals, interrupt-signals, and RD and WR control signals for external
memories. 68HC11 ports B and C are of eight bits each and have alternative uses for the
port pins in it. One of the alternate functions is to bring out the internal address and data
buses, respectively.
6. A port may have provision for multiplexed output tyo connect to multiple systems or
units.
7. A port may have provision for de-multiplexed inputs from multiple systems or units.

(a) (ii) What are the sophisticated interfacing features in device ports? (8)
Sophisticated interfacing features in device ports
A device port may not be as simple as one for a stepper motor port or for a serial line
UART. Nowadays, a complex embedded system has highly Sophisticated IO devoices, for
examples, SDIO, IO devices with fast serialization of data, fast transceivers, and real time video
processing system. The following are few Sophisticated interfacing device and port features:
(i) Let the operation voltage level expected for logic state 1 = 5 V (TTL or CMOS). The
Schimitt trigger circuit has a property that when a transition from 0 to 1 occurs, only if
the voltage level exceeds 2/3 of the 5 V level is there a transition to 1. Similarly, when a
transition from 1 to 0 occurs, only if the voltage level lowers blow 1/3 of the 5 V level is
there a transition from 1 to 0. Hence the Schimitt trigger circuit eliminates noise as large
a 2/3 of the 5 V or 3.3 V, when it is superimposed at an input line to the device.
Advantage:
Advantage of the inbuilt Schimitt trigger circuit at the port is conditioning of signal by
noise elimination. Otherwise, a device port input will need an external chip for Schimitt
trigger-based noise elimination. Such a device is used in transceivers for repeating
systems, which are used in long distance communication.
(ii) When a device port is waiting for instructions, power management can be done at the
gates of the device. Lately, a new technology called DataGate (from Xilinx) has been
developed for use at ports. DataGate is a programmable ON/OFF switch for power
management; DataGate makes it possible to reduce the power consumption by
unnecessary toggling of input when these are not in use.
Advantage:
It reduces power dissipation when the device port is operated at fast speeds. Such a
device is extremely useful in systems connected to a common bus and there is a need to
control unnecessary input toggling. For example, in a bus interface unit, the input signal
should activate only when the input has to be passed to the circuit. As the number of bus
interfaces in the system grows, the demand to prevent needless switching of input signals
increase.
(iii) Earlier, port interfaces used to be either open drain CMOS or TTL or RS232C.
Nowadays, a system may be required to operate at a voltage lower than 5 V. Low voltage
TTL and low voltage CMOS gates may be used at device ports for 1.5 V IO.
Nowadays, a system may be required to operate using advanced IO standard interfaces.
Example, are high speed Transceiver logics (HSTL) and stub-series terminated logic
(SSTL) standards. HSTL issued for high speed operations. SSTL is used when the buses
are to be isolated from relatively large stubs.
(iv) A device connects to a system bus and also to IO bus when it is networked with other
devices. Devices and buses impedance during an IO must match. Else, line reflection
occurs. Recent developments make it feasible to match these dynamically. For example, a
new technology, called XCITE (Xilinix Controlled Impedance Technology) can be used.
Advantage:
When the resistors are replaced digitally, dynamic controlled and matched impedances
occur in the device, and there are no line reflections and therefore no missing bits or bus
faults.
 10

(v) An IO device may consist of multiple gigabit (622Mbps to 3.125 Gbps) transceivers
(MGTs). Special support circuitry is needed for this rate. Rocker IOTM serial transceivers
are examples of circuits that provide support circuitry at this rate.
(vi) A device for an IO may integrate a SerDes (serialization and De-serialization) sub-unit.
SerDes is a standard subunit in a device where the bytes placed at ‘transmit holding
buffer’ serialize on transmission and once the bits are received these de-serialize and are
placed at the ‘receiver buffer’. Once the device SerDes sub-unit is configured,
serialization and de-serialization is done automatically without the use of the processor
instructions.
Advantage:
The serialization and de-serialization operations are fast when compared to operations
without SerDes. [A device for IO may integrate a DAA (Direct Access Arrangement
using analog IOs along with one master and seven slave CODECs) or McBSP (multi
channel buffered serial port with high speed communication) sub-unit when serializing].
(vii) Recently, multiple IO standards have been developed for IO devices. A support to the
multiple IO standards may be needed in certain embedded systems. A technology,
Flexible select IOTM – Ultra Technology, supports over 20 single-ended and differential
IO signaling standards. Advantages of multiple standard ports are obvious.
(viii) An IO device may integrate a digital physical sub layer (PCS). Analog audio and video
signals can then be pulse code modulated (PCM) at the sub layer. The PCS sub layer
directly provides codes from analog inputs within the device itself. The codes are then
saved in the device data buffers.
Advantage: of an inbuilt PCS at device port is that there is then no need of external PCM
coding. Besides these operations are performed in the background, they are also fast. It
improves the system’s performance when there are multimedia inputs at the device.
(ix) A device for IO may integrate an analog unit Physical Media Attachment (PMA) for
connecting direct inputs and outputs of voice, music, video and images.
(x) The greatest advantage of inbuilt PMA is that the device directly connects to the
physical media. PMA is needed for real-time processing of video and audio inputs at the
device.

(b)(i) Tabulate the uses of timer device with applications and explanations. (8)
Uses of timer devices
Sl. No Applications And Explanations
1 Real-time clock ticks (functioning as system heart beats) [Real time clock is a clock
that once the system starts it, does not stop and can’t be reset. Its count value can’t be
reloaded. Real time endlessly flows and never returns] Real time clock is st for ticks
using prescaling bits and rate-set bits in appropriate control registers.
2 Initiating an event after a preset delay time. Delay time is as per count value loaded.
3 Initiating an event (or a pair of event or a chain of events) after a comparison between
the preset time with counted value. Preset time is loaded in a Compare Register. [It is
similar to presetting an alarm.]
4 Capturing thecount-value at the timer on an event. The information of time (instance
of the event) is thus stored at the capture register.
5 Capturing the time interval between two events. Counts are captured at each event in
the capture register and read. The intervals are thus found out. A service routine does
the counts read on interrupt.
6 Wait for a message from queue or mailbox or semaphore for a preset time when using
an RTOS. There is a predefined waiting period before RTOS lets a task run withoiut
waiting for the message.
7 Watchdog timer. It resets the system after a defgined time.
8 Baud or bit rate control for serialcommunication on a line or network.timer timout
interrupt the clock inputs. The timer acts as a counter if, in place of clock inputs, the
inputs aregiven to the timer for each instance to be counted.
9 Input pulse counting when using a timer, which is ticked by giving non-periodic inputs
instead of the clock inputs. The timer acts as a ciounter if, in place of clock inputs, the
inputs are given to the timer for each instance to be counted.
10 Scheduling of various tasks. A chain of software-timer interrupts and RTOS uses these
interrupts to schedule the tasks.
11 Time slicing of various tasks. A multitasking or multiprogramming operating system
presents the illusion that multiple tasks or programs are running simultaneously by
switching between programs very rapidly, for example after every 16.6 ms. This
 11

process is known as context switch. RTOS switches after preset time-slice from one
running task to the next.
12 Time division multiplexing (TDM). Timer device is used for multiplexing the input
from a number of channels. Each channel input is allotted a distinct and fixed-time slot
to get a TDM output. [For example, multiple telephone calls are the inputs and TDM
device generates the TDM output for launching it into the optical fibre.]

(b) (ii) Explain the signals during a transfer of a byte when using the I2C bus and
also the format of the bits at the I2C bus with diagrams. (8)
Assume that there are number of device circuits in a number of processes in a plant, one
IC each for measuring temperatures and pressures. These I2C mutually network through a
common synchronous serial bus. I2C (Inter IC connect) bus is a popular bus for these circuits.
There are three I2C standards: Industrial 100kbps I2C, 100kbps SM I2C, and 400 kbps I2C. the
I2C was originally developed at Philips semiconductors.
The I2ZC bus has two line that carry its signals – one line for clock and one is for
bidirectional data. There is a protocol for I2C bus. Figure 3.10 (a) shows the signals during a
transfer of a byte when using I2C bus.
Each device has an address using which the data transfers take place. The master can
address 127 slaves at an nstance. It has a processing element functioning as a bus controller or a
microcontroller with I2C buas interface circuit. Each slave also optionally have an I2C bus
controller and processing element. A number of masters can also connect to the bus. However, at
any instance, there can be only one master, which transmits the SCL (serial clock) pulses. From
the master or slave, a data frame has fields beginning from start bit as per Table 3.9. Figure 3.10
(b) shows the format of the bits at the I2C bus.
Disadvantage
The disadvantage of this bus is the time taken by the algorithm in the master hardware
that analyses the bits through I2C in case the slace hardware doesnot provide for the hardware
that supports. Some ICs support the protocol and some donot. In that case, interface circuits for
those ICs are also required. Also, there are open collector drivers at the master. Therefore, a pull-
up resistance 2.2 k or an active circuit for pull0-up of line to logic 1 for on each line is essential.
13. (a)(i) Tabulate program elements: macros and functions and their uses. (8)
Program Uses
Element
Macro Executes a named small collection of codes
Function Executes a named set of codes with values passed by the calling
program through it arguments. Also returns a data object when it is
not declared as void. It has the context-saving and retrieving
overheads.
Main function Declaration of function anddata types, typedef and either
(i) Executes a named set of codes, call a set of functions and
call on the interrupts the ISRs or
(ii) Starts OS kernel.
Reentrant Reentrant function is usable by several tasks and routines
function synchronously (at the same time). This is because all its argument
values are retrievable from stack of local variables, data structures and
objects. A function is called re-entrant function when the following
three conditions are satisfied.
(i) None of the argument should be pointers.
(ii) When the operation is not atomic none of the variable
should be outside the function.
(iii) The function should not call another function that is not
itself re-entrant.
Interrupt service Declaration of functions and data types, typedef and executes a named
routine (ISR) set of codes. Must be short so that other sources of interrupts are also
serviced within the deadlines. Must be re-entrant routine. Not allowed
to wait for interprocess messages (semaphore or mailbox or queue
messages) but allowed to send the interprrocess messes for the ISTs or
tasks.
Process or task Must be either re-entrant routine or must have a solution to the shared
or thread data problem.
Recursive A function that calls itself. It must be re-entrant function also. Most
function often its use is avoided in embedded systems due to memory
 12

constraints. (stack grows after each recursive call and it may choke the
memory space availability.

(a) (ii) Explain the use of pointers, NULL pointers. (8)

Use of pointers and NULL pointers
Pointer
Pointers are powerful tools when used correctly and according to a certain basic
principles. Pointer is a reference to a starting memory address. A pointer can refer to a variable,
data structure and function. Before a pointer, in C language,. * is used.
Example:
unsigned char *0x1000 ;
Mean a character of 8 bits at address 0x1000.
NULL pointer
A NULL pointer is declared as follows:
#define NULL (void*) 0x0000;
We can assign any address instead of 0x0000 that is not in use in a given hardware.
Example
1. Consider unisigned short *timer1;
Pointer timer1 will point to two bytes, and the compiler will reserve two memory
addresses for the content of timer1.
Consider two statements:
unisigned short *timer1; and
timer1++;
the second statement adds 0x0002 in the address of timer1.
In c, if x is a variable, then x++ means increment of the value of x by 1. if p is a pointer,
then p++ means increment of the value of p to the next address.
timer1++ means point to the next address, and unsigned short declaration allocated two
address for timer1. (timer1++; or timer1 +=1; will have identical action.) therefore next
address is 0x0002 more than the address of timer1 that was originally defined. Had the
declaration been unsigned int *timer1; and timer1++; (incase of 32 bit timer), the second
statement would have incremented the address by 0x0004.
2. Let a byte each be stored at each memory address. Let a port A in a system have a buffer
register that stores a byte. Now a program using a pointer declares the byte at port A as
follows:
Unsigned byte *portA;
The * means ‘the content at’. This declaration means that there is a pointer and an
unsigned byte for portA. The compiler will reserve one memory address for a byte.
3. Consider declarations as follows:
Void *portAdata;
The void is the undefined data type for portAdata. The compiler will allocate address for
the portAdata without any type check.
4. A pointer can be assigned a constant fixed address. Two preprocessor directives:
#define portA (volatile byte *)0x1000;
#define PIOC (volatile unsigned byte *) 0x1001.
Alternatively, the addresses in a function call can be assigned as follows:
Volatile unsigned byte * portA;
*PIOC = (unsigned byte *) 0x1001;
An instruction ‘portA++;’ will make the portA pointer point to the next address and which is
PIOC.
5. Consider,
unsigned byte portAdata;
unsigned byte *portA = &portAdata;
The first statement directs the compiler to allocate one memory address for portAdata
because there is a byte each at an address. The & (ampersand sign) means ‘at the address
of’ . this declaration means the positive number of 8 bits (byte) pointed at portA is
replaced by the byte at the address of portAdata. The right side of the expression
evaluates the contained byte from address, and the left side puts that byte at the pointed
address. As the right side variable of portAdata is not declared pointer, the ampersand
sign is kept to point to its address so that the right side pointer gets the contents (bits)
from the address.
Note:
The equality sign in a program statement means ‘is replaced by’.
 13

(b) (i) What are the advantages of using multiple function calls in cyclic order in the
main? Also write the advantages of building ISR queues? (4+4)
Advantage of Multiple Function calls in cyclic order
The most
common method is for multiple function calls to be made in a cyclic order.
The ‘C’ code for an infinite loop for 64kbps network problem is given as,
# define false 0
# define True 1
Void main (void)
{
rtos.run ( );
{
Void task1 ( )
{
…….
}
Void task 2( )
{
…….
}
Void task n( )
{
……
}
}
The multiple function calls are defined in the main function for execution in cyclic order
be modeled such as

Include Files
↓
Void main(){
↓
Declaration
↓
Calling Fn1
↓
Calling Fn 2
↓
.
;
Calling Fn n
↓
}

(b) (ii) What are the programming advantages of C++? What are the disadvantages
of C++? (4+4)
 It supports the procedure oriented codes of C.
 It has the advantages of OOPs as well as C and In-Line assembly.
 Programming concepts for embedded programming in C++ are as follows,
 A class binds all the member functions together for creating objects.
 A class can derive from another class also
 Method overloading:-Methods can have same name in the inherited class.
 Method overriding:-Methods can have same name as well as same number and type
of arguments in the inherited class.
 Operators in C++ can be overloaded like in method overloading.
Disadvantages of C++ programming (4 marks)
i. Program codes become lengthy, particularly when certain features of the standard C++
are used.
ii. Example: Templates, Exceptional handling, Multiple Inheritance
 14

14. (a) (i) List the goals of operating system services. (8)
Goals of Operating Systems
1. Facilitating easy sharing of resources as per schedule and allocation Resources mean
processor(s), memory, IOs, devices, virtual devices (e.g. pipes, sockets), system timer,
keyboard, displays, printer and other such resources, which processes (task or threads)
request from the OS. No processing task or thread uses any resource until it has been
allocated by the OS at a given instance.
2. Facilitating easy implementation of the application program with the given system
hardware. An application programmer for a system can use the OS function that are
provided in the OS without having to write the codes for the services (functions) that
follow.
3. Optimally scheduling the processes on one (or more CPU if available) and providing an
appropriate context-switching mechanism.
4. Maximizing the system performance to let different processes (tasks or threads) share the
resources most efficiently with protection and without any security breach.
Example of security breach:
Tasks obtaining illegal access to other task-data directly without system calls, overflow
of the stacks into memories and overlaying of PCB at the memory.
5. Providing management functions for the processes (tasks and threads) memory, devices.,
and IOs and other functions.
6. Providing managements and organization functions for the drivers, files and virtual
devices and IOs.
7. Providing easy interfacing and management functions for the network protocol and
networking.
8. Providing portability of application on different hardware configuration.
9. Providing interoperability of application on different networks.
10. Providing a common set of interfaces that integrates various devices and application
through the standard and open system.

(a) (ii) Explain three alternative systems in three RTOSs for responding to a
hardware source call with diagrams. (8)
Direct Call to ISR by an Interrupting Source and ISR sending an ISR Enter Message
Figure 8.1(a) shows the steps. On an interrupt, the process running at the CPU is
interrupted and the ISR correspong to that source starts executing (step 1). A hadware source
calls an ISR directly. The ISR just sends an ISR message to the OS (step 2).
Os is simply sent an ISR message (ISM) from the ISR in step 2. Later the ISR code can send into
a mailbox or message queue (step 3) but the task waiting for the mailbox or message queue doest
not start bfre the return from the ISR ( 4). The ISR enter message in step 2 is to inform the OS
that an ISR has taken control of the CPU. The ISR continues execution of the code needed for
the interrupt service till the ISR exit message is sent just before the return (step 4).
RTOS First Interrupting on an Interrupt, then OS Calling the Corresponding ISR
Figure 8.1 (b) Shows the steps. On interrupt of a task, say, k-th task, the OS first gets the
hardware source call (step 1) and initiates the corresponding ISR after saving the present process
status (or context) (step 2). The called ISR (step 3) during the execution then can post one or
more output (step 4) for the events and messages ito the mailboxes or queues.
Assume that there are the routine (i-th ISR) and two processes (OS andj-th task) in three
memory blocks other than the interrupted k-th task. An i-th interrupt source causes the OS to get
the notice of that, then after that step 1 it finishes the critical code till the pre-emption point and
call the i-th ISR. ISR_i executes (step 3) after saving the context (step 2) onto the stack. The pre-
emption point is the last instruction of the critical part of the presently running OS function, after
which the ISR being of highest priority is called. The USR in step 4 can post the event or
mailbox message (s) to the OS for initiating the j-th task or k-th task after the return (step 5) from
the ISR and after retievibng the j-th or k-th task context.
RTOS First Interrupting on an Interrupt, then the RTOS Initiating the ISR and then an
ISR
An RTOS can provide for two levels of ISRs, a fast-level ISR, FLISR and slow-level
ISR (SLISR). The FLISR can also be called hardware interrupt ISR and the SLISR as software
interrupt ISR. FLISR is called just the ISR in RTOS Windows CE. The SLISR is called interrupt
service thread (IST) in windows CE. The use of FLISR reduces the interrupt latency (waiting
period) for an interrupt service and jiter (worsr case and best case latencies differences) for an
interrupt service.
 15

An IST function as a deferred procedure call (DPC) of the ISR. An i-th IST is a tread to
service an i-th interrupt source call.
Figure 8.1 (c ) shows the seven steps on the interrupt. On interrupt, the RTOS first gets
the hardware source call (step 1) and initiates the corresponding ISR after finishing the critical
section and reaching the pre-emption point and then saving the processor status (or context) (step
2). The ISR executes the device- and platform dependent code (step 3). The ISR at the start can
mask (disable) further pre-emption from the same or other hardware soyurces. The ISR during
the execution then can send one or more outputs for the events and messages into the mailboxes
or queues for the ISTs (step 4). The IST executeds the device- and platform- independent code.
The ISR just before the end, unmasks (enables) further pre-emption from the same or other
hardware sources (step 5).
There are the ISRs and number of ISTs, RTOS and tasks in the memory blocks other than
the interrupted task. Any interrupt source causes the RTOS to get the notive of that, then
completes the critical code till the pre-emption point and calls the ISR. ISR executes after saving
the context on to the stack. The ISR can post messages into the FIFO for the IST(s) after
recognizing the interrupt source and its priority. The ISTs in the FIFO that have received the
message from the ISR(s) executes (step 6) as per their priorities on return (step 5) from the ISR.
The ISR has the highest priority and pre-empts all pending ISTs and tasks.
When no IST or ISR is pending execution in the FIFO, the interrupted task runs on
return (Step 7).

(b) (i) What are the 15 points strategies must be taken into account for designing
the codes for synchronization between the processes, ISRs, OS functions and tasks
and for resource management. (8)
1. No ISR Instruction blocks any task. An ISR can only send the messages to RTOS &
parameter to task.
2. ISR coding should be like a reentrant function with no shared data problems. ISR codes
should not wait for actions by the RTOS or task.
3. Each task is under RTOS control. A task should not call another task.
4. Using RTOS call only task can send or receive messages.
5. While executing critical section code, disabling pre-emption is better than disabling
Interrupts
6. Resource locking using mutex semaphore is better than disabling interrupts or disabling
pre-emption
7. A task should take the semaphore only during a short period in which the critical section
alone is executed.
8. Relative Response time concept is advisable only for limited no. of multitask.
9. Use signals for most urgent IPC.
10. Create task at start up only and avoid creating and deleting task later.
11. Semaphores, queues & messages should not be globally shared variable and each should
be shared between a set of tasks only
12. Use idle CPU time for internal functions.
13. If memory allocation and de –allocation is done by a task, the no. of RTOS functions is
minimized this reduces Interrupt latency.
14. Use configurable RTOS which can put needed function from the scheduler.
15. Use appropriate precedence assignment strategy.

(b) (ii)Explain a scheduler in which the RTOS inserts into a list the ready tasks for
sequential execution in a cooperative round robin model. (8)
Round Robin Time Slicing Scheduling
Definition
A task may not complete in its allotted time frame. Round Robin means that each ready
task runs in turn only in a cyclic queue for a limited time slixce Tslice. Tslice. = Tcycle /N, where N
= Number of tasks. It is a widely used model in traditional OS. Round Robin is a hybrid model
of the clock-driven model (E.g.: Cyclic model) as well as event driven (E.g. Pre-emptive).
A real-time system response to the event is within a bounded time limit and within an
explicit time. A scheduler for the time-constraint tasks in the round Robin mode can be
understood by a simple example.
Example
Suppose after ever 20 ms, there is a stream of coded messages reaching at port A of an
embedded system, it is then decrypted and retransmitted to the port after encoding each
 16

decrypted message. The multiple processes consist of five tasks C1, C2, C3, C4, and C5 as
follows.
1. Task C1: checks for a message at port A every 20 ms.
2. Task C2: Read port A and put the message in the message queue.
3. Task C3: Decrypt the message from the message queue.
4. Task C4: Encode the message from the queue.
5. Task C5: Transmit the encoded message from the queue to port B.
Figure 8.5 (a)

Figure shows five tasks, C1 to C5 that are to be scheduled. Figure shows the five contexts
in five time schedules, between 0 and 4 ms, 4 and 8 ms, 8 and 12 ms, 12 and 16 ms, and 16 and
20 ms respectively.
Let OS initiate C1 to C5, let there be a slice-clock tick interrupt at each 4 ms. Task C1 is
scheduled by OS to bring it to the running state from its blocked state as soon as a timer triggers
an event. If it is known that after every 20 ms, a byte reaches port A, a timer interrupt triggers an
event every 4 ms. Task C1 runs with 4 ms, and C2 starts running.
Figure shows at different time slices the real-time schedules, process context and saved
context. Figure 8.5(b)
1. At the first instance (first row) the context is C1 and task C1 is running.
2. At the second instance (Second row) after 4 ms, the OS switches the context to C2. Task
C1 is finished, C2 is running. As task C1 is finished, nothing is saved on the task C1
stack.
3. At the third instance (third row), the OS switches the context to C3 on next timer
interrupt, which occurred after 8 ms from the start of task C1. Task C1 is finished, C2 is
blocked and C3 is running. Context C2 is saved on task C2 stack because C2 is in
blocked state.
4. At the fourth instance (Fourth row), the OS switches the context to C4 on timer interrupt
which occurred after12 ms, from the start of task C1. Task C! is finished, Context C2, C3
are blocked and C4 is running. Contexts of C2 and C3 are at the tasks C2 and C3 stacks,
respectively.
5. At the fifth instance (Fourth row), the OS switches the context to C5 on the next timer
interrupt which occurred after 16 ms from the start of task C1. Task C1 is finished, C2,
C3, and C4 are blocked and C5 is running. Contexts C2, C3, and C4 are at the tasks C2,
C3, and C4 stacks, respectively.
6. On a timer interrupt at the end of20 ms, the OS switches the context to C1. As task C5 is
finished, only the contexts C2, C3, and C4 remain at the stack. Task C1 is running as per
its schedule.
When the p-th task has high execution time etp, the worst-case latency of the lowest
priority task can exceed its deadline. To overcome this problem, it is beeter that the OS
definesn a lower time slice for each task. Each task has codes in an indefinite loop. Cyclic
scheduling with time-slocing is simpkle and there is no insertion or deletion into the queue or
list. Figure shows a programming model for cyclic time-sliced Round Robin scheduling.
Figure shows PC on context switches when the schedulker call to tasks at two consecutive
time-slices.
Eadch rask is allotted a maximum time interval = tslice /N, where tslice is the time after
which a timer (with the OS) interrupts and initiates a new cycle.
The OS completed the execution of all ready tasks in one cycle within a time-slice,
Nn x Tslice in this mode. Let tworst be the sum of the maximum times for all the tasks if there
are N tasks in all.then when Tslice. > or = tworst,
The tworst equals:
{ (dti + sti +eti)1 + (dti + sti +eti)2 + … + (dti + sti +eti)n-1 + (dti + sti +eti)n }+ tISR
If N x tslice equals the sum of the maximum times for each rask, then each task is
executed once and finishes in one cycle itself. When a task finishes the execution before the
maximum time it can take, there is a waiting period between two cycles. The worst-case
latency for any task is N x tslice. A task may periodically need execution. The period for the
required repeat execution of a task is an integral multiple of tslice. For each task to run only
once, the N x tslice should also be less that the greatest common factor of all the task periods.
The estimation of response time for each task is easy in tim slice cyclic round robin
scheduling.
Consider a k-th task:
 17

The task response within its task period plus the sum of the maximum times taken
during a time slice from the task 1 to task (k-1). The response time of the m-th task at the end
of the list is the maximum.
An alternative model strategy can be the decomposition of a task that takes an
obnormally long time to be executed. The decomposition is into two or four or more tasks.
Then one set of tasks (or the odd numbered tasks) can run in one tme slice, t’slice and another
set of tasks (or the even numbered tasks) in another time slice t”slice.
Another alternative strategy can be the decomposition of the long time-taking tasks
into a number of sequencial states or a number of node places and trasistions as in the FSM.
Then one of its states or transistion runs in the first cycle, the next state in the second cycle
and so on. Thios task then reduces the response times of the remaining tasks tgar are
executed after a state.

15. (a) Draw and explain basic system (ACVS) of an automatic chocolate vending
machine. (16)
Automatic Chocolate Vending Machine
Requirements
Table 11.1
Specifications
The ACVM specifications in breif are as follows:
1. It has an alphanumeric keypad on the top of the machine, that enables a child to interact
with it when buying achocolate. The owner can also command and interact with the
machine.
2. It has a three-line LCD display unit on the top of the machine. It displays menus,
textenered into the ACVM, pictograms, and welcom, thank you, and other nmessages. It
enables a child as well as the ACVM owner to graphically interact with the machine. It
also displays the time and date.
3. It has a coin-insrtion slot so that the child can insert the coin to buy a chocolate of his/ her
choice.
4. it has a delivery slot so that the child can collect the chocolate, and the coin if refunded.
5. It has an internet connection port so that the owner can know the status of the ACVM
sales from a remote location.
System Specifications in detail are a follows:
1. there is a slot into which a child (buyer) inserts the coin for buying the chocolate.
Suppose the chocolate costs Rs. 8 [Children whish that the chocolates should be so
cheap!] A coin can be in one of the three possible denominations: Re.
List of Six Tasks, Functions and IPCs
Table 11.2
(b) Discuss with a diagram task synchronization model for a specific application.(16)

Let MUCUS RTOS be the choice for an embedded software development for AVCM.
FIGURE 11.7 shows multiple tasks and their synchronization model. It demonstrates how
to draw synchronization diagrams. The figure mentions synchronization objects near the
line connecting a task with another task. The synchronization objects is a semaphores or
mailbox messages for notification. The steps for synchronization are as follows:

1.Task_ReadPorts starts action only when a semaphore SemFlag1 is posted from the
ports. It also accepted the semaphore timeout in case available. Stimeout semaphore is
released by the timer service routine for tick after 30s. It accepts amount messages from
Port_1,Port_2 and Port_5. It posts the message pointers for mailbox waiting for the mail
at Task_Collect.
2. Task_Collect waits for taking SemFlag1 and MboxAmount. It releases SemFlag2 to let
a Task_Deliver provide the choclate.Task_Collect also releases SemFlag2 again which
Task_ExcessRefund takes. This is because the child has already extra. So s/he must get a
chocolat e.
3.Task_Refund waits for taking SemFlag3. It sends message to *MboxStr3.
4.Task_ExcessRefund waits for taking SemFlag2 and posts mailbox message Str4 for
display .Tas_Display waits for taking SemFlag4. It takes mutex, SemMKey2 before
passing the bytes to a stream for Port_Display and releases it after sending. It display the
mailbox messages at the message pointers, *Collect, *delivered, *refund and
*ExcessRefund.
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5.Method DisplaytimeDate() displays at Task_Display gets a timeout notification through

a mailbox message for time and date. The timeout occurs from ISR_timedate after every
1000 ticks of the system clocks. A timeout updates the time and date values at a pointer
*timedate. It posts into the mailbox *timeDate to Task_Display and DisplayTimeDate()
uses it to display in the third line, at the corner of the LCD.