CGAL - A MULTI TECHNOLOGY GATE ARRAY LAYOUT SYSTEM
L. F. Todd, J. M. Hansen, S. V. Pantulu
J. L. Barron, D. J. Gilbert, R. J. Anderson, A. K. Biyani
Computer Aided Design, Roseville, MN
ABSTRACT
This paper describes the Computerized Gate Array Lay-
out system (CGAL), a general purpose tool developed at
Sperry Univac to provide efficient and reliable auto-
mated layouts for a variety of master slice arrays.
The system contains algorithms for the construction of
initial placement, placement improvement c glDbal
routing, channel routing and planar routing. The
system also provides for user interaction through a
design language and graphical output.
A wide range of device types encompassing significantly
different cell topologies and complexity are presently
in production use. Some of the problems encountered
are discussed and results are presented for different
technologies.
INTRODUCTION
The advantages of low cost, fast turnaround devices
referred to as master slices, uncommitted logic
arrays or gate arrays are well known and documented
(TANSl, RAMSO, HIGHSO).
Several gate arrays ranging from in size 360 to 1400
array cells and in cell complexity from 3 to 13 tran-
sistors were being designed at different chip design
centers within Sperry Univac when the CGAL development
was begun. It was apparent that an automated layout
system was required which:
I) Interfaced with the existing CAD systems
2) Could accomodate different chip technologies and
cell topologies (initial designs using CMOS,
Schottky TTL and IOK ECL were in progress)
3) Permitted both high and low volume applications
4) Offered possible extensions to larger applications
5) Provided flexibility in the logic design interface
area to accomodate the varying design practices in
use at Sperry.
The CGAL system was developed to interface cleanly
with the Sperry Univac Computer Aided Design (UCAD)
System, thus assuring access to logic simulation,
test list generation, timing analysis, higher level
logical and physical design tools, hierarchical data
base and documentation aids. Calma and Applicon
systems were already in use for gate array cell design
and custom IC design on a limited basis. These
systems offered a straightforward pattern mask gener-
ation capability and an interactive graphic tool for
manual completion of routes or engineering changes
should they be necessary. CGAL was therefore provided
with an output in CALMA GDSII stream format which
19th Design Automation Conference
Paper 44.3
792
could be translated to Applicon Apple format where
necessary.
General purpose systems with flexibility toward tech-
nology requirements and growth potential have been
reported on throughout the last decade (CHEN77, PER76j
HIGH80). The general approach has consisted first of
a constructive initial placement~ followed by an item-
ative interchange technique typically using net length
as the cost criteria. Some specific consideration to
wire congestion (KH081) may also be done at this point.
A global routing step is next which explores alternate
netting configurations to eliminate local wiring
density problems. The ordering of nets for consider-
ation and the modeling of vertical constraints offer
the opportunity for considerable variation in this
area. Both single pass (TANSl) and multipass
approaches (HIGHS0, CHEN77) are used. An assignment
of net segments to routing channels precedes the
detailed routing stage.
Detailed routing is normally done with a channel
router (HASH71, DEU76) employing a constraint breaking
procedure either prior to or during the routing
process. Again a variety of methods for handling
vertical constraints have been suggested (WAD81,
YOUSl).
Our problem was to put together a system which util-
ized these basic Components to handle a wide variety
of applications. Examination of these applications
indicated that pin accessability, routing constraints
and electrical rule constraints would become major
obstacles. In addition to the basic Components of
placement and routing, an effective language for
describing the design was essential to a general
purpose system. Two areas for design description
existed: I) the physical characteristics of the chip;
2) the logic design of the function(s) to be imple-
mented on the chip. Typically the first of these is
done by a chip designer and defines the character-
istics and design rules common to all utilizations of
the chip. The second consists of the circuits and
their interrelationships along with some application
specific design constraints (e.g.~ clocking rules,
critical paths, preplaced circuits). We found it
useful to define two types of interrelationships to
exist between circuits, one of connectivity~ the
second of hierarchy. Both of these can be constrained
and valued by the logic designer.
DEFINITION AND MODEL
A circuit is an electrical device which performs a
logical function. A cell represents the design
primitive used in CGAL. It consists of a defined set
of electrical components which may be interconnected
to form a circuit. The options available in inter-
connections are termed metal options. Cell complexity
0420-0098/82/0000/0792500.75 © 1982 IEEE
 can vary significantly from chip to chip or within (2) internal partitions used in global and vertical
a chip ranging from a basic logic gate to a collection routing, (3) left external, and (4) right external.
of complex gates. (Figure I) External columns are similar to rows only vertical.

KE__SY Channels partition the chip into local routing areas.

There are two kinds of channels, horizontal and verti-
= locations
cal. A horizontal channel is two adjacent rows and
where vias
are not the region between them. An external vertical channel
~. allowed is two adjacent columns, of which one is external, and
the region between the columns. An internal vertical
El]= tracks channel is an internal vertical column of internal
cell types.
blocked in
Layer 1 KEY

0 = tracks X = pin location

!i ~IIl blocked in * = alternate pin location
Layer 2 O = vias used in the implementation of book from cells

Cell Column 1 Cell Column 2

CACELL i ]
,', ,-, ,-, i t C
R
e
i o 1
i w
TTL CA CELL CMOS CELL
Figure 1
C
R
In a gate array structure, or CGAL chip, the cells are e
prelocated on the chip surface in a regular array. 1 °2
There are three major types of cells: internal, i w
external, and I/O pad. The internal cells comprise
the internal area of the chip and are used for the
majority of the logic design. External cells are I/0
buffers which are primarily used for interfacing with
I/O pads. I/O pads are used for connections that
leave the chip. A model of the chip is shown in
Figure 2.

SgODDDDDDD/° PADS

C Y E ~
Column 1
,, ,~, R

EXTERNAL CELLS O

~PC
D I I I ll"[Ei'c
LLS- O SIA ,,. R
o

D L coL° - O
8-input nand
I-I-S l l l l l l l I L
• ,\
lO Logic Representation (T2L GA)

Figure 3 Figure 4
0., iii iii lilRT _O A book is the specific definition of cell utilization

nhooonooo6° to implement a given logical function. Each logical

circuit h ~ an equivalent book type. A book descrip-
tion indicates the interconnections to be added to a
cell, i.e., which transistors, resistors, etc. to
Figure 2 connect for the circuit function. A book m ~ also
represent a larger circuit which requires more than
Rows are non-overlapping horizontal regions of adja- one cell. The interconnections must be defined for all
cent cells. There are three types of rc~s: (I) inter- intra and inter cell wiring required to construct a
nal cell types, (2) external cell types, and (3) I/O book. Multi-cell books must be rectangular in shape,
pad cell types. no "L" arrangements are allowed.

Columns are non-overlapping vertical regions of cells. Pins are the contact points for interconnections. A
There are four types of columns: (I) columns of cells pin can be ultimately mapped to an input or output of
which define placement cell sites when used with rows, the book and has appropriate electrical characteris-

Paper 44.3
793
 NUMBER OF
NUMBER NUMBER OF TRACKS
TOTAL NUMBE R OF OF TRANS IS- NIJMI',ER AVAILABLE NUMBER
GATE CIlIP NUMBER OF GA'I'ES TOTAL EQU[- BASIC TORS OF FOR ROUTING OF TOTAL
ARRAY SIZE TRACKS IN'rER- VALENT CATE PER BASIC CIIANNELS PER CEL|~ SIGNAL
TYPIC MILS I[ORZ VERT NAL [/C GATES GATES TYPE CELL VERT: IIORZ IIORZ' VERT 'PINS PINS

TTL 235X 578 414 816 204 1020 1020 4 5 28 37 85 115 116 137
(Schottky 235 INPUT
GA) NAND

ECL 236X 656 465 360 60 420 1260 SERIE! 13 20 13 9 15 116 132
240 GATED

CMOS 260X 479 373 1296 80 1376 1376 2 4 2

38 19 19 1.6 8O 84
260 INPUT
NOR

I. Does not include book metal which extends into the horizontal channel or which blocks vertical
tracks running over the cell.
2. Represents average number of feedthroughs available per cell.
3. The number of equivalent gates on the ECL and TTL chips can be increased through
emitter/collector dotting of outputs.

Tab le I

tics associated with it. (e.g,, capacitance, drive
capability, gate delay). A net is a set of pins to be
physically interconnected.
A macro is a high level design representation of a
group of logic circuits. It allows the logic designer
to take a hierarchical approach to his design. A
macro is physically realized as a set of books placed
and interconnected by the software. A common example
is a latch made up of 4 input hand gates. The user
can constrain a macro by specifying the half perimeter
of a rectangle enclosing its placed books.
pads themselves can be accessed only on second layer
when used to drive off chip and in a completely
different routing channel when used to drive gates on
the chip. All of this activity on the chip periphery
when coupled with constrained pin access due to power
bussing combines to creat~ significant routing
problems. Both of the b i-polar devices have single
layer routing areas on the chip periphery as a result
of the fixed power bus routing.

CHIP DESCRIPTIONS AND DESIGN CONSIDERATIONS

The CGAL system is currently used to layout gate arrays

of three different technologies--CMOS, ECL and TTL.
These LSI chips are being used to perform a variety
of functions in all phases of computer systems;
control, memory, central processing, I/O controllers,
arithmetic logic units etc. The three gate array
designs vary significantly in cell topology, pin
accessability, routing area, cell complexity and I/O
design. All three designs use two metal levels for
signal routing interconnections. Power and ground
busses run in one or both of these layers. Multi-
cell books using routing channel space for the custom-
ization interconnects are not unusual. Large multi-
cell books (up to 12 cells in some cases) exist with
cells found both in single and multiple row/column
configurations--Figures 3 & 4. Table I summarizes
some of the layout related aspects of the three gate
array designs. The books shown in Figures 3-5 reveal
some of the problems in pin accessability, tracks/cell
available for routing and book size which affect
placement and routing. The ability to manipulate
books of different sizes and to bias the layout in
favor of horizontal or vertical net components is
essential to effective placement of these devices.
The design of the I/O buffers varies radically from a
conventionally simple one buffer per I/O pad arrange-
ment in the CMOS chip to a complex configuration on
the TTL chip with 204 I/O buffers for 116 signal pins.
The TTL chip contains input buffers, output buffers
and tri state buffers which offer a functional capa-
bility equal to the internal gate and can be used as
an internal gate when needed. In addition, the I/O
Scan/Settable J-K Flip-Flop
(CMOS CA)
Figure 5
The most significant topological problem presented in
the internal array routing was the variation in pin
access between chip designs. Stacked pins create
situations where access to a pin from both the channel
above and the channel below is constrained. Another
related consequence is connections which are contained
within the cell area. Power busses and via constraints
create situations where a pin may be accessed only on
one layer. Book interconnection metal in the route
channel can create not only a local wiring density
problem but severe pin access problems.
At present specific techniques to handle all the
problems presented by these constraints in an optimal
fashion have not been implemented. Instead emphasis
has been on the ability to solve most of the problems
without becoming technology or project specific. The
system opportunities for manual intervention are used
to circumvent shortcomings.

Paper 44.3
794
 Once in the CALMA system, graphical editing can be
exercised and a pattern mask type can be written.
However, prior to the creation of a pattern tape a
checking program, LSICHECKS, is run. This program
verifies that the original design input as represented
in the logic equation file is accurately reflected in
the CALMA Data Base. Also checked are design rules to
insure no errors have been introduced during the
layout/routing/editing process. A final output of the
checking program is updates to the logic equation file
containing chip pins and net metal by layer. This
data is used by P.C. layout, timing analysis, and test
list generation programs.

OPERATIONAL MODULES

The CGAL system was developed as a set of independent

modules running off a common data base under an
environment controlled by a common supervisor. The
six modules are defined in this section.

Control Module

The center of the CGAL system is the Control (Super-

visor) Module whose responsibility is the initiali-
zation and control of the system environment. All
system requests are processed by the control module
via specific commands contained within a command
stack. The controller accomplishes these tasks by a
set of independent service routines contained within
Figure 6 the system. These are:

SYSTEM FLOW • Analysis of syntax and semantics of command/

parameter requests
Figure 6 depicts the general flow of information into • Assignment and maintenance of user files
and out of the CGAL system. Primary input data • Dynamic assignment and control of various submodule
sources are the LIBRARY FILE and the DESIGN FILE. files
The LIBRARY FILE contains descriptions of the cells, • Read/Write of user and program assigned files
the books, The routing grid, the I/O bonding pads, the • Building, processing and control of the command
placement restrictions, book to cell mapping, routing stack
restrictions, electrical rules, and book performance • Message handling and processing
data. The DESIGN FILE describes the logic design in • Error recovery procedures
the form of circuits, nets and macros. It allows nets
The command, parameter and message processing are
to be typed and weighted, correlating them to specific
the most interesting of these features.
sets of electrical rules in the LIBRARY FILE. The
DEEIGN FILE is normally derived through a conversion
CGAL contains a global command stack that is used as
program from the UCAD LOGIC EQUATION FILE which links
both a queue and as a stack. Initial entry commands
CGAL to the full complement of Sperry Univac CAD tools.
(via user parameters) are entered into the system as
Because of the relatively static condition of the
a queue (first in-first out) while system modules
LIBRARY FILE, it is advantageous to provide a stand
may request command entries (during processing)
alone compiler for this section of the input data
which are handled as a stack (last in-first out).
base. The compiler creates a compact quickly read
This flexibility of the command stack allows other
file where the majority of the syntax checking,
modules to add commands onto the stack causing alter-
linking and sorting processes have already been accom-
nate events to be scheduled as a function of the
plished.
action taken by the original module. The commands
within the command stack initiate all modules with-
Two other input sources are the user requests and the
in the system (i.e., Data Base Build, Placement,
Route Segment File. The user requests a CGAL function
Reports) via a numeric sequence that defines the
or functions to be performed through a command and
specific module to be called. The coumland language
parameter language. The Route Segment File provides
permits macro level commands which automatically load
an intermediate data store for routing results which
a series of micro module commands as chained events.
can be edited by the user. Both the Route Segment
File and the DESIGN FILE are used to retain inter-
Messages in CGAL are controlled such that at the end
mediate layout and routing results which can be easily
of each functional module the message processor will
edited through a text editor.
process all messages queued for output. The results
The user can cycle through the CGAL system using of this approach are that all messages appear
graphical output and printed reports to verify input, together for each module (rather than being scattered
throughout the listing) and that message formats are
analyze results, and determine manual intervention
controlled by one routine throughout the production
strategies. Multiple versions of intermediate place-
system.
ment and routing results can be saved and manually
modified. When a 100% routed chip has been obtained
with no electrical rules violations the user requests Data Base Module
that CGAL write a Calma compatible output file.
The data base module consists of a set of routines
which build the data base, handle access interfaces

Paper 44.3
795
and maintain checking services, as well as providing
an off line compiler. The data base refers to a
collection of all project information pertaining to
the definition of the project hardware design. Thus
while each design has its own independent data base,
portions of it are shared with other designs.
Throughout the CGAL system the common data base is
maintained via mass storage devices. The co~muon data
base structure has been an essential link to provi-
ding a flexible environment for the development of
both algorithmic and user interface modules within
the CGAL system.
The data base itself consists of tables (defined
global to the system) which are maintained and
controlled via load and store service routines.
These routines will upon request from a specific
module, load and/or restore selected tables in a
designated area.
The data base allows the user to retain numerous
Design and Route Segment files within the system as
separate elements of the same logic name but different
version names. This allows the user to attempt several
experimental layouts then select the preferred layout.
Because the Design and Route Segment files exist with-
in the UNIVAC ~ II00 as symbolic elements they can
be easily modified using the standard Ii00 System Edit
processors. The user has the flexibility to shape the
output of his design by weighting nets, manually
placing circuits, pre-assigning pins, applying differ-
ent wiring rules to nets, pre-grouping circuits for
clustering and adding discretes. Similarly the Route
Segment File tan be modified to complete or change a
connection path. The CGAL system creates updated
versions of these files upon user request.
The source languages used in CGAL for the Design,
Route Segment and Library files use a common format.
Each file consists of sections which consist of a set
of statements. These statements describe the data by
means of fields, sub-fields and segments of sub-fields.
The language allows for repeatable, as well as multi-
ple expressions of the statement elements. The co,~mon
language has proven to be very effective for user
training.
Placement Module
As in (PAT71) the placement module consists of four
major activities: (i) Partitioning (2) Cluster
Placement (3) Decomposition (4) Placement Improve-
ment.
To satisfy the twin criteria of wireability and net
length, each of these activities is divided into two
phases. In the first phase, an initial constructive
solution is obtained based on the objective of minimum
length. In the second phase an iterative loop is
entered during which an effort is made to achieve a
more uniform wiring distribution. During parti-
tioning, an initial constructive solution is obtained
using the cluster development method (HAN72). The
technique is augmented by the use of macros as pre-
partitioned cluster seeds. This portion of parti-
tioning is skipped when the input data contains
complete partitions provided by the logic designer.
In the iterative loop, wireability is attacked indi-
rectly by attempting to achieve balanced cluster
sizes; removing circuits from oversized clusters and
reassigning them with a linear assignment technique
until all the clusters are roughly equal in size.
Circuits which are members of constrained macros are
not candidates for reassignment. Separate linear
assignments of internal gates to clusters and to I/O
buffers insures a uniform distribution of internal
Paper 44.3
796
gates as well as external signals. The linear
reassignment of I/O buffers was found to be parti-
cularly useful for logic designs using a low percentage
of the I/O pads provided on the gate array.
Cluster placement begins by initially locating the
clusters on the gate array by a process similar to
the pair linking approach (HAN72). Analysis of
wiring density at evenly spaced vertical and hori-
zontal cut lines is done and using an iterative
procedure (BREU77) an attempt is made to reduce the
congestion at the most dense areas.
Decomposition first performs an initial mapping of
books to cells. Then the min-cut procedure is used
on the clusters to distribute the wiring within
cluster boundaries.
The placement improvement phase is based on a Force
Directed Interchange procedure. Each swap is eval-
uated on the basis of a composite function which
considers the effect on wiring length, the electri-
cal rules, and critical net identifications. To
reduce run time, this procedure uses several netting
methods with more precise schemes being used in the
later passes. Periodic reassignment of I/O signals
to pads is done to reflect the changes in the place-
ment of the I/O buffers. The process terminates with
a pass in which all the pins on the internal gates
are reassigned to reduce wire crossovers in routing.
User parameters to bias nets on the basis of number
of iterations and the size of target neighborhoods
are available to handle different designs and tech-
nologies.
Routin~ Module
The Router consists of submodules which perform
global routing, vertical track assignment, horizontal
track routing, clean up and maze routing. A router
environment provides a data base for all information
used by the various routing tasks. This router
environment, consisting of netting descriptions
required for each task and physical blockage lists
accessible by rectangular area provides a common set
of routines for determining where routing is permitted
and recording routes once made.
Global Routin~. Global routing is initiated by
dividing the chip into a matrix of global cells which
correspond to the grid formed by the rows and columms.
The cell area defines the location of a set of global
points while the cell edges represent a set of routing
paths. There fore each cell edge is assigned a value
representing the routing supply. This model closely
resembles the model described in (CHEN77). The edge
supply can be discounted by user parameter to allow
for more accurate modelling of cell routing density.
The supply across horizontal edges is generally set to
100% of the actual supply, however it is set at B0%-
90% of the actual supply across vertical edges. This
is to compensate for intra cell connections and
horizontal jogs introduced in vertical track assign-
ment. The global routing will determine the inter-
connection path for all global cell to cell routes,
ignoring all internal cell connections. Each signal
set is netted in the form of a Steiner tree (HAN66),
ignoring cell e~ge supplies. The cell edge crossings
are now examined for overflows where demand exceeds
supply. For each edge containing an overflow~ the
transfer of net segments to other edges will occur.
This is done one net at a time, by scoring and order-
ing the nets according to the number of overflows per
net, length and a measure of net criticalness. The
net is reconstructed to reduce overflows by moving net
segments. This process continues until no overflows
exist or no improvements can be made. The new global
points created during netting are translated into
channel points with channel locations, and the net
segments are assigned to channels according to the
global routing. This creates a set of channels with a
set of points to connect permitting subsequent routing
to be done a channel at a time.
Results after global routing can be used to evaluate
and predict the routability of the design without
further processing. In cases where multiple place-
ments have been created the global router is an
effective tool for selecting which one should be
routed to completion.
Vertical Track Assignment. This phase of routing
defines the X coordinate entry points into the hori-
zontal channels for wire segments within a vertical
channel. This includes both pin nodes and vertical
segments passing through a horizontal channel. The
basic approach follows the process used in (CHEN77).
A cost matrix is created with each vertical segment
and node assigned a cost for assignment to each
vertical track in the channel. Munkres (HAN72) linear
assignment method is then applied.
Costs are based on assuring pin access to the hori-
zontal channel, minimizing the introduction of new
horizontal segments and the length of existing ones.
Special problems were encountered in dealing with
stacked pin situations where two or more pins share
an X coordinate. The use of alternate pins is modeled
into the cost function, however, in some cell pin
configurations it is necessary that two signals be
assigned the same X coordinate with access on differ-
ent layers. In addition there are occasions where
vertical connections can be made totally within the
cell area. The accessability of a pin is considered
in the cost function to permit pins on the cell edge
to be left for assignment by an overflow processor
in stacked pin conflicts. Assignment proceeds on a
row by row basis through a vertical channel beginning
at either the bottom or top of the channel.
Horizontal Track Router. The horizontal track router
determines the detailed assignment of nets to tracks
in the horizontal and external vertical channels.
The line-packing scheme used is the Dogleg Routing
technique (DEU76). An e f f o r t i s made t o r e d u c e
constraints so that the routing can be completed near
channel density. A short vertical segment is intro-
d u c e d at non-critical density positions to break
cyclic and chain constraints. Segments requiring
first layer access are given priority for "the tracks
nearest the channel edges.
Maze Router. The maze router is used to complete
wires left following the track routers. The primary
set of wires left are those on the chip periphery in
areas where only one layer of metal is available for
routing. However, wires are also routed by the maze
router in areas of poor pin access and unresolved
constraints in the internal array. The maze routing
technique is an implementation of a directed wave
front router (SOU78) with multiple start and destin-
ations allowed. Two passes are made with a larger
routing window and relaxed orthogonality constraints
on the second pass.
Cleanup Routin~. The cleanup routine removes unnec-
essary vias by moving a portion of a route to another
layer. This is done following track routing.
Following maze routing the cleanup routine is again
invoked to remove extra vias and metal made unnec-
essary by the maze router.
Report Module
In addition to the output generated by the various
modules of CGAL, the user is provided with hard copy
reports of the layout results at various stages of
the design implementation. Two types of printer
reports are generated; summary reports which convey
chip profile information and violation reports which
identify design rule violations and provide data for
dealing with them.
The report module runs off the consnon data base and
has the f o l l ~ i n g attributes.
I) can be individually requested by user.
2) can be easily modified or added to according to
the users needs.
3) provides the pertinent information in a self-
sufficient form eliminating the need to refer to
other documents.
When dealing with multiple projects and technologies
the support problems can be quite extensive especially
in the area of project specific rules and constraints.
Our ability to generate effective reports on short
notice has enabled the user to maintain production
schedules through the manual intervention opportu-
nities in the CGAL system. It has also kept ill
advised project specific algorithmic modifications
to a minimum.
Summary reports include routing sunn~ary~ cell utili-
zation, pin usage, net length analysis, placement
maps, and circuit types used. Examples of error
reports include an analysis of voltage drop involving
determination of current flow in all net branches.
Also available are reports on net delay violations
and for the ~ technology, latch macro delay viola-
tions. Values which define a violation are contained
in the CGAL library file as part of the design rules
or electrical characteristics of the book.
CGAL also provides output reports in the form of
precision color graphics plots. A Xyneties Large
Area Flatbed plotter is used to verify the CGAL
library input data. For manual route completion, a
route master is generated along with a plot of all
routing and connections still to be made. This can
be marked up, then used to enter the data into the
Route Segment file.
A final output reporting form is to a color graphics
terminal. A Chromatics terminal is presently being
used and the output available is essentially the same
as is available on the Xynetics. An interactive
relationship is planned for future extensions.
Output Module
This module is responsible for transferring the
results of layout and routing to the Calma system for
merges with common data and pattern mask generation.
The Calma Graphic System contains the bulk of the
information required to describe the mask generation
data for a specific chip. The graphical data base
output (CGAL's contribution to the pattern generation)
is a description of the layout and routing results in
a format (GDSII Stream format) which can be read by
the CALMA Graphics System.
CGAL System output to CALMA consists of four major
sections. The first section establishes the CALMA
environment (providing a CALMA library name, CALMA
reference library names, CALMA "FONT" reference
Paper 44.3
797
library names, and the CALMA units descriptions).
The second section establishes the selection, place-
ment, and orientation of all the CALMA cell reference
names (the cells have previously been established
within the CALMA data base and contain all pertinent
information regarding the cell such as metal
descriptors, layers, pin numbers, etc.). The third
section contains the placement and data for textual
information (each unique circuit name described
within the particular design/layout). The fourth
section contains the actual routing descriptors and
"VIA's" as established within the Routed Segment file
(contains layer, datatype, pathtype, metal width, and
coordinates for each segment as well as "via" CALMA
library references and locations).
connections of book metal. These factors dis-
courage speculation about the CMOS performance
until more parts are run.
c. Manuel route completion is typically done through
the CGAL system files and requires ½ day to
manually route and ½ day to enter and check the
results with the program.
d. The TTL #2 part differs from the TTL #I part in
that the upper ~ of the chip area is devoted to
a special bus interface circuit. This is modelled
as a set of preplaced 'super' hooks in the CGAL
files and no special software is required to
handle it.

DISCUSSION Figures 7 & 8 depict routed TTL and ECL arrays.

The CGAL system is presently in production use. A CGAL has several areas where performance improve-
staff of design automation technicians run the pro- ments have been identified. From the user view-
grams and interact with the logic designers in a point, an expansion of the Chromatie~ interface to
production environment. A two week turnaround is the include interactive processing would make the
present average time from logic design input to system more independent of the CALMAwithout a loss
pattern tape. An initial capability of three chips in graphical capability. The algorithm being used
per week was experienced, subsequently it improved in the placement of the I/0 buffers is being
to better than one per day as project interfaces and reevaluated in light of the TTL routing results.
system familiarity improved. Training on the system The more severe stacked pin situations on the ECL
progressed smoothly and once a technology is estab- chip still result in some internal array routing
lished, new users of the system, whether technicians failures. The maze router has proven to be a good
or logic designers, have been able to obtain good final routing tool for both internal array failures
layouts in just a few weeks. The manual effort and periphery problems, but a better ordering is
involves dealing with unrouted connections, timing needed in conjunction with an I/0 PAD swapping to
constraints and physical constraints. Depending on produce optimal results.
the severity of the problem the user reaction can
Although 100% routing has not been regularly achieved,
range from weighting error nets and rerunning all or
the application of a collection of fairly standard
portions of placement to manually inserting extra
techniques in CGAL to different gate array technol~
metal on a net to balance clock skew or lower IR drop.
ogies has been a success. The CGAL system tools have
enabled users to handle problems in a cost effective,
TECHNOLOGY TTL #I TTL #2 CMOS ECL semi-automated mode. CGAL was designed using a
modular, structured approach to software development.
TOTAL NETS 761 588 480 483 This design with its common data base and independent
INTERNAL CELLS 816 600 1296 360 modules has allowed modifications and enhancements
USED CELLS 800 534 1239 347 to occur in a stable environment. The problem areas
I/O PADS i16 112 80 116 previously noted and those which will arise in future
I/O PADS USED 112 106 80 i01 gate array technologies can be handled by this system
TOTAL SEGMENTS 1872 1379 1119 1353 using the manual tools to permit production to con-
ROUTED SEGMENTS 1864 1368 1098 1347 tinue ~ i l e automated techniques are developed.
PERCENT ROUTED 99.57 99.2 98.12 99.55
CONCLUSION
Tab le II
A system for gate array layout has been presented
Results on four chips, each a different type, are which is in use on several different technologies.
displayed in TABLE II. These represent fairly dense The technologies offer diverse approaches to cell
chips ranging from 89% to 98% cell occupancy. topology, cell complexity, pin accessability, I/O
Segments are used to measure route completion connec- buffer procedures and routing constraints. The
tion and are defined system languages-pe~nit descriptions of constraints
unique to the different design uses and technologies.
n The system performance is adequate with routing
S = Z (Pi-l) failures occurring primarily in the chip periphery
i=l and tools for manual completion sufficient for meeting
production needs.
where S is the number of segments, n is the number of
nets and P. is the number of pins in net i. ACKNOWLEDGEMENTS
l
Several points should be noted about the results. The design and the development of the CGAL system
owes thanks to many individuals and organizations.
a. I/O buffer pin access and planar routing failures Terry Arntzen, Shubhada Nerurkar and John Dellwo all
on the two TTL and t h e ECL chips account for 50 contributed to software development and installation.
to 100% of the unroutes. The Research and Technical Planning, General Systems
Division CAD and Defense Systems Division CAD groups
b. Only one design is using the CMOS technology at
all contributed to the ultimate product. Jean Moen
this time. The logic design was unusual in that
typed and assembled the paper.
over 75% of the chip area was occupied by j-k
flip flop books similar to that in Figure 5.
These large books combined a low pin/cell density
with a large number of pre-routed in-channel

Paper 44.3
798
The authors would like to extend a special acknow- HASH71 A Haslmoto and J. Stevens, "Wire Routing by
ledgment of Mike Pluimer and Dr. Ash Patel for their Optimizing Channel Assignment within Large
efforts in the original design and subsequent consul- Apertures," Proc Sth Design Automation
tation on the detail design of the system. Workshop, pp. 155-169, 1971

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Paper 44.3
799
 ECL GA

Figure 7

Paper 44.3
800
 TTL GA

Figure 8

Paper 44.3
801