2108 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO.

6, JUNE 2009

Novel Family of PWM Soft-Single-Switched

DC–DC Converters With Coupled Inductors
Mohammad Reza Amini, Student Member, IEEE, and Hosein Farzanehfard, Member, IEEE

Abstract—In this paper, a novel family of pulsewidth-

modulation soft-single-switched dc–dc converters without high
voltage and current stresses is described. These converters do not
require any extra switch to achieve soft switching, which consider-
ably simplifies the control circuit. In all converter family members,
the switch is turned on under zero-current condition and is turned
off at almost zero-voltage condition. From the proposed converter
family, the boost topology is analyzed, and its operating modes are
explained. The presented experimental results of a prototype boost
converter confirm the theoretical analysis. Fig. 1. Proposed PWM SSS boost converter.
Index Terms—Pulsewidth modulation (PWM), soft-single
switched (SSS), zero-current switching (ZCS), zero-voltage converter, a soft-switching condition is not achieved for the
switching (ZVS). switch turnoff instant. Furthermore, in [16], an additional diode
is added in the main power path, which would further increase
I. I NTRODUCTION the converter conduction losses.
In this paper, a family of PWM SSS converters without any
I N ORDER to reduce the size and weight of switching
converters and increase power density, a high switching
frequency is required. However, in hard-switching converters,
substantial increase in voltage and current stresses is presented.
Furthermore, in this converter family, the number of additional
components is not high. The switch in all proposed converters
as the switching frequency increases, switching losses and
is turned on under zero-current-switching (ZCS) condition and
electromagnetic interference increase. To solve this problem,
is turned off at almost zero-voltage-switching (ZVS) condition.
soft-switching converters are indispensable.
The converter main diode turns on under ZVS condition and
In recent years, great amount of research is done to de-
turns off under zero-voltage zero-current switching (ZVZCS)
velop soft-switching techniques in dc–dc converters. In these
conditions. Furthermore, an auxiliary diode turns on under ZVS
converters, it is desirable to control the output voltage by
condition and turns off under ZCS condition. The proposed
pulsewidth modulation (PWM) because of its simplicity and
method can be easily applied to single-switch converters such
constant frequency. A low number of components, particularly
as buck, boost, buck–boost, Cuk, SEPIC, and Zeta. Further-
active components, is also desirable. Quasi-resonant converters
more, it can be applied to isolated single-switch converters
do not have any extra switch to provide soft-switching con-
such as forward, flyback, isolated Cuk, isolated SEPIC, and
ditions; however, they must be controlled by the variation of
isolated Zeta.
switching frequency [1]. Furthermore, zero-voltage transition,
In this paper, from the proposed PWM SSS converters,
zero-current transition, and active clamped converters are PWM
the boost converter is analyzed, and its operating modes are
controlled but require at least two switches, which increases the
described in Section II. General design considerations and
complexity of power and control circuits [2]–[9].
experimental results from a 120-W 100-kHz prototype boost
PWM soft-single-switched (SSS) converters [10]–[14] and
converter are presented in Sections III and IV, respectively. The
lossless passive snubbers [15], [16] enjoy all the mentioned
topology variation of the proposed converter is illustrated in
advantages, usually at the cost of additional current and voltage
Section V.
stresses. However, they usually have a large number of passive
elements, which makes the converter implementation difficult
II. C IRCUIT D ESCRIPTION AND O PERATION
[10]–[14], [16]. The lossless passive snubber circuit introduced
in [15] is simple and easy to implement. However, in this The circuit configuration of the proposed boost converter is
shown in Fig. 1. The circuit components including Lr1 , Lr2 ,
Manuscript received August 5, 2008; revised November 18, 2008 and
January 4, 2009. First published March 16, 2009; current version published D1 , and Cr are added to the conventional boost converter. It is
June 3, 2009. assumed that Lf and Cf are large enough so that they can be
M. R. Amini is with the Department of Electrical and Computer Engi- replaced by a current source (Iin ) and a voltage source (Vo ),
neering, Isfahan University of Technology, Isfahan 84156-83111, Iran (e-mail:
mrezaaminy@ec.iut.ac.ir). respectively.
H. Farzanehfard is with the Department of Electrical and Computer Engi- To further simplify the converter analysis, it is assumed
neering and the Information and Communication Technology Institute, Isfahan that all circuit components are ideal. The nonideal effects of
University of Technology, Isfahan 84156-83111, Iran (e-mail: hosein@cc.
iut.ac.ir). circuit components, particularly the leakage inductance of the
Digital Object Identifier 10.1109/TIE.2009.2016509 coupled inductors, are discussed in Section IV. It is assumed

0278-0046/$25.00 © 2009 IEEE

AMINI AND FARZANEHFARD: NOVEL FAMILY OF PWM SSS DC–DC CONVERTERS WITH COUPLED INDUCTORS 2109

Fig. 2. Equivalent modes of the proposed boost converter.

that the turn ratio of coupled inductors is N2 /N1 = n. Thus,

Lr2 = n2 Lr1 .
The proposed converter has six distinct operating modes in
a switching cycle, as shown in Fig. 2. The main theoretical
waveforms are shown in Fig. 3.
Mode 1 [t0 −t1 ]: Before the first mode, it is assumed that the
main switch is off and Iin flows through the main diode Do , and
thus, the Cr voltage is equal to Vo . At t0 , the switch is turned on
under ZCS condition due to series inductor Lr1 . The inductor
current is
Vo
ILr1 (t) = (t − t0 ). (1)
Lr1
At t1 , ILr1 reaches Iin ; therefore, the duration of this
mode is
Lr1 Iin
Δt1 = t1 − t0 = . (2)
Vo
Mode 2 [t1 −t2 ]: At t1 , the Lr1 current has reached Iin , and
the diode Do current has reached zero. Thus, the diode Do
turnoff is under ZCS. In addition, due to the existence of Cr
and based on (3), the Do voltage rises slowly and is con-
sidered ZVS.
Consequently, the Do turnoff is ZVZCS. In this mode, Lr1
starts to resonate with Cr . The resonant capacitor voltage and
resonant inductor current are
Fig. 3. Key waveforms of the proposed converter.
Vcr (t) = Vo cos (ωr (t − t1 )) (3)
This mode ends when the Cr voltage reaches zero. Thus, the
Vo
ILr1 (t) = Iin + sin (ωr (t − t1 )) (4) duration of this mode is
Zr
π
where Δt2 = t2 − t1 = . (6)
2ωr

1 Lr1 Mode 3 [t2 −t3 ]: When Vcr reaches zero, diode D1 starts to
ωr = 2πfr = √ Zr = . (5)
Lr1 Cr Cr conduct under ZVS condition, and the Cr voltage is clamped
2110 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 6, JUNE 2009

at zero. Since the total ampere turns of Lr1 and Lr2 should stay At t4 , Vcr reaches Vo ; thus, the duration of this mode and the
constant maximum voltage stress of the switch are
   
Vo n Vo
Iin + N1 = ILr1 N1 + ILr2 N2 . (7) Δt4 = t4 − t3 = sin−1
Zr ωr Vo + (n + 1)Zr Iin
(16)

 
Furthermore, the Lr1 current is equal to the sum of the input 1
current and the Lr2 current; thus, the following relations are Vsw,max = Vsw (t4 ) = 1 + Vo . (17)
n
derived:

Vo Mode 5 [t4 −t5 ]: This mode begins when the Cr voltage

ILr1 = Iin + (8) reaches Vo and the diode Do turns on under ZVS condition.
(n + 1)Zr
At the beginning of this mode, the Lr2 current is
Vo
ILr2 = . (9)  2
(n + 1)Zr
n+1 2 + 2(n + 1)Vo
I2 = Iin Iin − Iin . (18)
The interval of this mode and the previous mode is effectively n n2 Zr
the converter duty cycle. This mode ends when the switch is
turned off. The duration of this mode is In this mode, the Lr2 current decreases linearly. Thus, the
Lr2 current equation during this mode is
Δt3 = DTs − (Δt1 + Δt2 ) (10)
Vo
ILr2 (t) = I2 − (t − t4 ). (19)
where D is the switch duty cycle and Ts is the switching period. Lr2
Mode 4 [t3 −t4 ]: By turning the switch off, the ampere turn
of Lr1 is transferred to Lr2 , and now, the Lr2 ampere turn is At t5 , the Lr2 current reaches zero, and the diode D1 turns
the sum of its previous ampere turn plus the Lr1 ampere turn as off under ZCS condition; thus,
described by
Lr2 I2
Δt5 = t5 − t4 = . (20)
ILr1 N1 + ILr2 N2 = I1 N2 (11) Vo

where ILr1 and ILr2 are the values of the coupled inductor Mode 6 [t5 −t6 ]: In this mode, Iin freewheels through the
currents in the previous mode and I1 is the Lr2 current at t3 . diode Do , and the current through the resonant inductors re-
Thus, by substituting (8) and (9) in (11), the following is mains zero and the voltage across the resonant capacitor stays
obtained: at Vo . The duration of this mode is
 
1 Vo
I1 = ILr2 (t3 ) = Iin + . (12) Δt6 = (1 − D)Ts − (Δt4 + Δt5 ). (21)
n Zr

The resonant capacitor charges by Iin plus the Lr2 current The converter operations in continuous conduction mode
until its voltage reaches Vo . The switch voltage, Cr voltage, (CCM) and discontinuous conduction mode (DCM) are similar.
and Lr2 current during this mode are However, CCM is preferred since the energy stored in the
leakage inductance of the coupled inductors in this condition
  is less than that in DCM.
1
Vsw (t) = (n + 1)Zr (Iin + I1 ) sin ωr (t − t3 ) (13)
n
 
1 III. D ESIGN C ONSIDERATIONS
Vcr (t) = nZr (Iin + I1 ) sin ωr (t − t3 ) (14)
n The design of the proposed circuit involves the selection of
  Cr , Lr1 , and n. Cr provides the ZVS condition for the switch
1
ILr2 (t) = (Iin + I1 ) cos ωr (t − t3 ) − Iin . (15) turnoff instant. Therefore, its value can be selected similar to
n
any snubber capacitor as follows [17]:
It can be observed from (13) that the switch is turned off under
ZVS condition at the beginning of this mode. However, in Isw tf
Cr > Cr,min = (22)
practice, due to the small leakage inductance of the coupled 2Vsw
inductors, a small voltage spike appears across the switch, and
then, the switch voltage rises slowly to its final value. Thus, where tf is the switch current fall time, Isw is the switch current
actually, the switch is turned off under almost ZVS condition before turnoff, and Vsw is the switch voltage after turnoff. In
even though the spike peak is usually much smaller than the practice, Cr is considered much larger than Cr,min to guarantee
switch maximum voltage. soft switching.
AMINI AND FARZANEHFARD: NOVEL FAMILY OF PWM SSS DC–DC CONVERTERS WITH COUPLED INDUCTORS
Fig. 4. (1 − Dmax )f0 versus Iin (normalized to Vo /Zr ) for various n’s.
Lr1 provides ZCS condition for the switch turnon instant.
This inductor can be selected according to [17], as follows:
Vsw tr
Lr1 > Lr,min = (23)
Isw
where tr is the switch current rise time. In practice, Lr1 is
considered much larger than Lr,min to guarantee soft switching.
It can be observed from (17) and (8), that, as n increases,
the switch voltage stress (in the fourth mode) and freewheeling
current (in the third mode) decrease. However, this will result
in a higher voltage stress of diode D1 and limits the maximum
duty cycle of the converter. From (16) and (20), the following
relation is obtained, which provides the maximum allowable
duty cycle that soft-switching condition is provided for full load
range:
 
n −1 1 The experimental results of the prototype converter are
(1 − Dmax )f0 = sin
2π 1 + (n + 1)iin
 converter switch is turned on under ZCS condition and turned
iin 2(n + 1) n off at almost ZVS condition. The current ringing during the
+ (n + 1)2 + − iin (24)
2π iin 2π
where iin = Iin (Zr /Vo ), f0 = (fr /fs ), and fs is the switching
frequency.
Based on (24), for various values of n, (1 − Dmax )f0 versus
the normalized Iin is shown in Fig. 4. Since it is generally
desired to have a large value for n, from Fig. 4, the largest value
for n can be selected according to the output current range and
maximum duty cycle.
Note that, at small values of load current, soft switching is
not as significant as for full load current. Thus, soft-switching
condition at very light load current can be omitted, and a larger
value for n can be selected.
The additional current and voltage stresses of a switch can
be reduced to a small amount, by choosing large values of
Zr and n. However, large values of Zr and n limit the converter
maximum duty cycle and soft-switching range which can be
obtained from Fig. 4.
2111
TABLE I
COMPARISON OF SSS CONVERTERS
IV. S IMULATION AND E XPERIMENTAL R ESULTS
A prototype of the proposed boost PWM SSS converter is
implemented at 50-V input voltage and 100-V output voltage.
The converter operates at 100 kHz and an output power of
120 W.
According to the discussions in the previous section, the
designed values for Lr1 , Cr , and n are 18 μH, 10 nF,
and 3, respectively. Furthermore, the Lf and Cf values are
180 μH and 100 μF, respectively. IRF840 is selected for
the converter switch, and MUR460 is chosen for diodes Do
and D1 .
A comparison of two other SSS converters with the proposed
converter is illustrated in Table I. The simulation is performed
by PSpice using the same circuit values as aforementioned for
the experimental setup. The results show that the converter of
[11] has higher efficiency and lower switch stresses, but it has
two more diodes than the proposed converter, and it cannot
be extended to isolated converters. The proposed converter is
generally better than the converter of [12], except for the switch
voltage stress. It should be noted that the proposed converter
switch voltage stress can be reduced by increasing n, when soft
switching at light loads is not important.
shown in Figs. 5–7. It can be observed from Fig. 5 that the
turnoff switching instant, as shown in Fig. 5(c), is basically
due to the resonance between the leakage inductance of coupled
inductors and the switch junction capacitor.
Fig. 6 shows that the main diode Do turns on under ZVS
condition and turns off under ZVZCS condition. Since parasitic
inductances are not considered in ideal waveforms, at t4 (begin-
ning of mode 5), the current through Do can jump from zero to
I2 + Iin and then would decrease linearly to Iin . However, in
practice, there are stray inductances in series with Do , which
create a resonance with Cr . Thus, the current through Do rises
rapidly in a resonance fashion and creates an overshoot as
shown in Fig. 6(a). The undershoot voltage across the diode
confirms the nature of this resonance. After this resonance, as it
can be observed from Fig. 6(a), the current through Do linearly
decreases similar to the theoretical analysis.
Fig. 7 shows that diode D1 turns on under ZVS condition
and turns off under ZCS condition. The efficiency curve of a
prototype converter is shown in Fig. 8.
2112 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 6, JUNE 2009

Fig. 5. Measured (top) voltage and (bottom) current of (a) the switch at one switching cycle (voltage: 50 V/div; current: 2 A/div; time scale: 1 µs/div),
(b) the switch turnon instant (voltage: 50 V/div; current: 2 A/div; time scale: 250 ns/div), and (c) the switch turnoff instant (voltage: 50 V/div; current: 2 A/div;
time scale: 250 ns/div).

Fig. 6. Measured (top) voltage and (bottom) current of (a) the main diode Do at one switching cycle (voltage: 50 V/div; current: 2 A/div; time scale: 1 µs/div),
(b) the main diode Do turnon instant (voltage: 50 V/div; current: 2 A/div; time scale: 250ns/div), and (c) the main diode Do turnoff instant (voltage: 50 V/div;
current: 2 A/div; time scale: 250 ns/div).

Fig. 7. Measured (top) voltage and (bottom) current of (a) the diode D1 at one switching cycle (voltage: 200 V/div; current: 1 A/div; time scale: 1 µs/div),
(b) the diode D1 turnon instant (voltage: 200 V/div; current: 1 A/div; time scale: 500 ns/div), and (c) the diode D1 turnoff instant (voltage: 200 V/div;
current: 1 A/div; time scale: 500 ns/div).

SEPIC, and Zeta, as shown in Fig. 9. Furthermore, it can be

extended to isolated single-switch dc–dc converters such as
forward, flyback, isolated Cuk, isolated SEPIC, and isolated
Zeta, as shown in Fig. 10.
In all topology variations, the theoretical operating modes are
very similar to the operation of the boost converter explained in
Section II.

Fig. 8. Efficiency of the proposed boost converter in comparison with con-
ventional hard-switching boost converter.
V. T OPOLOGY V ARIATIONS OF THE
P ROPOSED C ONVERTER
The proposed topology can be extended to other nonisolated
single-switch dc–dc converters such as buck, buck–boost, Cuk,
VI. C ONCLUSION
In this paper, a new PWM SSS boost converter without
high voltage and current stresses has been described. This
converter does not require any extra switch to achieve soft
switching, which considerably simplifies the control circuit.
The experimental results of a 120-W 100-kHz prototype circuit
confirm the theoretical analysis of the proposed converter. The
proposed topology is extended to other nonisolated and isolated
single-switch dc–dc converters.
AMINI AND FARZANEHFARD: NOVEL FAMILY OF PWM SSS DC–DC CONVERTERS WITH COUPLED INDUCTORS 2113

Fig. 9. Topology variations of the proposed converter: (a) buck, (b) buck–boost, (c) Cuk, (d) SEPIC, and (e) Zeta converters.

Fig. 10. Isolated topology variations of the proposed converter: (a) forward, (b) flyback, (c) isolated Cuk, (d) isolated SEPIC, and (e) isolated Zeta converter.
2114
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Mohammad Reza Amini (S’08) was born in
Isfahan, Iran, in 1984. He received the B.S. and
M.S. degrees in electrical engineering from Isfahan
University of Technology, Isfahan, in 2006 and 2009,
respectively, where he is currently working toward
the Ph.D. degree in electrical engineering in the
Department of Electrical and Computer Engineering.
His research interest is soft-switching techniques
in dc–dc and dc–ac converters.
Hosein Farzanehfard (M’08) was born in Isfahan,
Iran, in 1961. He received the B.S. and M.S. de-
grees in electrical engineering from the University of
Missouri, Columbia, in 1983 and 1985, respectively,
and the Ph.D. degree from Virginia Polytechnic In-
stitute and State University, Blacksburg, in 1992.
Since 1993, he has been a Faculty Member in the
Department of Electrical and Computer Engineering,
Isfahan University of Technology, Isfahan, where he
is currently an Associate Professor and the President
of the Information and Communication Technology
Institute. He is the author of more than 70 technical papers published in journals
and conference proceedings. His research interests include high-frequency soft-
switching converters, pulse power applications, power factor correction, active
power filters, and high-frequency electronic ballasts.