DGTL RCVR HBK 43

®
Software Defined Radio Handbook

Seventh Edition
Sampling
Principles of SDR
Technology
Products
Applications
Summary
Links
by
Rodger H. Hosking
Vice-President & Cofounder of Pentek, Inc.
Pentek, Inc.
One Park Way, Upper Saddle River, New Jersey 07458
Tel: (201) 818-5900 • Fax: (201) 818-5904
Email: info@pentek.com • http://www.pentek.com
Copyright © 1998, 2001, 2003, 2006, 2008 Pentek Inc.

Last updated: September 2009
All rights reserved.
Contents of this publication may not be reproduced in any form without written permission.
Specifications are subject to change without notice.
Pentek, GateFlow, ReadyFow and VIM are registered trademarks of Pentek, Inc.
1
Pentek, Inc. • One Park Way, Upper Saddle River, NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.com • http://www.pentek.com
Preface
SDR (Software Defined Radio) has revolutionized electronic systems for a

variety of applications including communications, data acquisition and signal processing.
This handbook shows how DDCs (Digital Downconverters) and DUCs (Digital Upconverters),
the fundamental building blocks of SDR, can replace conventional analog receiver designs,
offering significant benefits in performance, density and cost.
In order to fully appreciate the benefits of SDR, a conventional analog receiver

system will be compared to its digital receiver counterpart, highlighting similarities and differences.
The inner workings of the SDR will be explored with an in-depth description of the internal
structure and the devices used. Finally, some actual board- and system-level implementations and available
off-the-shelf SDR products for embedded systems will be described.
2
Sampling
Nyquist’s Theorem and Sampling A Simple Technique to Visualize Sampling
Before we look at SDR and its various implementa-

tions in embedded systems, we’ll review a theorem
fundamental to sampled data systems such as those Frequency
0 fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/2
encountered in software defined radios.
Nyquist’s Theorem:
“Any signal can be represented by discrete Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7
samples if the sampling frequency is at least twice
the bandwidth of the signal.”
Figure 1
Notice that we highlighted the word bandwidth To visualize what happens in sampling, imagine
rather than frequency. In what follows, we’ll attempt to that you are using transparent “fan-fold” computer
show the implications of this theorem and the correct paper. Use the horizontal edge of the paper as the
interpretation of sampling frequency, also known as frequency axis and scale it so that the paper folds line
sampling rate. up with integer multiples of one-half of the sampling
frequency ƒs. Each sheet of paper now represent what we
will call a “Nyquist Zone”, as shown in Figure 1.
3
Sampling
Sampling Basics Baseband Sampling
0 fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/2 0 fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/2
Energy
No Signal Energy
Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7 Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7
Figure 2 Figure 4
Use the vertical axis of the fan-fold paper for signal A baseband signal has frequency components that
energy and plot the frequency spectrum of the signal to start at ƒ = 0 and extend up to some maximum frequency.
be sampled, as shown in Figure 2. To see the effects of
To prevent data destruction when sampling a baseband
sampling, collapse the transparent fan-fold paper into a
signal, make sure that all the signal energy falls ONY in
stack.
the 1st Nyquist band, as shown in Figure 4.
There are two ways to do this:
0 fs/2 1. Insert a lowpass filter to eliminate all signals
Folded Signals
Fall On Top of
above ƒs /2, or
Each Other 2. Increase the sampling frequency so all signals
present fall below ƒs /2.
Note that ƒs/2 is also known as the “folding frequency”.
Sampling Bandpass Signals
Let’s consider bandpass signals like the IF frequency

Figure 3 of a communications receiver that might have a 70 MHz
center frequency and 10 MHz bandwidth. In this case,
the IF signal contains signal energery from 65 to 75 MHz.
The resulting spectrum can be seen by holding the
transparent stack up to a light and looking through it. If we follow the baseband sampling rules above, we
You can see that signals on all of the sheets or zones are must sample this signal at twice the highest signal
“folded” or “aliased” on top of each other — and they frequency, meaning a sample rate of at least 150 MHz.
can no longer be separated. However, by taking advantage of a technique called
Once this folding or aliasing occurs during sampling, “undersampling”, we can use a much lower sampling rate.
the resulting sampled data is corrupted and can never be
recovered. The term “aliasing” is appropriate because
after sampling, a signal from one of the higher zones
now appears to be at a different frequency.
4
Sampling
Undersampling
Folded signals
still fall on top of
each other - but 0 fs/2
0 fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/2
now there is
energy in
only one sheet !
No Signal Energy No Signal Energy
Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7
Figure 5 Figure 6
Undersampling allows us to use aliasing to our The major rule to follow for successful undersampling
advantage, providing we follow the strict rules of the is to make sure all of the energy falls entirely in one
Nyquist Theorem. Nyquist zone.
In our previous IF signal example, suppose we try a There two ways to do this:
sampling rate of 40 MHz. 1. Insert a bandpass filter to eliminate all signals
outside the one Nyquist zone.
Figure 5 shows a fan-fold paper plot with Fs = 40 MHz.
2. Increase the sampling frequency so all signals
You can see that zone 4 extends from 60 MHz to 80 MHz,
fall entirely within one Nyquist zone.
nicely containing the entire IF signal band of 65 to 75 MHz.
Now when you collapse the fan fold sheets as shown
in Figure 6, you can see that the IF signal is preserved Summary
after sampling because we have no signal energy in any
other zone. Baseband sampling requires the sample frequency to
be at least twice the signal bandwidth. This is the same
Also note that the odd zones fold with the lower
as saying that all of the signals fall within the first
frequency at the left (normal spectrum) and the even
Nyquist zone.
zones fold with the lower frequency at the right (reversed
spectrum). In real life, a good rule of thumb is to use the 80%
relationship:
In this case, the signals from zone 4 are frequency
reversed. This is usually very easy to accommodate in Bandwidth = 0.8 x ƒs/2
the following stages of SDR systems.
Undersampling allows a lower sample rate even though
signal frequencies are high, PROVIDED all of the
signal energy falls within one Nyquist zone.
To repeat the Nyquist theorem: The sampling frequency
must be at least twice the signal bandwidth — not the
signal frequency.
5
Principles of SDR
Analog Radio Receiver Block Diagram Analog Radio Receiver Mixer
SPEAKER RF INPUT SIGNAL

FROM ANTENNA
ANTENNA
MIXER TRANSLATES Signal
INPUT SIGNAL BAND
ANALOG to IF FREQUENCY
MIXER
RF IF AMP DEMODULATOR AUDIO

AMP (FILTER) (Detector) AMP
ANALOG LOCAL
OSCILLATOR
ANALOG
LOCAL
OSCILLATOR
0 FIF FRF
Figure 7 Figure 8
The conventional heterodyne radio receiver shown The mixer performs an analog multiplication of the
in Figure 7, has been in use for nearly a century. Let’s two inputs and generates a difference frequency signal.
review the structure of the analog receiver so comparison
The frequency of the local oscillator is set so that
to a digital receiver becomes apparent.
the difference between the local oscillator frequency and
First the RF signal from the antenna is amplified, the desired input signal (the radio station you want to
typically with a tuned RF stage that amplifies a region receive) equals the IF.
of the frequency band of interest.
For example, if you wanted to receive an FM
This amplified RF signal is then fed into a mixer station at 100.7 MHz and the IF is 10.7 MHz, you would
stage. The other input to the mixer comes from the local tune the local oscillator to:
oscillator whose frequency is determined by the tuning
100.7 - 10.7 = 90 MHz
control of the radio.
This is called “downconversion” or “translation”
The mixer translates the desired input signal to the
because a signal at a high frequency is shifted down to a
IF (Intermediate Frequency) as shown in Figure 8.
lower frequency by the mixer.
The IF stage is a bandpass amplifier that only lets
The IF stage acts as a narrowband filter which only
one signal or radio station through. Common center
passes a “slice” of the translated RF input. The band-
frequencies for IF stages are 455 kHz and 10.7 MHz
width of the IF stage is equal to the bandwidth of the
for commercial AM and FM broadcasts.
signal (or the “radio station”) that you are trying to
The demodulator recovers the original modulating receive.
signal from the IF output using one of several different
For commercial FM, the bandwidth is about
schemes.
100 kHz and for AM it is about 5 kHz. This is consis-
For example, AM uses an envelope detector and FM tent with channel spacings of 200 kHz and 10 kHz,
uses a frequency discriminator. In a typical home radio, respectively.
the demodulated output is fed to an audio power
amplifier which drives a speaker.
6
Principles of SDR
SDR Receiver Block Diagram
DDC
Digital Downconverter
Digital
Analog Analog Digital IF Baseband
RF Signal RF IF Signal A/D Samples DIGITAL LOWPASS Samples
DSP
TUNER CONV MIXER FILTER
DIGITAL
LOCAL
OSC
Figure 9
Figure 9 shows a block diagram of a software SDR Receiver Mixer

defined radio receiver. The RF tuner converts analog RF
signals to analog IF frequencies, the same as the first three
CHANNEL
stages of the analog receiver. BANDWIDTH MIXER TRANSLATES
INPUT SIGNAL
BAND to DC IF BW
The A/D converter that follows digitizes the IF signal Signal
thereby converting it into digital samples. These samples

are fed to the next stage which is the digital downconverter DIGITAL LOCAL
(DDC) shown within the dotted lines. OSCILLATOR
FLO = FSIG
The digital downconverter is typically a single
monolithic chip or FPGA IP, and it is a key part of the
SDR system.
0 FSIG
Figure 10
A conventional DDC has three major sections:
• A digital mixer
• A digital local oscillator At the output of the mixer, the high frequency
wideband signals from the A/D input (shown in Figure
• An FIR lowpass filter
10 above) have been translated down to DC as complex I
The digital mixer and local oscillator translate the and Q components with a frequency shift equal to the
digital IF samples down to baseband. The FIR lowpass local oscillator frequency.
filter limits the signal bandwidth and acts as a decimat- This is similar to the analog receiver mixer except
ing lowpass filter. The digital downconverter includes a there, the mixing was done down to an IF frequency.
lot of hardware multipliers, adders and shift register Here, the complex representation of the signal allows us
memories to get the job done. to go right down to DC.
The digital baseband samples are then fed to a block By tuning the local oscillator over its range, any
labeled DSP which performs tasks such as demodulation, portion of the RF input signal can be mixed down to DC.
decoding and other processing tasks.
In effect, the wideband RF signal spectrum can be
Traditionally, these needs have been handled with “slid” around 0 Hz, left and right, simply by tuning the
dedicated application specific ICs (ASICs), and program- local oscillator. Note that upper and lower sidebands are
mable DSPs. preserved.
7
Principles of SDR
DDC Local Oscillator and Decimation DDC Signal Processing
Translation Filtering
Digital
Digital IF Baseband
A/D Samples DIGITAL LOWPASS Samples
CONV MIXER FILTER
90O
DIGITAL
LOCAL
OSC
Tuning Freq Decimation

F1 F2 F3
Figure 12
Figure 11A Local Oscillator Frequency Switching
This process is called decimation and it means keeping

A/D Sample Rate one out of every N signal samples. If the decimated
(before decimation)
Sample Rate: Fs output sample rate is kept higher than twice the output
bandwidth, no information is lost.
Decimated
Filter Output
The clear benefit is that decimated signals can be
Sample Rate: Fs/N processed easier, can be transmitted at a lower rate, or
stored in less memory. As a result, decimation can
Figure 11B FIR Filter Decimation dramatically reduce system costs!
As shown in Figure 12, the DDC performs two
signal processing operations:
Because the local oscillator uses a digital phase
accumulator, it has some very nice features. It switches 1. Frequency translation with the tuning controlled
between frequencies with phase continuity, so you can by the local oscillator.
generate FSK signals or sweeps very precisely with no
2. Lowpass filtering with the bandwidth controlled
transients as shown in Figure 11A.
by the decimation setting.
The frequency accuracy and stability are determined
We will next turn our attention to the Software
entirely by the A/D clock so it’s inherently synchronous
Defined Radio Transmitter.
to the sampling frequency. There is no aging, drift or
calibration since it’s implemented entirely with digital logic.
Since the output of the FIR filter is band limited, the
Nyquist theorem allows us to lower the sample rate. If
we are keeping only one out of every N samples, as shown
in Figure 11B above, we have dropped the sampling rate
by a factor of N.
8
Principles of SDR
SDR Transmitter Block Diagram
Digital Digital Analog Analog

Baseband Baseband Digital IF IF RF
Samples Samples DIGITAL Samples Signal Signal
INTERPOLATION D/A RF Power
DSP
FILTER MIXER CONV Upconverter Amplifier
Fs/N Fs Fs
DUC DIGITAL
Digital Up LOCAL
Converter OSC
Figure 13
The input to the transmit side of an SDR system is DUC Signal Processing
a digital baseband signal, typically generated by a DSP
stage as shown in Figure 13 above.
The digital hardware block in the dotted lines is a Digital Digital
DUC (digital upconverter) that translates the baseband Baseband Baseband Digital IF
Samples Samples DIGITAL Samples
signal to the IF frequency. INTERPOLATION
FILTER MIXER
Fs/N Fs Fs
The D/A converter that follows converts the digital
IF samples into the analog IF signal. DUC DIGITAL
Digital Up LOCAL
Next, the RF upconverter converts the analog IF Converter OSC
signal to RF frequencies.
Figure 14
Finally, the power amplifier boosts signal energy to
the antenna.
Inside the DUC shown in Figure 14, the digital
mixer and local oscillator at the right translate baseband
samples up to the IF frequency. The IF translation
frequency is determined by the local oscillator.
The mixer generates one output sample for each of
its two input samples. And, the sample frequency at
the mixer output must be equal to the D/A sample
frequency ƒs .
Therefore, the local oscillator sample rate and the
baseband sample rate must be equal to the D/A sample
frequency ƒs .
The local oscillator already operates at a sample rate
of ƒs , but the input baseband sample frequency at the
left is usually much lower. This problem is solved with
the Interpolation Filter.
9
Principles of SDR
Interpolation Filter: Time domain Interpolation Filter: Frequency Domain
Fs/N Fs Digital Digital

Baseband Baseband Digital IF
I INTERPOLATING I Samples Samples Samples
LOW PASS INTERPOLATION DIGITAL
Q FIR FILTER Q Fs/N FILTER MIXER
Fs Fs
BASEBAND INTER-
INPUT POLATED DUC
OUTPUT DIGITAL
Digital Up LOCAL
Converter OSC
INTERPOLATION
FACTOR = N
INTERPOLATED
BASEBAND INPUT TRANSLATED OUTPUT
Baseband Input
MIXER
Sample Rate: Fs/N
LOCAL
OSCILLATOR
F = IF Freq
Interpolating
Filter Output
Sample Rate: Fs 0 IF Freq
Figure 15 Figure 16
The interpolation filter must boost the baseband Figure 16 is a frequency domain view of the digital
input sample frequency of ƒs /N up to the required mixer upconversion process.
input and D/A output sample frequency of ƒs .
This is exactly the opposite of the frequency domain
The interpolation filter increases the sample frequency view of the DDC in Figure 10.
of the baseband input signal by a factor N, known as
The local oscillator setting is set equal to the
the interpolation factor.
required IF signal frequency, just as with the DDC.
At the bottom of Figure 15, the effect of the
interpolation filter is shown in the time domain.
Notice the baseband signal frequency content is
completely preserved by filling in additional samples in
the spaces between the original input samples.
The signal processing operation performed by the
interpolation filter is the inverse of the decimation filter
we discussed previously in the DDC section.
10
Principles of SDR
DDC Processing DUC Processing
Translation Filtering Filtering Translation
A/D DIGITAL LOWPASS INTERPOLATE DIGITAL D/A

DSP DSP
CONV MIXER FILTER FILTER MIXER CONV
Fs Fb Fb Fs
DIGITAL ´ N DIGITAL
LOCAL ¸ N LOCAL
OSC OSC
Freq uency Deci mation Inter polation Freq uency
Tuning Bandwidth Bandwidth Tuning

Figure 17 Figure 18
Figure 17 shows the two-step processing performed Figure 18 shows the two-step processing performed
by the digital downconverter. by the digital upconverter:
Frequency translation from IF down to baseband is The ratio between the required output sample rate
performed by the local oscillator and mixer. and the sample rate input baseband sample rate deter-
mines the interpolation factor N.
The “tuning” knob represents the programmability
of the local oscillator frequency to select the desired ● Baseband bandwidth = 0.8 x ƒb
signal for downconversion to baseband.
● Output sample frequency ƒs = ƒb x N
The baseband signal bandwidth is set by setting
Again, the bandwidth equation assumes a complex
decimation factor N and the lowpass FIR filter:
(I+Q) baseband input and an 80% filter.
● Baseband sample frequency ƒb = ƒs /N
The “bandwidth” knob represents the programma-
● Baseband bandwidth = 0.8 x ƒb bility of the interpolation factor to select the desired
input baseband signal bandwidth.
The baseband bandwidth equation reflects a typical
80% passband characteristic, and complex (I+Q) samples. Frequency translation from baseband up to IF is
performed by the local oscillator and mixer.
The “bandwidth” knob represents the program-
mability of the decimation factor to select the desired The “tuning” knob represents the programmability
baseband signal bandwidth. of the local oscillator frequency to select the desired IF
frequency for translation up from baseband.
11
Principles of SDR
Key DDC and DUC Benefits SDR Tasks
Digital
Digital IF Baseband
A/D Samples DIGITAL LOWPASS Samples
CONV MIXER FILTER
Fs Fs/N
DIGITAL
DUC
LOCAL Digital Down
OSC Converter
Digital Digital
Baseband Baseband Digital IF
Samples Samples DIGITAL Samples
INTERPOLATION D/A
FILTER MIXER CONV
Fs/N Fs Fs
DUC DIGITAL
Digital Up LOCAL
Converter OSC
Figure 19 Figure 20
Think of the DDC as a hardware preprocessor for Here we’ve ranked some of the popular signal
programmable DSP or GPP processor. It preselects only processing tasks associated with SDR systems on a two
the signals you are interested in and removes all others. axis graph, with compute Processing Intensity on the
This provides an optimum bandwidth and minimum vertical axis and Flexibility on the horizontal axis.
sampling rate into the processor.
What we mean by process intensity is the degree of
The same applies to the DUC. The processor only highly-repetitive and rather primitive operations. At the
needs to generate and deliver the baseband signals upper left, are dedicated functions like A/D converters
sampled at the baseband sample rate. The DUC then and DDCs that require specialized hardware structures
boosts the sampling rate in the interpolation filter, to complete the operations in real time. ASICs are usually
performs digital frequency translation, and delivers chosen for these functions.
samples to the D/A at a very high sample rate.
Flexibility pertains to the uniqueness or variability
The number of processors required in a system is of the processing and how likely the function may have
directly proportional to the sampling frequency of to be changed or customized for any specific application.
input and output data. As a result, by reducing the At the lower right are tasks like analysis and decision
sampling frequency, you can dramatically reduce the making which are highly variable and often subjective.
cost and complexity of the programmable DSPs or
Programmable general-purpose processors or DSPs
GPPs in your system.
are usually chosen for these tasks since these tasks can be
Not only do DDCs and DUCs reduce the processor easily changed by software.
workload, the reduction of bandwidth and sampling rate
Now let’s temporarily step away from the software
helps save time in data transfers to another subsystem. This
radio tasks and take a deeper look at programmable
helps minimize recording time and disk space, and reduces
logic devices.
traffic and bandwidth across communication channels.
12
Technology
Early Roles for FPGAs Legacy FPGA Design Methodologies
§ Used primarily to replace discrete digital § Tools were oriented to hardware engineers
hardware circuitry for: Schematic processors
Control logic Boolean processors
Glue logic Gates, registers, counters, multipliers
Registers and gates § Successful designs required high-level

State machines hardware engineering skills for:
Counters and dividers Critical paths and propagation delays
§ Devices were selected by hardware engineers Pin assignment and pin locking
Signal loading and drive capabilities
§ Programmed functions were seldom changed
Clock distribution
after the design went into production Input signal synchronization and skew analysis
Figure 21 Figure 22
As true programmable gate functions became These programmable logic devices were mostly the
available in the 1970’s, they were used extensively by domain of hardware engineers and the software tools
hardware engineers to replace control logic, registers, were tailored to meet their needs. You had tools for
gates, and state machines which otherwise would have accepting boolean equations or even schematics to help
required many discrete, dedicated ICs. generate the interconnect pattern for the growing
number of gates.
Often these programmable logic devices were one-
time factory-programmed parts that were soldered down Then, programmable logic vendors started offering
and never changed after the design went into production. predefined logic blocks for flip-flops, registers and
counters that gave the engineer a leg up on popular
hardware functions.
Nevertheless, the hardware engineer was still
intimately involved with testing and evaluating the
design using the same skills he needed for testing
discrete logic designs. He had to worry about propaga-
tion delays, loading, clocking and synchronizing—all
tricky problems that usually had to be solved the hard
way—with oscilloscopes or logic analyzers.
13
Technology
FPGAs: New Device Technology FPGAs: New Development Tools
§ 500+ MHz DSP Slices and Memory Structures

§ Over 1000 dedicated on-chip hardware multipliers
§ On-board GHz Serial Transceivers § High Level Design Tools
§ Partial Reconfigurability Maintains Block Diagram System Generators
Operation During Changes Schematic Processors
§ Switched Fabric Interface Engines High-level language compilers for
§ Over 330,000 Logic Cells VHDL & Verilog
§ Gigabit Ethernet media access controllers Advanced simulation tools for modeling speed,
propagation delays, skew and board layout
§ On-chip 405 PowerPC RISC micro-controller cores
Faster compilers and simulators save time
§ Memory densities approaching 15 million bits
Graphically-oriented debugging tools
§ Reduced power with core voltages at 1 volt
§ IP (Intellectual Property) Cores
§ Silicon geometries to 65 nanometers
FPGA vendors offer both free and licensed cores
§ High-density BGA and flip-chip packaging
FPGA vendors promote third party core vendors
§ Over 1200 user I/O pins
Wide range of IP cores available
§ Configurable logic and I/O interface standards
Figure 23 Figure 24
It’s virtually impossible to keep up to date on FPGA To support such powerful devices, new design tools
technology, since new advancements are being made are appearing that now open up FPGAs to both hard-
every day. ware and software engineers. Instead of just accepting
logic equations and schematics, these new tools accept
The hottest features are processor cores inside the
entire block diagrams as well as VHDL and Verilog
chip, computation clocks to 500 MHz and above, and
definitions.
lower core voltages to keep power and heat down.
Choosing the best FPGA vendor often hinges
About five years ago, dedicated hardware multipliers
heavily on the quality of the design tools available to
started appearing and now you’ll find literally hundreds
support the parts.
of them on-chip as part of the DSP initiative launched
by virtually all FPGA vendors. Excellent simulation and modeling tools help to
quickly analyze worst case propagation delays and
High memory densities coupled with very flexible
suggest alternate routing strategies to minimize them
memory structures meet a wide range of data flow
within the part. This minimizes some of the tricky
strategies. Logic slices with the equivalent of over ten
timing work for hardware engineers and can save one
million gates result from silicon geometries shrinking
hours of tedious troubleshooting during design verifica-
down to 0.1 micron.
tion and production testing.
BGA and flip-chip packages provide plenty of I/O
In the last few years, a new industry of third party
pins to support on-board gigabit serial transceivers and
IP (Intellectual Property) core vendors now offer
other user-configurable system interfaces.
thousands of application-specific algorithms. These are
New announcements seem to be coming out every ready to drop into the FPGA design process to help beat
day from chip vendors like Xilinx and Altera in a never- the time-to-market crunch and to minimize risk.
ending game of outperforming the competition.
14
Technology
FPGAs for SDR FPGAs Bridge the SDR Application Space
§ Parallel Processing
§ Hardware Multipliers for DSP
FPGAs can now have over 500 hardware multipliers
§ Flexible Memory Structures
Dual port RAM, FIFOs, shift registers, look up tables, etc.
§ Parallel and Pipelined Data Flow
Systolic simultaneous data movement
§ Flexible I/O
Supports a variety of devices, buses and interface standards
§ High Speed
§ Available IP cores optimized for special functions
Figure 25 Figure 26
Like ASICs, all the logic elements in FPGAs can As a result, FPGAs have significantly invaded the
execute in parallel. This includes the hardware multipli- application task space as shown by the center bubble in
ers, and you can now get over 1000 of them on a single the task diagram above.
FPGA.
They offer the advantages of parallel hardware to
This is in sharp contrast to programmable DSPs, handle some of the high process-intensity functions like
which normally have just a handful of multipliers that DDCs and the benefit of programmability to accommo-
must be operated sequentially. date some of the decoding and analysis functions of DSPs.
FPGA memory can now be configured with the These advantages may come at the expense of
design tool to implement just the right structure for increased power dissipation and increased product costs.
tasks that include dual port RAM, FIFOs, shift registers However, these considerations are often secondary to the
and other popular memory types. performance and capabilities of these remarkable devices.
These memories can be distributed along the signal
path or interspersed with the multipliers and math
blocks, so that the whole signal processing task operates
in parallel in a systolic pipelined fashion.
Again, this is dramatically different from sequential
execution and data fetches from external memory as in a
programmable DSP.
As we said, FPGAs now have specialized serial and
parallel interfaces to match requirements for high-speed
peripherals and buses.
15
Technology
Typical Pentek Products with Installed SDR IP Cores
Model
Model
7141-430
7141-430 7141-420
7141-420 7142-428
7142-428 7151
7151 7152
7152 7153
7153
Feature
Feature
Input
InputChannels
Channels 11 22 44 44 44 44
Max
MaxSample
SampleRate
Rate 125
125MHz
MHz 125
125MHz
MHz 125
125MHz
MHz 200
200MHz
MHz 200
200MHz
MHz 200
200MHz
MHz
Input
Input Resolution
Resolution 14-Bit
14-Bit 14-Bit
14-Bit 14-Bit
14-Bit 16-Bit
16-Bit 16-Bit
16-Bit 16-Bit
16-Bit
DDC
DDCChannels
Channels 256
256 22or
or44 44 256
256 32
32 22or
or44
Core:
Core:2,4,8,16,32,64
2,4,8,16,32,64 22to
to64K
64K 128
128to
to1024
1024 16
16to
to8192
8192 22Ch:
Ch:22to
to65536
65536
Decimation
DecimationRange
Range 1K-10K
1K-10K GC4016:
GC4016:32to
32to16k
16k Steps
Stepsof of11 Steps
Stepsof
of64
64 Steps
Stepsofof88 44Ch:
Ch:22to
to256
256
No.
No.of
ofFilter
FilterTaps
Taps 24*DEC/512
24*DEC/512 Core:
Core:28*DEC
28*DEC 28*DEC
28*DEC 24*DEC/64
24*DEC/64 28*DEC/8
28*DEC/8 28*DEC
28*DEC
Power
PowerMeters
Meters None
None None
None None
None None
None 32
32 22or
or44
Thresh
ThreshDetectors
Detectors None
None None
None None
None None
None 32
32 22or
or44
Channel
ChannelSummers
Summers None
None None
None None
None None
None 32
32channels
channels 22or
or44channels
channels
I/Q,
I/Q,Offset,
Offset, I/Q,
I/Q, I/Q,
I/Q, I/Q,
I/Q, I/Q,
I/Q,
Output
OutputFormat
Format Normal
NormalI/Q
I/Q Inverse,
Inverse,Real
Real Offset,
Offset,Inverse
Inverse Offset,
Offset,Inverse
Inverse Offset,
Offset,Inverse
Inverse Offset,
Offset,Inverse
Inverse
Output
OutputResolution
Resolution 16-Bit
16-Bit 16-Bit,
16-Bit,24-Bit
24-Bit 16-Bit,
16-Bit,24-Bit
24-Bit 16-Bit,
16-Bit,24-Bit
24-Bit 16-Bit,
16-Bit,24-Bit
24-Bit 16-Bit,
16-Bit,24-Bit
24-Bit
Tuning
TuningFrequency
Frequency 32-bits
32-bits--00to
toFs
Fs 32-bits
32-bits--00to
toFs
Fs 32-bits
32-bits--00to
toFs
Fs 32-bits
32-bits--00to
toFs
Fs 32-bits
32-bits--00to
toFs
Fs 32-bits
32-bits--00to
toFs
Fs
Phase
PhaseOffset
Offset -- 32-bits
32-bits±±180
180deg
deg 32-bits
32-bits±±180
180deg
deg 32-bits
32-bits±±180
180deg
deg 32-bits
32-bits±±180
180deg
deg 32-bits
32-bits±±180
180deg
deg
Gain
GainControl
Control 32
32bits
bits 32
32bits
bits 32
32bits
bits 32
32bits
bits 32
32bits
bits 32
32bits
bits
DAC
DAC Interpolation
Interpolation None
None 22--32768
32768 22--32768
32768 None
None None
None None
None
Figure 27
The above chart shows the salient characteristics for Other information that’s specific to each core is
some of Pentek’s SDR products with IP cores installed included as well as an indication of the Models that
in their FPGAs. The chart provides information regard- include an interpolation filter and output D/A. As shown
ing the number of input channels, maximum sampling in the chart, some of these Models include power meters,
frequency of their A/Ds, and number of DDC channels threshold detectors, and gain along with phase offset
in each one. This information is followed by DDC control for optimizing results in applications such as
characteristics regarding the decimation range and available direction-finding and beamforming.
steps along with the output format and resolution.
All the Models shown here are PMC or PMC/XMC
modules. These products are also available in PCI, cPCI
and PCIe formats as well.
16
Technology
FPGA Resource Comparison
Virtex-II Pro Virtex-4 Virtex-5

VP50 SX55 SX50T
LUT Organization 4 Input LUT 4 Input LUT 6 Input LUT
FF/Logic Ratio Good Good Poor
LUT/FF Pairs 53,136 49,152 32,640
DSP Hard IP 18x18 Multipliers DSP48 DSP48E
DSP Quantity 232 512 288
DSP Speed Good Better Best
Block RAM 2 kB 2 kB 4 kB or 2 kB
Used as DPRAM 512x36 DPRAM 512x36 DPRAM Restrictions
Uses one 2 kB Uses one 2 kB 512x36 DPRAM
Block RAM Block RAM Uses 2 kB
Block RAM
Used as FIFO Good Better Best
Block RAM Quantity 232 320 132–4 kB
264–2 kB
Block RAM Speed Good Better Best
Figure 28
The above chart compares the available resources in While the Virtex-5 FPGAs have enhancements to
the three FPGA families that are used in the Pentek DSP resources, they don’t necessarily provide a significant
Models shown in the previous chart. A few remarks are advantage in the quantity of these resources.
now appropriate:
The Model 7142-428 quad DDC utilizes the
The Models 7141-430 and 7141-420 utilize the Virtex-4 SX55 while the Model 7153 quad DDC uses
Virtex-II Pro VP50. The speed of this FPGA is well the Virtex-5 SX50T. The existing 7142-428 could not
matched to the maximum sampling frequency of 125 MHz. be ported to the new 7153 because it would not fit. The
Both the Virtex-II Pro and the Virtex-4 SX55 have Virtex-5 SX50T has less DSP blocks and differently
ample DSP resources for most typical applications such orgnized RAM blocks. In addition, the maximum design
as FIR filters, DDCs, DUCs, FFTs and demodulators. speed degrades more rapidly as resource usage increases.
17
Products
PMC, PMC/XMC, CompactPCI, PCI, PCI Express and VMEbus Software Radio
Half-length
PCI Express Board
PCI Board
PMC/XMC Module
CompactPCI Board Full-length VMEbus Board

PCI Express Board
Figure 29
The Pentek family of board-level software radio All Pentek software radio products include multiboard
products is the most comprehensive in the industry. synchronization that facilitates the design of multichannel
Most of these products are available in several formats systems with synchronous clocking, gating and triggering.
to satisfy a wide range of requirements.
Pentek’s comprehensive software support includes
In addition to their commercial versions, many the ReadyFlow® Board Support Package, the GateFlow®
software radio products are available in ruggedized and FPGA Design Kit and high-performance factory-
conduction-cooled versions. installed IP cores that expand the features and range
of many Pentek software radio products. In addition,
All of the software radio products include input A/D
Pentek software radio recording systems are supported
converters. Some of these products are software radio
with SystemFlow® recording software that features a
receivers in that they include only DDCs. Others are
graphical user interface.
software radio transceivers and they include DDCs as
well as DUCs with output D/A converters. These come A complete listing of these products with active
with independent input and output clocks. links to their datasheets on Pentek’s website is included
at the end of this handbook.
18
Products
Multiband Receivers
Model 7131 PMC ● Model 7231 6U cPCI ● Model 7331 3U cPCI ● Model 7631A PCI
Model 7631A
PCI
Model 7131
PMC Model 7331 Model 7231D
Figure 30 3U cPCI 6U cPCI
The Model 7131, a 16-Channel Multiband Receiver, The unit supports the channel combining mode of
is a PMC module. The 7131 PMC may be attached to a the 4016s such that two or four individual 2.5 MHz
wide range of industry processor platforms equipped channels can be combined for output bandwidths of
with PMC sites. 5 MHz or 10 MHz, respectively.
Two 14-bit 105 MHz A/D Converters accept The sampling clock can be sourced from an internal
transformer-coupled RF inputs through two front panel 100 MHz crystal oscillator or from an external clock supplied
SMA connectors. Both inputs are connected to four through an SMA connector or the LVDS clock/sync bus on
TI/GC4016 quad DDC chips, so that all 16 DDC the front panel. The LVDS bus allows multiple modules to be
channels can independently select either A/D. synchronized with the same sample clock, gating, triggering
and frequency switching signals. Up to 80 modules can be
Four parallel outputs from the four DDCs deliver
synchronized with the Model 9190 Clock and Sync Genera-
data into the Virtex-II FPGA which can be either the
tor. Custom interfaces can be implemented by using the 64
XC2V1000 or XC2V3000. The outputs of the two A/D
user-defined FPGA I/O pins on the P4 connector.
converters are also connected directly to the FPGA to
support the DDC bypass path to the PCI bus and for direct Versions of the 7131 are also available as a PCI
processing of the wideband A/D signals by the FPGA. board (Model 7631A), 6U cPCI (Models 7231 and
7231D dual density), or 3U cPCI (Model 7331). All
these products have similar features.
19
Products
Multiband Transceivers with Virtex-II Pro FPGA
Model 7140 PMC/XMC ● Model 7240 6U cPCI ● Model 7340 3U cPCI ● Model 7640 PCI
Sample
Clock A In RF In RF In RF Out RF Out
TIMING BUS XTL

LVDS Clock A RF RF RF XFORMR RF XFORMR
GENERATOR A OSC A
XFORMR XFORMR
LVDS Sync A
Clock/Sync/Gate 16-bit D/A 16-bit D/A
LVDS Gate A SYNC Bus A AD6645 AD6645 DAC5686
TTL Gate/ INTERRUPTS 105 MHz 105 MHz DIGITAL UPCONVERTER
Trigger & CONTROL Clock/Sync/Gate 14-bit A/D 14-bit A/D
Bus B
TTL Sync
14 14 GC4016 32
LVDS Gate B 4-CHANNEL
16 FLASH
16 DIGITAL
LVDS Sync B RECEIVER 16 MB
16 24
TIMING BUS XTL 14
LVDS Clock B
16
GENERATOR B OSC B
VIRTEX-II Pro FPGA
To All XC2VP50
Sample
Sections Control/ DSP – Channelizer – Digital Delay – Demodulation – Decoding – Control – etc.
Clock B In
Status
32 32 32
64 8X 64
Model 7140 DDR DDR DDR
SDRAM SDRAM SDRAM
PMC/XMC PCI 2.2 INTERFACE P15 XMC P4 PMC
128 MB 128 MB 256 MB (64 Bits / 66 MHz) VITA 42.0 FPGA I/O
(Serial RapidIO, (Option –104)
PCI BUS
PCI-Express, etc.)
(64 Bits / 66 MHz)
Figure 31
The Model 7140 PMC module combines both In addition to acting as a simple transceiver, the
receive and transmit capability with a high-performance module can perform user-defined DSP functions on the
Virtex II-Pro FPGA and supports the VITA 42 XMC baseband signals, developed using Pentek’s GateFlow
standard with optional switched fabric interfaces for and ReadyFlow development tools.
high-speed I/O.
The module includes a TI/GC4016 quad digital
The front end of the module accepts two RF inputs downconverter along with a TI DAC5686 digital
and transformer-couples them into two 14-bit A/D upconverter with dual D/A converters.
converters running at 105 MHz. The digitized output
Each channel in the downconverter can be set with
signals pass to a Virtex-II Pro FPGA for signal process-
an independent tuning frequency and bandwidth. The
ing or routing to other module resources.
upconverter translates a real or complex baseband signal to
These resources include a quad digital down- any IF center frequency from DC to 160 MHz and can
converter, a digital upconverter with dual D/A convert- deliver real or complex (I + Q) analog outputs through
ers, 512 MB DDR SDRAM delay memory and the PCI its two 16-bit D/A converters. The digital upconverter
bus. The FPGA also serves as a control and status can be bypassed for two interpolated D/A outputs with
engine with data and programming interfaces to each of sampling rates to 500 MHz.
the on-board resources. Factory-installed FPGA functions
Versions of the 7140 are also available as a PCI
include data multiplexing, channel selection, data packing,
board (Model 7640), 6U cPCI (Models 7240 and
gating, triggering, and SDRAM memory control.
7240D dual density), or 3U cPCI (Model 7340). All
these products have similar features.
20
Products
Transceivers with Dual Wideband DDC and Interpolation Filter Installed Cores
Model 7140-420 PMC/XMC ● Model 7240-420 6U cPCI

Model 7340-420 3U cPCI ● Model 7640-420 PCI
RF AD6645
CH A DDC C 128 MB DDR
105 MHz
RF In XFORMR DDC D SDRAM
14-bit A/D
MEMORY
D/A A
CONTROL 128 MB DDR
WIDEBAND DDC CORE D/A B & SDRAM
A/D A DATA ROUTING
RF AD6645
CH B A/D B 256 MB DDR
105 MHz
RF In XFORMR SDRAM
14-bit A/D
A/D A
WIDEBAND MEM W
A/D B M
DIGITAL FIFO
DDC A U
DOWNCONVERTR A
X MEM W
DDC B DECIMATION: 2 – 64
XTAL MEMORY FIFO
Sample OSC A MEMORY
A B C D A/D A A/D A PCI BUS
Clock A In
WIDEBAND FIFO 64 bit /
MUX A/D B M
CLOCK & DIGITAL 66 MHz
Clock/Sync DDC A U A/D B
SYNC GC4016 DIGITAL DOWNCONVERTR A
Bus X FIFO
GENERATOR DOWNCONVERTR DDC B DECIMATION:.2 – 64
WB DDC A
Sample DDC A
A B C D DDC A MUX PCI 2.2
Clock B In FIFO
XTAL WB DDC B INTERFACE
OSC B DDC B
DDC B MUX
FIFO
DDC C
FIFO
DDC D
RF 16-bit FIFO
CH A MEMORY
500 MHZ
RF Out XFORMR DAC 5686 MUX D/A A FIFO D/A A
D/A CIC CFIR
DIGITAL MEMORY FIFO
16-bit UPCONVERTER FILTER FILTER
CH B RF MUX D/A B FIFO D/A B
500 MHZ
RF Out XFORMR FIFO
D/A
INTERPOLATION CORE
XC2VP50
Figure 32
The Pentek IP Core 420 includes a dual high- The decimation settings of 2, 4, 8, 16, 32, and 64
performance wideband DDC and an interpolation filter. provide output bandwidths from 40 MHz down to
Factory-installed in the Model 7140 FPGA, they extend 1.25 MHz for an A/D sampling of 100 MHz. A multi-
the range of both the GC4016 ASIC DDC and the plexer in front of the Core 420 DDCs allows data to be
DAC5686 DUC. sourced from either the A/Ds or the GC4016, extending
the maximum cascaded decimation range to 1,048,576.
Like the GC4016, each of the core 420 DDCs
translates any frequency band within the input band- The interpolation filter included in the 420 Core,
width range down to zero frequency. A complex FIR low expands the interpolation factor from 2 to 32,768
pass filter removes any out-of-band frequency components. programmable in steps of 2, and relieves the host
An output decimator and formatter deliver either complex processor from performing upsampling tasks. Including
or real data. An input gain block scales both I and Q the DUC, the maximum interpolation factor is 32,768
data streams by a 16-bit gain term. which is comparable to the maximum decimation of the
GC4016 narrowband DDC.
The mixer utilizes four 18x18-bit multipliers to
handle the complex inputs from the NCO and the In addition to the Core 420, all the standard
complex data input samples. The FIR filter is capable of features of the 7140 are retained.
storing and utilizing up to four independent sets of
Versions of the 7140-420 are also available as a PCI
18-bit coefficients for each decimation value. These
board (Model 7640-420), 6U cPCI (Models 7240-420
coefficients are user-programmable by using RAM
and 7240D-420 dual density), or 3U cPCI (Model
structures within the FPGA.
7340-420). All these products have similar features.
21
Products
Transceivers with 256-Channel Narrowband DDC Installed Core
Model 7140-430 PMC/XMC ● Model 7240-430 6U cPCI

Model 7340-430 3U cPCI ● Model 7640-430 PCI
RF AD6645
CH A MEM W
105 MHz
RF In XFORMR FIFO
14-bit A/D
MEM W
FIFO
256 CHANNEL DIGITAL DOWNCONVERTER BANK
AD6645 CORE
CH B RF
105 MHz
RF In XFORMR 1 DDC 1
14-bit A/D OUT A
Local Oscillator, Mixer, Filter DDC A
DDC A
FIFO
2 DDC 1
OUT B
MUX Local Oscillator, Mixer, Filter DDC B
XTAL DDC B
M M FIFO
Sample OSC A
A B C D U OUT C U
Clock A In PCI BUS
X X DDC C
DDC C 64 bit /
CLOCK & MUX 255 DDC 255 FIFO
Clock/Sync 66 MHz
SYNC GC4016 DIGITAL Local Oscillator, Mixer, Filter OUT D
Bus DDC D
GENERATOR DOWNCONVERTR . DDC D
Sample 256 DDC 256 FIFO
A B C D PCI 2.2
Clock B In Local Oscillator, Mixer, Filter
XTAL INTERFACE
INT
OSC B
RF 16-bit
CH A
500 MHZ D/A A
RF Out XFORMR DAC 5686
D/A FIFO
DIGITAL
16-bit UPCONVERTER D/A B
CH B RF
500 MHZ FIFO
RF Out XFORMR D/A XC2VP50
Figure 33
For applications that require many channels of cies need not be at fixed intervals, and are independently
narrowband downconverters, Pentek offers the GateFlow programmable to any value.
IP Core 430 256-channel digital downconverter bank.
Core 430 DDC comes factory installed in the
Factory installed in the Model 7140 FPGA, Core 430
Model 7140-430. A multiplexer in front of the core
creates a flexible, very high-channel count receiver system
allows data to be sourced from either A/D converter
in a small footprint.
A or B. At the output, a multiplexer allows the 7140-
Unlike classic channelizer methods, the Pentek 430 430 to route either the output of the GC4016 or the
core allows for completely independent programmable Core 430 DDC to the PCI Bus.
tuning of each individual channel with 32-bit resolution
In addition to the DDC outputs, data from both
as well as filter characteristics comparable to many
A/D channels are presented to the PCI Bus at a rate
conventional ASIC DDCs.
equal to the A/D clock rate divided by any integer value
Added flexibility comes from programmable global between 1 and 4096. A TI DAC5686 digital upconverter
decimation settings ranging from 1024 to 8192 in steps and dual D/A accepts baseband real or complex data streams
of 256, and 18-bit user programmable FIR decimating from the PCI Bus with signal bandwidths up to 40 MHz.
filter coefficients for the DDCs. Default DDC filter
Versions of the 7140-430 are also available as a PCI
coefficient sets are included with the core for all possible
board (Model 7640-430), 6U cPCI (Models 7240-430
decimation settings.
and 7240D-430 dual density), or 3U cPCI (Model
Core 430 utilizes a unique method of channelization. 7340-430). All these products have similar features.
It differs from others in that the channel center frequen-
22
Products
Multiband Transceivers with Virtex-II Pro FPGA
Model 7141 PMC/XMC ● Model 7241 6U cPCI ● Model 7341 3U cPCI

Model 7641 PCI ● Model 7741 Full-length PCIe ● Model 7841 Half-length PCIe
Sample
TIMING BUS XTL

LVDS Clock A GENERATOR A OSC A RF RF RF XFORMR RF XFORMR
XFORMR XFORMR
LVDS Sync A
Clock/Sync/Gate 16-bit D/A 16-bit D/A
LVDS Gate A SYNC Bus A LTC2255
AD6645 LTC2255
AD6645 DAC5686
TTL Gate/ INTERRUPTS 105
125 MHz 105
125 MHz DIGITAL UPCONVERTER
Trigger & CONTROL Clock/Sync/Gate 14-BIT
14-bit A/D
A/D 14-BIT
14-bit A/D
A/D
Bus B
TTL Sync
14 14 GC4016 32
LVDS Gate B 4-CHANNEL
16
DIGITAL FLASH
16
LVDS Sync B RECEIVER 16 MB
16 24
TIMING BUS XTL 14
LVDS Clock B
16
GENERATOR B OSC B
VIRTEX-II Pro FPGA
FRONT
PANEL To All XC2VP50
Sample
CONNECTOR Sections Control/ DSP – Channelizer – Digital Delay – Demodulation – Decoding – Control – etc.
Clock B In
Status
Model 7141 32 32 32
64 64
DDR DDR DDR
PMC/XMC
SDRAM SDRAM SDRAM PCI 2.2 INTERFACE P15 XMC P4 PMC
128 MB 128 MB 256 MB (64 Bits / 66 MHz) VITA 42.0 FPGA I/O
(Serial RapidIO, (Option –104)
PCI BUS
PCI-Express, etc.)
(64 Bits / 66 MHz)
Figure 34
The Model 7141 PMC/XMC module combines baseband signals, developed using Pentek’s GateFlow
both receive and transmit capabilities with a high- and ReadyFlow development tools.
performance Virtex II-Pro FPGA and supports the
The module includes a TI/GC4016 quad digital
VITA 42 XMC standard with optional switched fabric
downconverter along with a TI DAC5686 digital
interfaces for high-speed I/O.
upconverter with dual D/A converters.
The front end of the module accepts two RF inputs
Each channel in the downconverter can be set with
and transformer-couples them into two 14-bit A/D
an independent tuning frequency and bandwidth. The
converters running at 125 MHz. The digitized output
upconverter translates a real or complex baseband signal to
signals pass to a Virtex-II Pro FPGA for signal process-
any IF center frequency from DC to 160 MHz and can
ing or routing to other module resources.
deliver real or complex (I + Q) analog outputs through
These resources include a quad digital down- its two 16-bit D/A converters. The digital upconverter
converter, a digital upconverter with dual D/A converters, can be bypassed for two interpolated D/A outputs with
512 MB DDR SDRAM delay memory and the PCI sampling rates to 500 MHz.
bus. The FPGA also serves as a control and status
Versions of the 7141 are also available as a PCIe
engine with data and programming interfaces to each of
full-length board (Models 7741 and 7741D dual density),
the on-board resources. Factory-installed FPGA functions
PCIe half-length board (Model 7841), PCI board
include data multiplexing, channel selection, data packing,
(Model 7641), 6U cPCI (Models 7241 and 7241D
gating, triggering, and SDRAM memory control.
dual density), and 3U cPCI (Model 7341).
In addition to acting as a simple transceiver, the
Model 7141-703 is a conduction-cooled version.
module can perform user-defined DSP functions on the
23
Products
Transceivers with Dual Wideband DDC and Interpolation Filter Installed Cores
Model 7141-420 PMC/XMC ● Model 7241-420 6U cPCI ● Model 7341-420 3U cPCI

Model 7641-420 PCI ● Model 7741-420 Full-length PCIe ● Model 7841-420 Half-length PCIe
RF LTC2255
AD6645
CH A DDC C 128 MB DDR
125
105 MHz
RF In XFORMR DDC D SDRAM
14-bit A/D
MEMORY
D/A A
CONTROL 128 MB DDR
WIDEBAND DDC CORE D/A B & SDRAM
A/D A DATA ROUTING
RF LTC2255
AD6645
CH B A/D B 256 MB DDR
125
105 MHz
RF In XFORMR SDRAM
14-bit A/D
A/D A
WIDEBAND MEM W
A/D B M
DIGITAL FIFO
DDC A U
DOWNCONVERTR A
X MEM W
DDC B DECIMATION: 2 – 64
XTAL MEMORY FIFO
Sample OSC A MEMORY
A B C D A/D A A/D A PCI BUS
Clock A In
WIDEBAND FIFO 64 bit /
MUX A/D B M
CLOCK & DIGITAL 66 MHz
Clock/Sync DDC A U A/D B
SYNC GC4016 DIGITAL DOWNCONVERTR A
Bus X FIFO
GENERATOR DOWNCONVERTR DDC B DECIMATION:.2 – 64
WB DDC A
Sample DDC A
A B C D DDC A MUX PCI 2.2
Clock B In FIFO
XTAL WB DDC B INTERFACE
OSC B DDC B
DDC B MUX
FIFO
DDC C
FIFO
DDC D
RF 16-bit FIFO
CH A MEMORY
500 MHZ
RF Out XFORMR DAC 5686 MUX D/A A FIFO D/A A
D/A CIC CFIR
DIGITAL MEMORY FIFO
16-bit UPCONVERTER FILTER FILTER
CH B RF MUX D/A B FIFO D/A B
500 MHZ
RF Out XFORMR FIFO
D/A
INTERPOLATION CORE
XC2VP50
Figure 35
The Pentek IP Core 420 includes a dual high- The decimation settings of 2, 4, 8, 16, 32, and 64
performance wideband DDC and an interpolation filter. provide output bandwidths from 40 MHz down to 1.25
Factory-installed in the Model 7141 FPGA, they extend MHz for an A/D sampling of 100 MHz. A multiplexer
the range of both the GC4016 ASIC DDC and the in front of the Core 420 DDCs allows data to be sourced
DAC5686 DUC. from either the A/Ds or the GC4016, extending the
maximum cascaded decimation range to 1,048,576.
Each of the core 420 DDCs translates any frequency
band within the input bandwidth range down to zero The interpolation filter included in the 420 Core,
frequency. A complex FIR low pass filter removes any out- expands the interpolation factor from 2 to 32,768
of-band frequency components. An output decimator and programmable in steps of 2, and relieves the host
formatter deliver either complex or real data. An input gain processor from performing upsampling tasks. Including
block scales both I and Q data streams by a 16-bit gain the DUC, the maximum interpolation factor is 32,768
term. which is comparable to the maximum decimation of the
GC4016 narrowband DDC.
The mixer utilizes four 18x18-bit multipliers to
handle the complex inputs from the NCO and the Versions of the 7141-420 are also available as a PCIe
complex data input samples. The FIR filter is capable of full-length board (Models 7741-420 and 7741D-420 dual
storing and utilizing up to four independent sets of density), PCIe half-length board (Model 7841-420), PCI
18-bit coefficients for each decimation value. These board (Model 7641-420), 6U cPCI (Models 7241-420 and
coefficients are user-programmable by using RAM 7241D-420 dual density), or 3U cPCI (Model 7341-420).
structures within the FPGA.
Model 7141-703-420 is a conduction-cooled version.
24
Products
Transceivers with 256-Channel Narrowband DDC Installed Core

RF LTC2255
AD6645
CH A MEM W
125
105 MHz
RF In XFORMR FIFO
14-bit A/D
MEM W
FIFO
256 CHANNEL DIGITAL DOWNCONVERTER BANK
LTC2255
AD6645 CORE
CH B RF
125
105 MHz
RF In XFORMR 1 DDC 1
14-bit A/D OUT A
Local Oscillator, Mixer, Filter DDC A
DDC A
FIFO
2 DDC 1
OUT B
MUX Local Oscillator, Mixer, Filter DDC B
XTAL DDC B
M M FIFO
Sample OSC A
A B C D U OUT C U
Clock A In PCI BUS
X X DDC C
DDC C 64 bit /
CLOCK & MUX 255 DDC 255 FIFO
Clock/Sync 66 MHz
SYNC GC4016 DIGITAL Local Oscillator, Mixer, Filter OUT D
Bus DDC D
GENERATOR DOWNCONVERTR . DDC D
Sample 256 DDC 256 FIFO
A B C D PCI 2.2
Clock B In Local Oscillator, Mixer, Filter
XTAL INTERFACE
INT
OSC B
RF 16-bit
CH A
500 MHZ D/A A
RF Out XFORMR DAC 5686
D/A FIFO
DIGITAL
16-bit UPCONVERTER D/A B
CH B RF
500 MHZ FIFO
RF Out XFORMR D/A XC2VP50
Figure 36
For applications that require many channels of cies need not be at fixed intervals, and are independently
narrowband downconverters, Pentek offers the GateFlow programmable to any value.
IP Core 430 256-channel digital downconverter bank.
Core 430 DDC comes factory installed in the Model
Factory installed in the Model 7141 FPGA, Core 430
7141-430. A multiplexer in front of the core allows data to be
creates a flexible, very high-channel count receiver
sourced from either A/D converter A or B. At the output, a
system in a small footprint.
multiplexer allows the 7141-430 to route either the output of
Unlike classic channelizer methods, the Pentek 430 the GC4016 or the Core 430 DDC to the PCI Bus.
core allows for completely independent programmable
In addition to the DDC outputs, data from both
tuning of each individual channel with 32-bit resolution
A/D channels are presented to the PCI Bus at a rate equal
as well as filter characteristics comparable to many
to the A/D clock rate divided by any integer value between
conventional ASIC DDCs.
1 and 4096. A TI DAC5686 digital upconverter and dual
Added flexibility comes from programmable global D/A accepts baseband real or complex data streams from
decimation settings ranging from 1024 to 8192 in steps the PCI Bus with signal bandwidths up to 50 MHz.
of 256, and 18-bit user programmable FIR decimating
Versions of the 7141-430 are also available as a PCIe
filter coefficients for the DDCs. Default DDC filter
full-length board (Models 7741-430 and 7741D-430 dual
coefficient sets are included with the core for all possible
density), PCIe half-length board (Model 7841-430), PCI
decimation settings.
board (Model 7641-430), 6U cPCI (Models 7241-430 and
Core 430 utilizes a unique method of channelization. 7241D-430 dual density), or 3U cPCI (Model 7341-430).
It differs from others in that the channel center frequen- Model 7141-703-430 is a conduction-cooled version.
25
Products
Multichannel Transceivers with Virtex-4 FPGAs

Sample
Clock In
RF In RF In RF In RF In RF Out
TIMING BUS XTL

LVDS Clock A GENERATOR A OSC A RF RF RF RF RF
XFORMR XFORMR XFORMR XFORMR XFORMR
LVDS Sync A
Clock/Sync/Gate
LVDS Gate A SYNC Bus A 16-bit D/A
LTC2255 LTC2255 LTC2255 LTC2255
TTL Gate/ INTERRUPTS 125MHz 125MHz 125MHz 125MHz DAC5686
Trigger & CONTROL Clock/Sync/Gate 14-bit A/D 14-bit A/D 14-bit A/D 14-bit A/D
DIGITAL
Bus B
TTL Sync UPCONVERTER
14 14 14 14
LVDS Gate B
32
LVDS Sync B
LVDS Clock B TIMING BUS XTL VIRTEX-4 FPGA

GENERATOR B OSC B XC4VSX55
DSP – Channelizer – Digital Delay – Demodulation – Decoding – Control – etc.
To All Control/
Sections Status LOCAL HI-SPEED
32 32 32 64 32 32 32
DDR 2 DDR 2 DDR 2 BUS BUSES
SDRAM SDRAM SDRAM VIRTEX-4 FPGA
256 MB 256 MB 256 MB XC4VFX60 or XC4VFX100
Model 7142 PCI 2.2 SERIAL
PMC/XMC INTERFACE INTERFACE
PCI BUS
64
(64 Bits / 66 MHz)
P15 XMC P4 PMC

VITA 42.0 FPGA I/O
(Option –104)
Figure 37
The Model 7142 is a Multichannel PMC/XMC A 9-channel DMA controller and 64 bit / 66 MHz PCI
module. It includes four 125 MHz 14-bit A/D convert- interface assures efficient transfers to and from the module.
ers and one upconverter with a 500 MHz 16-bit D/A
A high-performance 160 MHz IP core wideband digital
converter to support wideband receive and transmit
downconverter may be factory-installed in the first FPGA.
communication channels.
Two 4X switched serial ports, implemented with the
Two Xilinx Virtex-4 FPGAs are included: an
Xilinx Rocket I/O interfaces, connect the second FPGA
XC4VSX55 or LX100 and an XC4VFX60 or FX100.
to the XMC connector with two 2.5 GB/sec data links
The first FPGA is used for control and signal processing
to the carrier board.
functions, while the second one is used for implement-
ing board interface functions including the XMC interface. A dual bus system timing generator allows separate
clocks, gates and synchronization signals for the A/D
It also features 768 MB of SDRAM for implementing
and D/A converters. It also supports large, multichannel
up to 2.0 sec of transient capture or digital delay memory
applications where the relative phases must be preserved.
for signal intelligence tracking applications at 125 MHz.
Versions of the 7142 are also available as a PCIe full-
A 16 MB flash memory supports the boot code for
length board (Models 7742 and 7742D dual density),
the two on-board IBM 405 PowerPC microcontroller
cores within the FPGA.
(Model 7642), 6U cPCI (Models 7242 and 7242D dual
density), and 3U cPCI (Model 7342).
26
Products
Transceivers with Four Multiband DDCs and Interpolation Filter Installed Cores

RF LTC2255
AD6645
CH A A/D A 256 MB DDR
125
105 MHz
RF In XFORMR A/D B SDRAM
14-bit A/D
A/D C MEMORY
256 MB DDR
A/D D CONTROL &
LTC2255 SDRAM
RF DATA ROUTING
CH B
125 MHz A/D A D/A
RF In XFORMR 256 MB DDR
14-bit A/D A/D B DIGITAL DIGITAL
M SDRAM
DOWNCONVERTR A DOWNCONVERTR A
A/D C U
STAGE 1 STAGE 2
A/D D X
RF LTC2255 DECIMATION: 2 – 256 DECIMATION: 1 – 256
CH C
125 MHz
RF In XFORMR A/D A MEM W
14-bit A/D
A/D B DIGITAL DIGITAL FIFO
M
DOWNCONVERTR B DOWNCONVERTR B
A/D C U MEM W
LTC2255 STAGE 1 STAGE 2
RF A/D D X FIFO
CH D DECIMATION: 2 – 256 DECIMATION: 1 – 256
125 MHz A/D A PCI BUS
RF In XFORMR A/D A
14-bit A/D A/D A DDC A MUX 64 bit /
FIFO
DIGITAL DIGITAL A/D B 66 MHz
A/D B M
DOWNCONVERTR C DOWNCONVERTR
. C A/D B
A/D C U DDC B MUX
STAGE 1 STAGE 2 FIFO
A/D D X A/D C
DECIMATION: 2 – 256 DECIMATION: 1 – 256
Sample A/D C PCI 2.2
XTAL DDC C MUX
Clock In A/D A FIFO INTERFACE
CLOCK & OSC A A/D D
A/D B DIGITAL DIGITAL A/D D
SYNC M MUX
Clock/Sync DOWNCONVERTR D DOWNCONVERTR D DDC D
A/D C U FIFO
Bus GENERATOR XTAL STAGE 1 STAGE 2
A/D D X
OSC B DECIMATION: 2 – 256 DECIMATION: 1 – 256
DIGITAL DOWNCONVERTER CORE
16-bit
500 MHZ
16-bit
D/A DAC 5686 MEMORY
RF CIC CFIR
RF Out 500 MHZ DIGITAL MUX D/A FIFO D/A
XFORMR FILTER FILTER
D/A UPCONVERTER FIFO
INTERPOLATION CORE XC4VSX55
Figure 38
The Pentek IP Core 428 includes four high- Four identical Core 428 DDCs are factory installed
performance multiband DDCs and an interpolation in the 7142-428 FPGA. An input multiplexer allows
filter. Factory-installed in the Model 7142 FPGA, any DDC to independently select any of the four A/D
they add DDCs to the Model 7142 and extend the sources. The overal decimation range from 2 to 65,536,
range of its DAC5686 DUC. programmable in steps of 1, provides output bandwidths
from 50 MHz down to 1.52 kHz for an A/D sampling
The Core 428 downconverter translates any frequency
rate of 125 MHz and assuming an 80% filter.
band within the input bandwidth range down to zero
frequency. The DDCs consist of two cascaded decimat- The Core 428 interpolation filter increases the
ing FIR filters. The decimation of each DDC can be set sampling rate of real or complex baseband signals by a
independently. After each filter stage is a post filter gain factor of 16 to 2048, programmable in steps of 4, and
stage. This gain may be used to amplify small signals relieves the host processor from performing upsampling
after out-of-band signals have been filtered out. tasks. The interpolation filter can be used in series with
the DUC’s built-in interpolation, creating a maximum
The NCO provides over 108 dB spurious-free
interpolation factor of 32,768.
dynamic range (SFDR). The FIR filter is capable of
storing and utilizing two independent sets of 18-bit Versions of the 7142-428 are also available as a PCIe
coefficients. These coefficients are user-programmable by full-length board (Models 7742-428 and 7742D-428 dual
using RAM structures within the FPGA. NCO tuning density), PCIe half-length board (Model 7842-428), PCI
frequency, decimation and filter coefficients can be board (Model 7642-428), 6U cPCI (Models 7242-428 and
changed dynamically. 7242D-428 dual density), or 3U cPCI (Model 7342-428).
27
Products
256-Channel DDC Installed Core with Quad 200 MHz, 16-bit A/D
Model 7151 PMC ● Model 7251 6U cPCI ● Model 7351 3U cPCI

RF ADS5485
AD6645
CH A
200
105 MHz
RF In XFORMR
16-bit
14-bit A/D
ADS5485
CH B RF
200 MHz
RF In XFORMR
16-bit A/D
RF ADS5485
CH C
200 MHz A/D A
RF In XFORMR
16-bit A/D A/D B DIGITAL A/D A
M MUX
DOWNCONVERTR I&Q DDC BANK 1 FIFO
A/D C U
BANK 1: CH 1 - 64
A/D D X
RF ADS5485 DECIMATION: 128 - 1024
CH D
200 MHz PCI BUS
RF In XFORMR A/D A
16-bit A/D A/D B 64 bit /
A/D B DIGITAL A/D B
M MUX 66 MHz
DOWNCONVERTR I&Q DDC BANK 2 FIFO
A/D C U .
BANK 2: CH 65 - 128
A/D D X
DECIMATION: 128 - 1024
PCI 2.2
A/D A
A/D C INTERFACE
Sample A/D B DIGITAL A/D C
M MUX
Clock In DOWNCONVERTR I&Q DDC BANK 3 FIFO
A/D C U
TIMING BUS BANK 3: CH 129 - 192
A/D D X
GENERATOR DECIMATION: 128 - 1024
PPS In
A/D A
Clock / Gate / DIGITAL A/D D
A/D B M A/D D
TTL In Sync / PPS DOWNCONVERTR I&Q DDC BANK 4 MUX
A/D C U FIFO
BANK 4: CH 193 - 256
A/D D X
DECIMATION: 128 - 1024
Sync Bus
XTAL DIGITAL DOWNCONVERTER CORE
OSC
XC5VSX95T
Figure 39
The Model 7151 PMC module is a 4-channel high- supporting as many as four different output bandwidths
speed digitizer with a factory-installed 256-channel for the board.
DDC core. The front end of the module accepts four
The decimating filter for each DDC bank accepts a
RF inputs and transformer-couples them into four
unique set of user-supplied 18-bit coefficients. The 80%
16-bit A/D converters running at 200 MHz. The
default filters deliver an output bandwidth of 0.8*ƒs/N,
digitized output signals pass to a Virtex-5 FPGA for
where N is the decimation setting. The rejection of
routing, formatting and DDC signal processing.
adjacent-band components within the 80% output band-
The Model 7151 employs an advanced FPGA-based width is better than 100 dB.
digital downconverter engine consisting of four identical
Each DDC delivers a complex output stream
64-channel DDC banks. Four independently controllable
consisting of 24-bit I + 24-bit Q samples. Any number
input multiplexers select one of the four A/Ds as the
of channels can be enabled within each bank, selectable
input source for each DDC bank. Each of the 256 DDCs
from 0 to 64. Each bank includes an output sample
has an independent 32-bit tuning frequency setting.
interleaver that delivers a channel-multiplexed stream for
All of the 64 channels within a bank share a common all enabled channels within the bank.
decimation setting that can range from 128 to 1024,
Versions of the 7151 are also available as a PCIe
programmable in steps of 64. For example, with a sampling
full-length board (Models 7751 and 7751D dual density),
rate of 200 MHz, the available output bandwidths
range from 156.25 kHz to 1.25 MHz. Each 64-channel
bank can have its own unique decimation setting
density), or 3U cPCI (Model 7351).
28
Products

RF ADS5485
AD6645
CH A
200
105 MHz
RF In XFORMR
16-bit
14-bit A/D
RF ADS5485
CH B
200 MHz
RF In XFORMR DIGITAL DOWNCONVERTER CORE 8x4
16-bit A/D SUM
CHANNEL
A/D A SUMMATION A/D B
A/D B DIGITAL MUX A/D A
ADS5485 M
CH C RF DOWNCONVERTR I & Q BANK 1 FIFO
200 MHz A/D C U
RF In XFORMR BANK 1: CH 1 - 8
16-bit A/D A/D D X
DEC: 16 - 8192 POWER
METER &
THRESHOLD
RF ADS5485 A/D A DETECT
CH D
200 MHz DIGITAL A/D B PCI BUS
RF In XFORMR A/D B M A/D B
16-bit A/D DOWNCONVERTR I & Q BANK 2 MUX 64 bit /
A/D C U FIFO
BANK 2: CH 9 - 16 66 MHz
A/D D X
DEC: 16 - 8192 POWER.
METER &
THRESHOLD PCI 2.2
A/D A DETECT
A/D C INTERFACE
M
Clock In DOWNCONVERTR I & Q BANK 3 MUX FIFO
A/D C U
TIMING BUS BANK 3: CH 17 - 24
A/D D X
GENERATOR DEC: 16 - 8192 POWER
PPS In METER &
THRESHOLD
Clock / Gate /
A/D A DETECT
TTL In Sync / PPS DIGITAL A/D D
A/D B M A/D D
DOWNCONVERTR I & Q BANK 4 MUX FIFO
A/D C U
BANK 4: CH 25 - 32
A/D D X POWER
Sync Bus DEC: 16 - 8192
METER &
XTAL THRESHOLD
OSC DETECT
XC5VSX95T
Figure 40
The Model 7152 PMC module is a 4-channel high- have its own unique decimation setting supporting as
speed digitizer with a factory-installed 32-channel DDC many as four different output bandwidths for the board.
core. The front end of the module accepts four RF
The decimating filter for each DDC bank accepts a unique
inputs and transformer-couples them into four
set of user-supplied 18-bit coefficients. The 80% default filters
deliver an output bandwidth of 0.8*ƒs/N, where N is the
decimation setting. The rejection of adjacent-band components
within the 80% output band-width is better than 100 dB.
The Model 7152 employs an advanced FPGA-based
Each DDC delivers a complex output stream consist-
ing of 24-bit I + 24-bit Q samples. Any number of channels
8-channel DDC banks. Four independently controllable
can be enabled within each bank, selectable from 0 to 8.
Each bank includes an output sample interleaver that
input source for each DDC bank. Each of the 32 DDCs
delivers a channel-multiplexed stream for all enabled
has an independent 32-bit tuning frequency setting.
channels within the bank. Gain and phase control, power
All of the 8 channels within a bank share a common meters and threshold detectors are included.
decimation setting that can range from 16 to 8192,
programmable in steps of 8. For example, with a sampling
length board (Models 7752 and 7752D dual density), PCIe
rate of 200 MHz, the available output bandwidths range
half-length board (Model 7852), PCI board (Model 7652),
from 19.53 kHz to 10.0 MHz. Each 8-channel bank can
6U cPCI (Models 7252 and 7252D dual density), or 3U
cPCI (Model 7352).
29
Products

RF ADS5485
AD6645
CH A
200
105 MHz
RF In XFORMR
16-bit
14-bit A/D
RF ADS5485
CH B DIGITAL DOWNCONVERTER CORE
200 MHz
RF In XFORMR 4
16-bit A/D SUM
CHANNEL
A/D A SUMMATION A/D B
A/D B DIGITAL MUX A/D A
ADS5485 M
CH C RF DOWNCONVERTR I & Q DDC 1 FIFO
200 MHz A/D C U
RF In XFORMR CH 1
16-bit A/D A/D D X
DEC: 2 - 256 POWER
METER &
THRESHOLD
RF ADS5485 A/D A DETECT
CH D
200 MHz DIGITAL A/D B PCI BUS
RF In XFORMR A/D B M A/D B
16-bit A/D DOWNCONVERTR I & Q DDC 2 MUX 64 bit /
A/D C U FIFO
CH 2 66 MHz
A/D D X
DEC: 2 - 256 POWER.
METER &
THRESHOLD PCI 2.2
A/D A DETECT
A/D C INTERFACE
M
Clock In DOWNCONVERTR I & Q DDC 3 MUX FIFO
A/D C U
TIMING BUS CH 3
A/D D X
GENERATOR DEC: 2 - 256 POWER
PPS In METER &
THRESHOLD
Clock / Gate /
A/D A DETECT
TTL In Sync / PPS DIGITAL A/D D
A/D B M A/D D
DOWNCONVERTR I & Q DDC 4 MUX FIFO
A/D C U
CH 4
A/D D X POWER
Sync Bus DEC: 2 - 256
METER &
XTAL THRESHOLD
OSC DETECT
XC5VSX50T
Figure 41
The Model 7153 PMC/XMC module is a 4-channel rejection of adjacent-band components within the 80%
high-speed digitizer with a factory-installed 4-channel output band-width is better than 100 dB.
DDC core. The front end of the module accepts four
Each DDC delivers a complex output stream consist-
RF inputs and transformer-couples them into four
ing of 24-bit I + 24-bit Q samples. Any number of channels
can be enabled, selectable from 0 to 4. Each channel
includes an output sample interleaver that delivers a
channel-multiplexed stream for all enabled channels.
The Model 7153 employs an advanced FPGA-based
Gain and phase control, power meters and threshold
detectors are included for applications such as direction
multiband DDC banks. Four independently controllable
finding and beamforming.
input source for each DDC bank. Each of the 4 DDCs This product is also available in individually tunable
has an independent 32-bit tuning frequency setting. two DDC format with independent decimation range
of 2 to 65536.
All four DDCs have a decimation setting that can
range from 2 to 256, programmable independenly in Versions of the 7153 are also available as a PCIe
steps of 1. The decimating filter for each DDC bank full-length board (Models 7753 and 7753D dual density),
accepts a unique set of user-supplied 18-bit coefficients. PCIe half-length board (Model 7853), PCI board
The 80% default filters deliver an output bandwidth of (Model 7653), 6U cPCI (Models 7253 and 7253D
0.8*ƒs/N, where N is the decimation setting. The dual density), or 3U cPCI (Model 7353).
30
Products
Dual SDR Transceivers with 400 MHz A/D, 800 MHz D/A, and Virtex-5 FPGAs

RF In RF In RF Out RF Out
RF RF RF RF
XFORMR XFORMR XFORMR XFORMR
Sample Clock In
A/D Clock Bus ADS5474 ADS5474
800 MHz 800 MHz
PPS In TIMING BUS 400 MHz 400 MHz 16-bit D/A 16-bit D/A
GENERATOR 14-bit A/D 14-bit A/D
D/A Clock Bus
TTL Gate / Trig Clock/ Sync / DIGITAL UPCONVERTER
TTL Sync / PPS
Gate / PPS
Sample Clk 14 14
Sync Clk 32
Gate A Control/
Gate B Status
Sync PROCESSING FPGA
PPS VCXO To All VIRTEX –5: LX50T, SX50T, SX95T or FX100T
Sections LVDS GTP GTP GTP
Timing Bus
32 32 16
64 4X 4X 4X
DDR 2 DDR 2
FLASH
SDRAM SDRAM GTP
32 MB
512 MB 512 MB
INTERFACE FPGA
VIRTEX-5: LX30T, SX50T or FX70T
Model 7156
LVDS PCI-X GTP
PMC/XMC
32 32 64 4X
P4 PMC PCI-X BUS P15 XMC
FPGA (64 Bits VITA 42.x
I/O 100 MHz) (PCIe, etc.)
Figure 42
Model 7156 is a dual high-speed data converter A high-performance IP core wideband DDC may be
suitable for connection as the HF or IF input of a factory-installed in the processing FPGA.
communications system. It features two 400 MHz 14-bit
A 5-channel DMA controller and 64 bit/100 MHz PCI-
A/Ds, a DUC with two 800 MHz 16-bit D/As, and
X interface assures efficient transfers to and from the module.
two Virtex-5 FPGAs. Model 7156 uses the popular
PMC format and supports the VITA 42 XMC standard Two 4X switched serial ports implemented with the
for switched fabric interfaces. Xilinx Rocket I/O interfaces, connect the FPGA to the
XMC connector with two 2.5 GB/sec data links to the
The Model 7156 architecture includes two Virtex-5
carrier board.
FPGAs. The first FPGA is used primarily for signal
processing while the second one is dedicated to board A dual bus system timing generator allows separate
interfaces. All of the board’s data and control paths are clocks, gates and synchronization signals for the A/D
accessible by the FPGAs, enabling factory installed and D/A converters. It also supports large, multichannel
functions such as data multiplexing, channel selection, data applications where the relative phases must be preserved.
packing, gating, triggering and SDRAM memory control.
Two independent 512 MB banks of DDR2 SDRAM length board (Models 7756 and 7756D dual density),
are available to the signal processing FPGA. Built-in PCIe half-length board (Model 7856), PCI board
memory functions include an A/D data transient capture (Model 7656), 6U cPCI (Models 7256 and 7256D dual
mode with pre- and post-triggering. All memory banks density), or 3U cPCI (Model 7356). All these products
can be easily accessed through the PCI-X interface. have similar features.
31
Products
Dual SDR Transceivers with 500 MHz A/D, 800 MHz D/A, and Virtex-5 FPGAs

RF In RF In RF Out RF Out
RF RF RF RF
XFORMR XFORMR XFORMR XFORMR
Sample Clock /
Reference Clock In A/D Clock Bus ADS5463 ADS5463
800 MHz 800 MHz
PPS In TIMING BUS 500 MHz 500 MHz 16-bit D/A 16-bit D/A
GENERATOR 12-bit A/D 12-bit A/D
D/A Clock Bus
TTL Gate / Trig DIGITAL UPCONVERTER
Clock/ Sync /
TTL Sync / PPS Gate / PPS
Sample Clk 14 14
Sync Clk 32
Gate A Control/
Gate B Status
Sync PROCESSING FPGA
PPS VCXO To All VIRTEX –5: LX50T, LX155T, SX50T, SX95T or FX100T
Sections LVDS GTP GTP GTP
Timing Bus
32 32 16
64 4X 4X 4X
DDR 2 DDR 2
FLASH
SDRAM SDRAM GTP
32 MB
256 MB 256 MB
INTERFACE FPGA
Model 7158 VIRTEX-5: LX30T, SX50T or FX70T
PMC/XMC GTP
LVDS PCI-X
32 32 64 4X
P4 PMC PCI-X BUS P15 XMC
FPGA (64 Bits VITA 42.x
I/O 100 MHz) (PCIe, etc.)
Figure 43
Model 7158 is a dual high-speed data converter A 5-channel DMA controller and 64 bit / 100 MHz
suitable for connection as the HF or IF input of a PCI-X interface assures efficient transfers to and from the
communications system. It features two 500 MHz 12-bit module.
A/Ds, a digital upconverter with two 800 MHz 16-bit
Two 4X switched serial ports implemented with the
D/As, and two Virtex-5 FPGAs. Model 7158 uses the
Xilinx Rocket I/O interfaces, connect the FPGA to the
popular PMC format and supports the VITA 42 XMC
XMC connector with two 2.5 GB/sec data links to the
standard for switched fabric interfaces.
carrier board.
The Model 7158 architecture includes two Virtex-5
A dual bus system timing generator allows separate
FPGAs. The first FPGA is used primarily for signal
clocks, gates and synchronization signals for the A/D
processing while the second one is dedicated to board
and D/A converters. It also supports large, multichannel
interfaces. All of the board’s data and control paths are
applications where the relative phases must be preserved.
accessible by the FPGAs, enabling factory installed
functions such as data multiplexing, channel selection, data Versions of the 7158 are also available as a PCIe full-
packing, gating, triggering and SDRAM memory control. length board (Models 7758 and 7758D dual density),
Two independent 256 MB banks of DDR2 SDRAM
are available to the signal processing FPGA. Built-in
density), or 3U cPCI (Model 7358). All these products
memory functions include an A/D data transient capture
have similar features.
mode with pre- and post-triggering. All memory banks
can be easily accessed through the PCI-X interface.
32
Products
215 MHz, 12-bit A/D with Wideband DDCs - VME/VXS
Model 6821-422
LVDS
RF Input I/O
215 MHz
50 ohms
12-Bit A/D
AD9430 32 XILINX 32 32
128 MB FPDP-II
VIRTEX-II 128k Out A
Fs SDRAM FIFO
PRO FPGA Slot 1
Ext Clock In 32
50 ohms 16 MB 16 XC2VP50 32 FPDP-II
128k Out C
XTAL FLASH FIFO Slot 2
OSC 64 LVDS
I/O
Fs/2
Front 32 XILINX 32 32 FPDP-II
Panel CLOCK, SYNC 128 MB 128k
VIRTEX-II Out B
LVDS & TRIGGER SDRAM FIFO Slot 1
Timing PRO FPGA
GENERATOR 32 32 FPDP-II
Bus 16 MB 16 XC2VP50 128k
FIFO Out D
FLASH Slot 2
4x Switched 4x Switched
Control and Status Serial Fabric Serial Fabric
VME Slave Interface To All Sections 1.25 GB/sec 1.25 GB/sec
Model 6821
VMEbus VXS Switched Backplane
Figure 44
The Model 6821 is a 6U single slot board with the installed in one or both of the FPGAs to perform this
AD9430 12-bit, 215 MHz A/D converter. function.
Capable of digitizing input signal bandwidths up to Two 128 MB SDRAMs, one for each FPGA,
100 MHz, it is ideal for wideband applications includ- support large memory applications such as swinging
ing radar and spread spectrum communication systems. buffers, digital filters, DSP algorithms, and digital delay
lines for tracking receivers.
The sampling clock can be supplied either from a
front panel input or from an internal crystal oscillator. Either two or four FPDP-II ports connect the FPGAs
Data from the A/D converter flows into two Xilinx to external digital destinations such as processor boards,
Virtex-II Pro FPGAs where optional signal processing memory boards or storage devices.
functions can be performed. The size of the FPGAs can
A VMEbus interface supports configuration of the
range from the XC2VP20 to the XC2VP50.
FPGAs over the backplane and also provides data and
Because the sampling rate is well beyond conven- control paths for runtime applications. A VXS interface
tional ASIC digital downconverters, none are included is optionally available.
on the board.
This Model is available in commercial as well as
Instead, the Pentek GateFlow IP Core 422 Ultra conduction-cooled versions.
Wideband Digital Downconverter can be factory-
33
Products
Dual 215 MHz, 12-bit A/D with Wideband DDCs - VME/VXS
Model 6822-422
LVDS
RF Input I/O
215 MHz
50 ohms
12-Bit A/D
AD9430 32 XILINX 32 32 FPDP-II
128 MB 128k
VIRTEX-II Out A
SDRAM FIFO
PRO FPGA Slot 1
Fs LVDS Clock 16 XC2VP50 32 32
& Sync Bus 16 MB 128k FPDP-II
Ext Clock In Out C
50 ohms FLASH FIFO Slot 2
XTAL 64 LVDS
OSC CLOCK I/O
GEN
32
Fs/2 128 MB XILINX 32 32 FPDP-II
SDRAM VIRTEX-II 128k Out B
RF Input 215 MHz FIFO
50 ohms PRO FPGA Slot 1
12-Bit A/D 16 XC2VP50 32 32 FPDP-II
AD9430 16 MB 128k Out D
FLASH FIFO Slot 2
4x Switched 4x Switched
Control and Status Serial Fabric Serial Fabric
VME Slave Interface To All Sections 1.25 GB/sec 1.25 GB/sec
Model 6822
VMEbus VXS Switched Backplane
Figure 45
The Model 6822 is a 6U single slot VME board installed in one or both of the FPGAs to perform this
with two AD9430 12-bit 215 MHz A/D converters. function.
Capable of digitizing input signal bandwidths up to Two 128 MB SDRAMs, one for each FPGA,
100 MHz, it is ideal for wideband applications includ- support large memory applications such as swinging
ing radar and spread spectrum communication systems. buffers, digital filters, DSP algorithms, and digital delay
lines for tracking receivers.
The sampling clock can be supplied either from a
front panel input or from an internal crystal oscillator. Either two or four FPDP-II ports connect the FPGAs
Data from each A/D converter flows into a Xilinx to external digital destinations such as processor boards,
Virtex-II Pro FPGA where optional signal processing memory boards or storage devices.
functions can be performed. The size of the FPGAs can
A VMEbus interface supports configuration of the
range from the XC2VP20 to the XC2VP50.
FPGAs over the backplane and also provides data and
Because the sampling rate is well beyond conven- control paths for runtime applications. A VXS interface
tional ASIC digital downconverters, none are included is optionally available.
on the board.
This Model is available in commercial as well as
Instead, the Pentek GateFlow IP Core 422 Ultra conduction-cooled versions.
Wideband Digital Downconverter can be factory-
34
Products
Dual 2 GHz, 10-bit A/D with Very High-Speed DDCs - VME/VXS
Model 6826
RF INPUT
50 OHMS 2 GHz 10 4:1 40 2:1 80
32 32 FPDP-II
10-Bit A/D DEMUX DEMUX 128k
AT84AS008 AT84CS001 V4 FPGA FIFO 400 MB/sec
EXT Fs 64 32
512 MB 32 128k FPDP-II
CLOCK XILINX
INPUT DDR RAM FIFO 400 MB/sec
XTAL Fs/4 Fs/8 VIRTEX-II
64 PRO FPGA 16 16 MB
OSC 512 MB
Fs XC2VP70 FLASH
DDR RAM
RF INPUT 32 32
50 OHMS 2 GHz 10 4:1 40 2:1 80 128k FPDP-II
10-Bit A/D DEMUX DEMUX FIFO 400 MB/sec
AT84AS008 AT84CS001 V4 FPGA
32 32 FPDP-II
128k
Fs/4 Fs/8 FIFO 400 MB/sec
Fs/8 IN
Fs/8 OUT GATE 4x SWITCHED 4x SWITCHED
TRIGGER SERIAL FABRIC SERIAL FABRIC Model 6826
FPGA SYNC IN VME SLAVE 1.25 GB/SEC 1.25 GB/SEC
& SYNC
GATE A IN INTERFACE
VMEbus VXS SWITCHED BACKPLANE
GATE B IN
Figure 46
The Model 6826 is a 6U single slot VME board for the Model 6826 can be developed for a customer who
with two Atmel AT84AS008 10-bit 2 GHz A/D is interested in one.
converters.
The customer will be able to incorporate this core
Capable of digitizing input signals at sampling rates into the Model 6826 by ordering it as a factory-installed
up to 2 GHz, it is ideal for extremely wideband option.
applications including radar and spread spectrum
Two 512 MB or 1 GB SDRAMs, support large
communication systems. The sampling clock is an
memory applications such as swinging buffers, digital
externally supplied sinusoidal clock at a frequency from
filters, DSP algorithms, and digital delay lines for
200 MHz to 2 GHz.
tracking receivers.
Data from each of the two A/D converters flows
Either two or four FPDP-II ports connect the FPGA
into an innovative dual-stage demultiplexer that packs
to external digital destinations such as processor boards,
groups of eight data samples into 80-bit words for
memory boards or storage devices.
delivery to the Xilinx Virtex-II Pro XC2VP70 FPGA
at one eighth the sampling frequency. This advanced A VMEbus interface supports configuration of the
circuit features the Atmel AT84CS001 demultiplexer FPGA over the backplane and also provides data and
which represents a significant improvement over previous control paths for runtime applications. A VXS interface
technology. is optionally available.
Because the sampling rate is well beyond conven- This Model is also available in a single-channel
tional digital downconverters, none are included on the version and in commercial as well as conduction-cooled
board. A very high-speed digital downconverter IP core versions.
35
Products
2.2 GHz Clock, Sync and Gate Distribution Board
Model 6890 - VME

Front
Panel TTL / PECL Ch 1
Gate SELECTOR Ch 2
Enable LVPECL Ch 3 Front
GATE
CONTROL PROG BUFFER MUX BUFFER Ch 4 Panel
Front DELAY 1:2 2:1 Ch 5 Gate
1:8
Panel TTL / PECL REG Ch 6 Output
Gate SELECTOR Ch 7
Input Ch 8
Ch 1
Ch 2
Front POWER POWER Ch 3 Front
Panel SPLITTER SPLITTER Ch 4 Panel
Clock 1:2 BUFFER Ch 5 Clock
Input 1:8
1:2 Ch 6 Output
Ch 7
Ch 8
Front
Panel TTL / PECL Ch 1
Sync SELECTOR Ch 2
Enable REG LVPECL Ch 3 Front
SYNC BUFFER
PROG BUFFER MUX Ch 4 Panel
CONTROL
DELAY 1:2 2:1 Ch 5 Sync
Front 1:8
Panel TTL / PECL Ch 6 Output
Sync SELECTOR Ch 7
Input Ch 8
Model 6890
VME
Figure 47
Model 6890 Clock, Sync and Gate Distribution splitter feeds a 1:2 buffer which distributes the clock
Board synchronizes multiple Pentek I/O boards within a signal to both the gate and synchronization circuits.
system. It enables synchronous sampling and timing
The 6890 features separate inputs for gate/trigger
for a wide range of multichannel high-speed data
and sync signals with user-selectable polarity. Each of
acquisition, DSP and software radio applications. Up
these inputs can be TTL or LVPECL. Separate Gate
to eight boards can be synchronized using the 6890,
Enable and Sync Enable inputs allow the user to enable
each receiving a common clock of up to 2.2 GHz along
or disable these circuits using an external signal.
with timing signals that can be used for synchronizing,
triggering and gating functions. A programmable delay allows the user to make
timing adjustments on the gate and sync signals before
Clock signals are applied from an external source
they are sent to an LVPECL buffer. A bank of eight
such as a high performance sine wave generator. Gate
MMCX connectors at the output of each buffer delivers
and sync signals can come from an external source, or
signals to up to eight boards.
from one supported board set to act as the master.
A 2:1 multiplexer in each circuit allows the gate/
The 6890 accepts clock input at +10 dBm to +14 dBm
trigger and sync signals to be registered with the input
with a frequency range from 800 MHz to 2.2 GHz and
clock signal before output, if desired.
uses a 1:2 power splitter to distribute the clock. The first
output of this power splitter sends the clock signal to a Sets of input and output cables for two to eight
1:8 splitter for distribution to up to eight boards using boards are available from Pentek.
SMA connectors. The second output of the 1:2 power
36
Products
System Synchronizer and Distribution Board
Model 6891 - VME

Gate
Clock Sync Bus
Sync Output 1
Ch 1
Ch 2
Front Panel Gate
Ch 3
Gate Enable GATE Clock Sync Bus
Ch 4
GATE
LVPECL to Sync Bus Sync Output 2
PROG BUFFER MUX BUFFER Ch 5
CONTROL DELAY
Outputs 2-8
Front Panel 1:2 2:1 Ch 6
MUX 1:8 Gate
GateInput REG Ch 7
2:1 Ch 8 Clock Sync Bus
Sync Output 3
Ch 1 Gate
Ch 2 Clock Sync Bus
Ch 3 Sync Output 4
CLOCK
Front Panel LVPECL Ch 4
MUX to Sync Bus
Clock Input BUFFER Ch 5 Gate
2:1 Outputs 2-8
1:10
Ch 6 Clock Sync Bus
Ch 7 Sync Output 5
Ch 8
Gate
Clock Sync Bus
Ch 1 Sync Output 6
Front Panel Ch 2
Sync Enable REG Ch 3 Gate
SYNC PROG BUFFER MUX SYNC
LVPECL Ch 4 Clock Sync Bus
CONTROL DELAY 1:2 2:1 BUFFER
to Sync Bus
Front Panel Ch 5 Sync Output 7
MUX
Outputs 2-8
Sync Input Ch 6
1:8
2:1 Ch 7 Gate
Ch 8
Clock Sync Bus
Gate Output 8
Sync
Sync Bus Clock
Input Sync
Model 6891
VME
Figure 48
Model 6891 System Synchronizer and Distribution Clock signals can be applied from an external source
Board synchronizes multiple Pentek I/O modules within a such as a high performance sine-wave generator. Gate/trigger
system. It enables synchronous sampling and timing for a and sync signals can come from an external system source.
wide range of multichannel high-speed data acquisition, Alternately, a Sync Bus connector accepts LVPECL inputs
DSP and software radio applications. from any compatible Pentek products to drive the clock,
sync and gate/trigger signals.
Up to eight modules can be synchronized using the
6891, each receiving a common clock up to 500 MHz The 6891 provides eight front panel Sync Bus output
along with timing signals that can be used for synchroniz- connectors, compatible with a wide range of Pentek I/O
ing, triggering and gating functions. For larger systems, modules. The Sync Bus is distributed through ribbon
up to eight 6891’s can be linked together to provide cables, simplifying system design. The 6891 accepts clock
synchronization for up to 64 I/O modules producing input at +10 dBm to +14 dBm with a frequency range
systems with up to 256 channels. from 1 kHz to 800 MHz. This clock is used to register
all sync and gate/trigger signals as well as providing a
Model 6891 accepts three TTL input signals from
sample clock to all connected I/O modules.
external sources: one for clock, one for gate or trigger
and one for a synchronization signal. Two additional A programmable delay allows the user to make
inputs are provided for separate gate and sync enable signals. timing adjustments on the gate and sync signals before
they are sent to an LVPECL buffer for output through
the Sync Bus connectors.
37
Products
Multifrequency Clock Synthesizer

Clock Out
Reference CLOCK
1
In SYNTHESIZER
QUAD AND JITTER
CLEANER Clock Out
VCXO 2
A A
Clock Out
CLOCK 3
SYNTHESIZER
AND JITTER Clock Out
QUAD
CLEANER 4
VCXO
B B
Clock Out
5
CLOCK
SYNTHESIZER Clock Out
QUAD AND JITTER 6
VCXO CLEANER
C C Clock Out
7
CLOCK
SYNTHESIZER
QUAD AND JITTER
VCXO CLEANER Clock Out
D D 8
Model 7190 NON-VOLATILE
CONFIGURATION
PMC Control MEMORY
PCI INTERFACE
PCI BUS
32 (32 Bits / 66 MHz)
Figure 49
Model 7190 generates up to eight synthesized clock The five clock output signals from each of the four
signals suitable for driving A/D and D/A converters in CDC7005s are joined into five clock buses. Each output
high-performance real-time data acquisition and software can be independently enabled to drive each bus, thereby
radio systems. The clocks offer exceptionally low phase allowing any combination of output signals from the four
noise and jitter to preserve the signal quality of the data CDC7005s.
converters. These clocks are synthesized from an input
Eight front panel SMC connectors supply synthesized
reference signal using phase-locked oscillators.
clock outputs driven from the five clock buses, as shown
The 7190 uses four Texas Instruments CDC7005 in the block diagram. This supports a single identical
clock synthesizer and jitter cleaner devices. Each device clock to all eight outputs or five different clocks to various
includes phase-locking circuitry that locks the frequency outputs; numerous other combinations are possible.
of its associated quad VCXO (Voltage Controlled Crystal
The 7190 is equipped with a non-volatile memory.
Oscillator) to the input reference clock. This reference is a 5
Once configured, the settings return to the saved
or 10 MHz signal supplied to a front panel SMC connec-
configuration upon power up.
tor. Each quad VCXO is programmed to generate one of
four base frequencies. Versions of the 7190 are also available as a PCIe full-
length board (Models 7790 and 7790D dual density),
Each CDC7005 generates five output signals. Each
signal is independently programmable as a submultiple of
the associated VCXO base frequency using divisors of 1, 2,
density), or 3U cPCI (Model 7390).
4, 8 or 16.
38
Products
Clock and Sync Generator for I/O Modules
Model 9190 - Rack-mount
Model 9190
LVDS To
DIFF. Module
DRIVERS No. 1
Timing
From Signals Timing
Module LVDS Signals To
DIFF. LVDS
Master RECEIVER DIFF. Module
Source DRIVERS No. 2
Timing
Signals Multiplexer
Front
Switches
Panel LVDS To
LINE Clock
Input DIFF. Module
RCVRS DRIVERS
SMA Ext. Clock No. 80
Connectors
Front
OPTIONAL Panel
INTERNAL LINE
DRIVERS Output
OSCILLATOR
SMA
Connectors
Figure 50
Model 9190 Clock and Sync Generator synchronizes Buffered versions of the clock and five timing
multiple Pentek I/O modules within a system to provide signals are available as outputs on the 9190’s front panel
synchronous sampling and timing for a wide range of SMA connectors.
high-speed, multichannel data acquisition, DSP and
Model 9190 is housed in a line-powered, 1.75 in.
software radio applications. Up to 80 I/O modules can
high metal chassis suitable for mounting in a standard
be driven from the Model 9190, each receiving a
19 in. equipment rack, either above or below the cage
common clock and up to five different timing signals
holding the I/O modules.
which can be used for synchronizing, triggering and
gating functions. Separate cable assemblies extend from openings in
the front panel of the 9190 to the front panel clock and
Clock and timing signals can come from six front
sync connectors of each I/O module. Mounted between
panel SMA user inputs or from one I/O module set to act
two standard rack-mount card cages, Model 9190 can
as the timing signal master. (In this case, the master I/O
drive a maximum of 80 clock and sync cables, 40 to the
module will not be synchronous with the slave modules
card cage above and 40 to the card cage below. Fewer
due to delays through the 9190.) Alternately, the master
cables may be installed for smaller systems.
clock can come from a socketed, user-replaceable crystal
oscillator within the Model 9190.
39
Products
Real-Time Recording and Playback Transceiver System
Model RTS 2504 Host

PC
Front
Front Panel ETHERNET
JBOD Disk Array Panel
Fibre Channel
Fibre
160 MB/sec Channel 100 baseT
Adapter & ETHERNET
DMA
PENTEK Model 7141-420 PMC Controller
(64 bits / 66 MHz)

VME64
VME
CH A
IN PMC Site UNIV II
125 MHz 64
PCI 2.2 64
(64 bits / 33 MHz)

14bit A/D INTERFACE 64 bits
PCI Bus 0
64 bits/ 66 MHz 66 MHz
CH B
IN
PCI Bus 1
125 MHz 32 128 MB
14bit A/D SDRAM
XILINX 32 128 MB
CLK A VIRTEX-II SDRAM
VIRTEX-II FPGA
DUAL
Pro 256 MB
PCI Bridge
CLK B TIMING 32
FPGA SDRAM
& DMA
BUS SDRAM
CLOCK GEN 1 GB
& SYNC XC2VP50
32 16 MB Dual PCI
BUS FLASH Node
CH A
OUT
DMA,
500 MHz &
GC4016
16bit D/A 320
QUAD
Memory FLASH
CH B A
OUT
MHz B
DDC Controller
500 MHz DUC C
D
16bit D/A
VIRTEX-II FPGA
PCI Bridge
& DMA
MPC7457
1 GHz L3
G4 CACHE
PowerPC
PENTEK Model 4205 G4 PowerPC

Figure 51
The Pentek RTS 2504 is a highly scalable real-time as an executive for managing data transfer tasks as well as
recording and playback system. It utilizes the Model performing digital signal processing or formatting functions.
7141 multiband transceiver PMC/XMC module with two
A built-in Fibre Channel interface connects directly
14-bit 125 MHz A/Ds, ASIC DDC, and DUC with
to JBOD arrays for real time storage to 500 gigabytes at
two 16-bit 500 MHz D/As.
rates up to 160 MB/sec. Standard RS-232 and 100 baseT
The factory-installed IP core 420 provides a dual Ethernet ports allow the PowerPC to communicate with a
wideband DDC and expands the decimation range of wide range of host workstations for control and software
the ASIC DDC. The core also includes an interpolation development applications.
filter that expands the interpolation factor of the ASIC
Fully supported by Pentek’s SystemFlow recording
DUC. The Model 7141-420 combines downconverter and
software and scalable from 2 to 40 channels in a single
upconverter functions in one PCI module and offers
6U VMEbus chassis, the RTS 2504 serves equally well
real-time recording and playback capabilities.
as a development platform for advanced research projects
The heart of the RTS 2504 is the Pentek Model and proof-of-concept prototypes, or as a cost-effective
4205 I/O Processor featuring a 1 GHz MPC7457 G4 strategy for deploying high-performance, multichannel
PowerPC, mezzanine sites for two PMC modules, and embedded systems.
two Xilinx Virtex-II FPGAs. The G4 PowerPC acts both
40
Products
Rack-mount Real-Time Recording and Playback Transceiver System
Model RTS 2701
Sample
TIMING BUS XTL
GENERATOR A OSC A RF RF RF XFORMR RF XFORMR
LVDS Clock A
XFORMR XFORMR
LVDS Sync A 16-BIT D/A 16-BIT D/A
Bus A
LVDS Gate A SYNC 125 MHz 125 MHz DAC5686
TTL Gate/ INTERRUPTS 14-BIT A/D 14-BIT A/D DIGITAL UPCONVERTER
Trigger & CONTROL Bus B
TTL Sync GC4016 32
14 14
LVDS Gate B 4-CHANNEL FLASH
16 DIGITAL
16 16 MB
LVDS Sync B 16 RECEIVER 24
TIMING BUS XTL 14 16
LVDS Clock B
GENERATOR B OSC B
VIRTEX-II Pro XC2VP50 FPGA
Sample IP Core 420 – Wideband DDC and Interpolation Filter
Clock B In
32 32 32
64
DDR DDR DDR
Pentek Model 7641-420 PCI 2.2 INTERFACE
SDRAM SDRAM SDRAM
Transceiver PCI Card 256 MB 256 MB 256 MB (64 Bits / 66 MHz)
PCI-X Bus
PCI USB Front & Rear

Express
Opteron / Pentium Server Class Motherboard Gigabit Ethernet
n-port Video Interface
SATA HARD SATA
DRIVES RAID SATA 10/100 Ethernet
Controller
DDR
RS-232 PS/2 PS/2
SDRAM
Serial Port Keyboard Mouse
System Drive
Figure 52
The Pentek RTS 2701 is a highly scalable real-time back file format for easy access by user applications for
recording and playback system in an industrial rack-mount analysis, signal processing, and waveform generation.
Opteron PC server chassis. Built on the Windows XP File headers include recording parameter settings and
professional workstation, it utilizes the Model 7641-420 time stamping so that the signal viewer correctly formats
multiband transceiver PCI module with two 14-bit and annotates the displayed signals.
125 MHz A/Ds, ASIC DDC, and DUC with two
A high-performance PCI Express SATA RAID
16-bit 500 MHz D/As.
controller connects to multiple SATA hard drives to
The factory-installed IP core 420 provides a dual support storage to 5 terabytes and real-time recording
wideband DDC and expands the decimation range of and playback rates to 500 MB/sec.
the ASIC DDC. The core also includes an interpolation
Multiple RAID levels, including 0, 1, 5, 6, 10 and
filter that expands the interpolation factor of the ASIC
50, provide a choice for the required level of redundancy.
DUC. The Model 7641-420 combines downconverter and
The Pentek RTS 2701 serves equally well as a develop-
upconverter functions in one PCI module and offers
ment platform for advanced research projects and proof-
real-time recording and playback capabilities.
of-concept prototypes, or as a cost-effective strategy for
Fully supported by Pentek’s SystemFlow recording deploying high-performance, multichannel embedded
software, the RTS 2701 uses a native NTFS record/play- systems.
41
Products
Portable Real-Time Recording and Playback Transceiver Instrument
Model RTS 2721
DIGITAL x3
125 MHz GIGABIT ENET
CH 1 IN DOWN
14-BIT A/D
CONVERTER
x2
HIGH RESOLUTION
DIGITAL VIDEO DISPLAY RS-232 SERIAL
125 MHz
CH 2 IN DOWN
14-BIT A/D x4
CONVERTER
USB 2.0
500 MHz x2
CH 1 OUT
16-BIT D/A DDR
DIGITAL SDRAM SATA 11
DUAL CORE
UP OPTERON
CONVERTER x1
500 MHz DDR PROCESSOR
CH 2 OUT PS/2 KEYBOARD
16-BIT D/A SDRAM
x1
PS/2 MOUSE
RAID
CONTROLLER x1
CLK A IN PENTEK MODEL 7641-420 VGA VIDEO
TRANSCEIVER PCI CARD
CLK B IN
TTL GATE/ SAMPLE

TRIG IN CLOCK
AND XTAL DATA DATA
TTL SYNC IN SYNC OSC DRIVES DRIVES
GENERATOR A
CLOCK DATA DATA

SYNC XTAL DRIVES DRIVES
BUS OSC
B RAID ARRAY
PENTEK RTS 2721 RECORDER
Figure 53
The Pentek RTS 2721 is a turnkey real-time record- Fully supported by Pentek’s SystemFlow recording
ing and playback instrument supplied in a convenient software, the RTS 2721 uses a native NTFS record/play-
briefcase-size package that weighs just 23 pounds. Built back file format for easy access by user applications for
on the Windows XP professional workstation, it includes analysis, signal processing, and waveform generation.
a dual-core Opteron processor, a high-resolution 17 in. File headers include recording parameter settings and
LCD monitor and a high-performance SATA RAID time stamping so that the signal viewer correctly formats
controller. and annotates the displayed signals.
The RTS 2721 utilizes the Model 7641 multiband A high-performance PCI Express SATA RAID
transceiver PCI module with two 14-bit 125 MHz controller connects to multiple SATA hard drives to
A/Ds, ASIC DDC, and DUC with two 16-bit 500 MHz support storage to 2.4 terabytes and real-time recording
D/As. The factory-installed IP core 420 provides a and playback rates up to 500 MB/sec.
dual wideband DDC and expands the decimation range
Pentek’s portable recorder instrument provides a
of the ASIC DDC. The core also includes an interpola-
flexible architecture that is easily customized to meet
tion filter that expands the interpolation factor of the
special needs. Multiple RAID levels, including 0, 1, 5,
ASIC DUC.
6, 10 and 50, provide a choice for the required level of
The Model 7641-420 combines downconverter and redundancy. With its wide range of programmable
upconverter functions in one PCI module and offers decimation and interpolation, the system supports signal
real-time recording and playback capabilities. bandwidths from 8 kHz to 60MHz.
42
Applications
Applications of Software Defined Radio
● Tracking Receiver System

● Software Radio Transceiver System
● 512-Channel SDR System in a single VMEbus Slot
● Radar Signal Processing System
● 8-Channel Beamforming System
Software Radio can be used in many different systems: tightly-packed frequency division multiplexed voice
channels.
Tracking receivers can be highly automated because
software radio allows DSPs to perform the signal Direction finding and beamforming are ideal
identification and analysis functions as well as the applications for digital receivers because of their excel-
adaptable tuning functions. lent channel-to-channel phase and gain matching and
consistent delay characteristics.
Signal intelligence applications and radar benefit
from the tight coupling of the A/D, DDC, DUC, and As a general capability, any system requiring a
DSP functions to process wideband signals. tunable bandpass filter should be considered a candidate
for using DDCs. Take a look at the following application
Cellular phone applications are one of the strongest
examples to give you some more details.
high-volume applications because of the high density of
43
Applications
Tracking Receiver System
215 MHz 128 MB Delayed Data

12-Bit A/D SDRAM
AD9430
FPGA
Peaks Power Tuning 32 32
FFT IP PC DDC FIFO
CORE CORE
Controller
16 MB
FLASH
Model 6821 215 MHz A/D Converter with FPGA
System Highlights
● A/D data delivered into SDRAM acts as a digital delay memory
● A/D data also delivered into a Pentek FFT IP core in FPGA
Model 6821 commercial (left) and
● FFT core detects the strength of signals at each analysis frequency conduction-cooled version
● PowerPC controller in FPGA sorts signals according to peak strenth
● PowerPC controller also tunes DDC IP core in FPGA to the strongest signal frequencies
● Delayed data from SDRAM feeds DDC IP core to compensate for FFT calculation time
● DDC captures these moving signals in real time and downconverts them to baseband
Figure 54
A tracking receiver locates unknown signals, locks the FPGA, accordingly. The delayed data from the
onto them and tracks them if their frequency changes. circular buffer feeds the input of this DDC core.
As shown above, to implement this receiver, we use The digital delay can be set to match the time it
the 128 MB SDRAM of the Model 6821 to create a takes for the FFT energy detection and the processor
delay memory function. algorithm for the tuning frequency decision, so that
frequency-agile or transient signals can be recovered
Samples from the A/D are sent into a circular buffer
from their onset. The dehopped baseband output is
within the SDRAM and also to a Pentek FFT IP core
delivered to the rest of the system through the FPDP
implemented in the FPGA. The spectral peaks of the FFT
port or, optionally, across a VXS link.
indicate the frequencies of signals of interest present at the
input. This Model is also available in a dual-channel
version as Model 6822. Both Models are available in
The PowerPC microcontroller of the FPGA digests
commercial and conduction-cooled versions.
this frequency list and decides which signals to track. It
then tunes the Pentek DDC core, also implemented in
44
Applications
4-Channel Software Radio Transceiver System
CH A PENTEK Model 7141 PENTEK Model 7141 CH A

OUT OUT
CH A IN CH A IN
125 MHz 125 MHz
500 MHz 320 MHz 14bit A/D 14bit A/D 320 MHz 500 MHz
16bit D/A DUC DUC 16bit D/A
CH B IN CH B IN
125 MHz 125 MHz
CH B 32 14bit A/D 14bit A/D CH B
OUT 128 MB 32 128 MB OUT
SDRAM XILINX CLK A XILINX SDRAM
CLK A
128 MB 32
VIRTEX-II VIRTEX-II 32
DUAL TIMING CLK B CLK B DUAL TIMING 128 MB
SDRAM PRO BUS GEN BUS GEN PRO SDRAM
CLOCK CLOCK
256 MB 32 & SYNC & SYNC 32
VP50 VP50 256 MB
SDRAM 4 BUS BUS 4 SDRAM
QUAD QUAD
DDC DDC
64 4 GC4106 4
64
GC4106
PCI INTERFACE PCI INTERFACE
PCI 32 16 MB 16 MB 32
PCI
FLASH FLASH
P14
PENTEK Model 4207
Front Panel MPC8641 Dual Quad

XMC
XMC // Optical Single/Dual Core 1000BT RS- XMC //
XMC
PMC
PMC Site
Site Interface FLASH DDR2
Enet 232C PMC Site
PMC Site
To VME P2 32 MB
FLASH
256 MB SDRAM
1 GB
SRIO 8x
PCI-X Bus 0 4x PCI-X Bus 1
(64 Bits, 100 MHz) (64 Bits, 100 MHz)
PCIe to
PCIe to
PCI-X Bridge
PCI-X Bridge
Dual
Dual
4 Gb
4 Gbit
Fibre
2x Channel
Fibre Channel
Controller
Dual 2x Dual
4x 4x
Zero
Latency
Dual
Crossbar Virtex-4 FPGA
VME64x 4x
Switch XC4VFX60 / FX100
2eSST
Dual FLASH
32 MB DDR2 SDRAM
Gigabit 2x
4x FLASH
128 MB 1 GB
VME64x ENET-x VXS VITA 41
Figure 55
This system accepts four analog inputs from Signal processing resources include the Freescale
baseband or IF signals with bandwidths up to 50 MHz MPC8641 AltiVec processor and an FX60 or FX100
and IF center frequencies up to 150 MHz. A total of Virtex-4 FPGA on the Model 4207 I/O processor, plus
eight DDC channels are independently tunable across a Virtex-II VP-50 FPGA on each PMC module.
the input band and can deliver downconverted output
Using these on-board processing resources this
signal bandwidths from audio up to 2.5 MHz.
powerful system can process analog input data locally
Four analog outputs can deliver baseband or IF and deliver it to the analog outputs. It can also be used
signals with bandwidths up to about 50 MHz and IF as a pre- and post-processing I/O front end for sending
center frequencies up to 100 MHz. The system supports and receiving data to other system boards connected
four independent D/A channels or two upconverted over the VMEbus or through switched fabric links using
channels with real or quadrature outputs. the VXS interface.
Ruggedized and conduction-cooled versions of the
boards used in this system are available.
45
Applications
512-Channel Software Radio Recording System in a Single VMEbus Slot
CH A PENTEK Model 7141-430 PENTEK Model 7141-430 CH A

OUT OUT
CH A IN CH A IN
125 MHz 125 MHz
500 MHz 320 MHz 14bit A/D 14bit A/D 320 MHz 500 MHz
16bit D/A DUC XILINX CH B IN CH B IN
XILINX DUC 16bit D/A
VIRTEX-II 125 MHz 125 MHz
CH B
VIRTEX-II CH B
32 14bit A/D 14bit A/D
OUT 128 MB PRO PRO 32 128 MB OUT
SDRAM CLK A SDRAM
VP50 CLK A VP50
128 MB 32 CLK B 32
DUAL TIMING CLK B DUAL TIMING 128 MB
SDRAM IP CORE
CORE BUS GEN BUS GEN SDRAM
IP CLOCK CLOCK IP CORE
256 MB 32 430
430 & SYNC & SYNC 430 32 256 MB
SDRAM 256-CHAN
256-CHAN BUS BUS 256-CHAN
4 4 SDRAM
DIGITAL
DIGITAL QUAD QUAD DIGITAL
DOWN
DOWN DDC JBOD Disk Array DDC DOWN
64 CONVERTER 4 4
CONVERTER GC4106 GC4106 CONVERTER 64
PCI INTERFACE PCI INTERFACE
PCI 32 16 MB 16 MB 32
PCI
FLASH FLASH
P14 2x PENTEK Model 4207

XMC
XMC
PMC
PMC Site
Site Interface DDR2
Enet 232C PMC Site
PMC Site
To VME P2 FLASH
32 MB
FLASH
256 MB SDRAM
1 GB
8x
(64 Bits, 100 MHz) SRIO (64 Bits, 100 MHz)
PCIe to
PCIe to
PCI-X Bridge
PCI-X Bridge
Dual
Dual
4 Gb
4 Gbit
Fibre
2x Channel Controller
Fibre Channel
Dual 2x Dual
4x 4x
Zero
Latency
Dual
VME64x Crossbar 4x Virtex-4 FPGA
2eSST
Dual FLASH
32 MB DDR2 SDRAM
Gigabit 2x 4x FLASH
128 MB 1 GB
Figure 56
Each Model 7141 PMC features the Xilinx Virtex-II Pentek’s SystemFlow® software presents an intuitive
Pro VP50 with a Pentek 256-Channel Digital Down- graphical user interface (GUI) to set up the DDC
converter (DDC) IP Core 430. Each channel provides channels and recording mode. The GUI executes on a
independent tuning frequency with a global decimation Windows host PC connected to the 4207 via Ethernet.
from 1024 to 9984. Either one of the two 14-bit A/D
A SystemFlow signal viewer on the PC allows
converters operating at 125 MHz sample rate can feed
previewing of data prior to recording and viewing of
this core producing a range of output bandwidths from
recorded data files in both time and frequency domains.
10 kHz to 100 kHz.
Files can be moved between the Fibre Channel disk and
A dual 4-Gbit Fibre Channel copper interface the PC over Ethernet.
allows wideband A/D data or DDC outputs from all
This system is ideal for downconverting and capturing
512 channels to be recorded in real time to a RAID or
real time signal data from a very large number of
JBOD disk array at aggregate rates up to 640 MB/sec.
channels in an extremely compact, low cost system.
46
Applications
Radar Signal Processing System
PENTEK Model 7142-428

CH A
CH A IN
125 MHz OUT
14bit A/D 320 MHz 500 MHz
CH B IN DUC 16bit D/A
125 MHz XILINX
14bit A/D VIRTEX-4 32 256 MB
CH C IN FPGA SDRAM
125 MHz
14bit A/D 32 256 MB
With
CH D IN SDRAM
125 MHz 4-chan.
14bit A/D 32 256 MB
DDC &
SDRAM
CLK A Interpol.
DUAL TIMING Filter
CLOCK 96
BUS GEN VIRTEX-4 FPGA
& SYNC
BUS
FX60 or FX100
64
16 MB 32 I/O PCI XMC
FLASH
PENTEK Model 4207 P14

Dual
4x
XMC
XMC
PMC
PMC Site
Site Interface DDR2
Enet 232C PMC Site
PMC Site
FLASH
32 MB
FLASH SDRAM To VME P2
256 MB
1 GB
8x
PCIe to
PCIe to
PCI-X Bridge
PCI-X Bridge
Dual
Dual
4 Gb
4 Gbit
Fibre
2x 2x Channel Controller
Fibre Channel
Dual Dual
4x 4x
Zero
Latency
Dual
VME64x Crossbar Virtex-4 FPGA
4x
2eSST
Dual FLASH
32 MB DDR2 SDRAM
Gigabit 2x 4x FLASH
128 MB 1 GB
Figure 57
Radar is well served by high-speed A/D converters FPGA. Factory-installed IP cores such as pulse compres-
and wideband digital downconverters. The channelized sion and FFT are available and can be factory installed
system shown above, takes advantage of a Model in this FPGA.
7142-428 multichannel transceiver with an installed
The upconverter with the interpolation filter can be
FPGA core that includes four wideband DDCs and an
used to generate arbitrary radar pulse waveforms that
interpolation filter.
can be used to calibrate the system. The D/A output can
Operating at sampling rates up to 125 MHz, the also be used for countermeasures, such as jamming or
A/D converters can digitize baseband signals with spoofing.
bandwidths up to 50 MHz. After frequency translation
Jamming blasts energy that disables radars, and
and filtering, the DDCs deliver complex (I & Q) data
spoofing deceives radars by making it seem that the
to the Model 4207 processor board. Here, data may be
target is a different shape, speed, direction or distance by
processed by custom user-defined algorithms before it is
using DSP techniques. This is especially useful for a jet
sent across the VXS interface for recording and off-line
or UAV to prevent it from getting shot down.
processing.
Note that one more PMC/XMC site is available for
The optional GateFlow FPGA Design Kit can be
installation of an additional module.
used to install custom algorithms in the Model 4207
47
Applications
8-Channel Beamforming System
PENTEK Model 7153 PENTEK Model 7153

CH A IN
Sync Bus Cable CH A IN
200 MHz 200 MHz
16-bit A/D 16-bit A/D
CH B IN CH B IN
200 MHz 200 MHz XILINX
XILINX
VIRTEX-5 VIRTEX-5
CH C IN CH C IN FPGA
FPGA 200 MHz 200 MHz
with CH D IN CH D IN with
200 MHz 200 MHz
4-Channel 16-bit A/D 16-bit A/D 4-Channel
DDC DDC
CLK A CLK A
DUAL TIMING DUAL TIMING
96 CLOCK CLOCK 96
BUS GEN BUS GEN
VIRTEX-5 FPGA & SYNC & SYNC VIRTEX-5 FPGA
64 BUS BUS 64
PCI I/O I/O PCI
P14
PENTEK Model 4207

XMC
XMC
PMC
PMC Site
Site Interface DDR2
Enet 232C PMC Site
PMC Site
To VME P2 FLASH
32 MB
FLASH
256 MB SDRAM
1 GB
8x
PCIe to
PCIe to
PCI-X Bridge
PCI-X Bridge
Dual
Dual
4 Gb
4 Gbit
Fibre
2x 2x Channel Controller
Fibre Channel
Dual Dual
4x 4x
Zero
Latency
Dual
VME64x Crossbar Virtex-4 FPGA
4x
2eSST
Dual FLASH
32 MB DDR2 SDRAM
Gigabit 2x 4x FLASH
128 MB 1 GB
To next 4207 VXS Backplane From previous 4207 VXS Backplane
Figure 58
The Model 7153 PMC/XMC module is a high-speed Data from the first 8-channel system is beamformed
digitizer featuring four 200 MHz 16-bit A/Ds with a using the PowerPC resources of the Model 4207 proces-
high-performance 4-Channel DDC. Two such modules sor and then sent through VXS to the second system.
mounted on the Model 4207 PowerPC I/O processor Beamformed data from the second system is combined
can be used to create an 8-channel beamforming system. with the first, and then propagated through VXS to the
Two or more of these systems can be joined together next system or else to the destination for display, analysis
to create multichannel systems with higher density. or storage.
The Model 7153 DDCs offer programmable phase Each 4X VXS backplane link supports 1.25 GB/sec
and gain adjustments, power meters and a summation of traffic between boards.
block that can be used to match all the beamformed
Alternate methods for delivering the final beamformed
channels.
output signals include front panel gigabit Ethernet to a
Joining the sync/gate facilities of all 7153 modules network and Fibre Channel to a real-time disk array for
supports synchronous sampling, triggering and gating of real-time recording.
all channels.
48
Summary
DSP Boards for VMEbus SDR Benefits
• Freescale Altivec G4 Benefits of Software Defined Radio:

PowerPC
• Texas Instruments • Reduction of DSP processing demands
C6000 DSPs • Very fast tuning
• Single, Dual, Quad and • Fast bandwidth selection
Octal Processor versions
• PMC, PMC/XMC, PCI • Zero frequency drift and error
and cPCI I/O peripherals • Precise, stable filter characteristics
• VME/VXS platforms • Excellent dynamic range
Figure 59 Figure 60
Pentek offers a comprehensive array of VMEbus To summarize, we restate the major benefits:
DSP boards featuring the AltiVec G4 PowerPC from
SDRs can dramatically reduce the DSP requirements for
Freescale and the TMS320C6000 family of processor
systems which need to process signals contained within a certain
products from Texas Instruments.
frequency band of a wideband signal.
On-board processor densities range from one to
The fast tuning of the digital local oscillator and the
eight DSPs with many different memory and interface
easy bandwidth selection in the decimating digital filter
options available.
and interpolation filter make the SDR easy to control.
The Models 4205 and 4207 I/O processor boards
Since the entire circuitry uses digital signal process-
feature the latest G4 PowerPCs, accept PMC mezzanines
ing, the characteristics are precise, predictable, and will
and include built-in Fibre Channel interfaces.
not drift with time, temperature or aging. This also
The Models 4294 and 4295 processor boards feature means excellent channel-to-channel matching and no need
four MPC74xx G4 PowerPC processors utilizing the for calibration, alignment or maintenance.
AltiVec vector processor capable of delivering several
With the addition of FPGA technology, dramatic
GFLOPS of processing power.
increases in system density have been coupled with a
The Models 4292 and 4293 processor boards feature significantly lower cost per channel. Furthermore,
the Texas Instruments latest TMS320C6000 family of FPGA technology allows one to incorporate custom
fixed-point DSPs that represent a 10-fold increase in algorithms right at the front end of these systems.
processing power over previous designs.
As we have seen, there are inherently many benefits
Once again, the ability of the system designer to and advantages to when using SDR. We hope that this
freely choose the most appropriate DSP processor for introduction has been informative. We stand ready to
each software radio application, facilitates system discuss your requirements and help you configure a
requirement changes and performance upgrades. complete SDR system.
Full software development tools are available for work- For all the latest information about Pentek SDRs,
stations running Windows and Linux with many different DSP boards and data acquisition products, be sure to
development system configurations available. visit Pentek’s comprehensive website regularly.
49
Links
The following links provide you with additional information about the Pentek products
presented in this handbook: just click on the Model number. Links are also provided to other
handbooks or brochures that may be of interest in your software radio development projects.
Model Description Page

7131 Multiband Receiver - PMC 19
7231 Multiband Receiver - 6U cPCI 19
7331 Multiband Receiver - 3U cPCI 19
7631A Multiband Receiver - PCI 19
7140 Multiband Transceiver with Virtex-II Pro FPGA - PMC/XMC 20
7240 Multiband Transceiver with Virtex-II Pro FPGA - 6U cPCI 20
7640 Multiband Transceiver with Virtex-II Pro FPGA - PCI 20
7140-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - PMC/XMC 21
7240-420 Transceiver w. Dual Wideband DDC and Interpolation - 6U cPCI 21
7340-420 Transceiver w. Dual Wideband DDC and Interpolation - 3U cPCI 21
7640-420 Transceiver w. Dual Wideband DDC and Interpolation - PCI 21
7140-430 Transceiver w. 256-Channel Narrowband DDC - PMC/XMC 22
7240-430 Transceiver w. 256-Channel Narrowband DDC - 6U cPCI 22
7640-430 Transceiver w. 256-Channel Narrowband DDC - PCI 22
7141 Multiband Transceiver with Virtex-II Pro FPGA - PMC/XMC 23
7641 Multiband Transceiver with Virtex-II Pro FPGA - PCI 23
7741 Multiband Transceiver with Virtex-II Pro FPGA - Full-length PCIe 23
7841 Multiband Transceiver with Virtex-II Pro FPGA - Half-length PCIe 23
7141-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - PMC/XMC 24
7241-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - 6U cPCI 24
7341-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - 3U cPCI 24
7641-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - PCI 24
7741-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - Full-length PCIe 24
7841-420 Transceiver w. Dual Wideband DDC and Interpolation Filter - Half-length PCIe 24
7141-430 Transceiver w. 256-Channel Narrowband DDC - PMC/XMC 25
7641-430 Transceiver w. 256-Channel Narrowband DDC - PCI 25
7741-430 Transceiver w. 256-Channel Narrowband DDC - Full-length PCIe 25
7841-430 Transceiver w. 256-Channel Narrowband DDC - Half-length PCIe 25
7141-703 Conduction-cooled Multiband Transceiver - PMC/XMC 25
7142 Multichannel Transceiver with Virtex-4 FPGAs - PMC/XMC 26
7242 Multichannel Transceiver with Virtex-4 FPGAs - 6U cPCI 26
7342 Multichannel Transceiver with Virtex-4 FPGAs - 3U cPCI 26
7642 Multichannel Transceiver with Virtex-4 FPGAs - PCI 26
7742 Multichannel Transceiver with Virtex-4 FPGAs - Full-length PCIe 26
7842 Multichannel Transceiver with Virtex-4 FPGAs - Half-length PCIe 26
More links on the next page ➤
50
Links

7142-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter - PMC/XMC 27
7242-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- 6U cPCI 27
7342-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- 3U cPCI 27
7642-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- PCI 27
7742-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- Full-length PCIe 27
7842-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- Half-length PCIe 27
7151 256-Channel DDC with Quad 200 MHz, 16-bit A/D - PMC 28
7251 256-Channel DDC with Quad 200 MHz, 16-bit A/D - 6U cPCI 28
7651 256-Channel DDC with Quad 200 MHz, 16-bit A/D - PCI 28
7751 256-Channel DDC with Quad 200 MHz, 16-bit A/D - Full-length PCIe 28
7851 256-Channel DDC with Quad 200 MHz, 16-bit A/D - Half-length PCIe 28
7152 32-Channel DDC with Quad 200 MHz, 16-bit A/D - PMC 29
7153 4-Channel DDC with Quad 200 MHz, 16-bit A/D - PMC/XMC 30
7156 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC 31
7256 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI 31
7656 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI 31
7756 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length PCIe 31
7856 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Half-length PCIe 31
7158 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC 32
7658 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI 32
7758 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length PCIe 32
7858 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Half-length PCIe 32
More links on the next page ➤
51
Links

6821-422 215 MHz, 12-bit A/D with Wideband DDCs - VME/VXS 33
6822-422 Dual 215 MHz, 12-bit A/D with Wideband DDCs - VME/VXS 34
6826 Dual 2 GHz 10-bit A/D - VME/VXS 35
6890 2.2 GHz Clock, Sync and Gate Distribution Board - VME 36
6891 System Synchronizer and Distribution Board - VME 37
7190 Multifrequency Clock Synthesizer - PMC 38
7290 Multifrequency Clock Synthesizer - 6U cPCI 38
7390 Multifrequency Clock Synthesizer - 3U cPCI 38
7690 Multifrequency Clock Synthesizer - PCI 38
7790 Multifrequency Clock Synthesizer - Full-length PCIe 38
7890 Multifrequency Clock Synthesizer - Half-length PCIe 38
9190 Clock and Sync Generator for I/O Modules 39
RTS 2504 Real-Time Recording and Playback Transceiver System 40
4205 PowerPC I/O Processor - VME 40
RTS 2701 Rack-Mount Real-Time Recording and Playback Transceiver System 41
RTS 2721 Portable Real-Time Recording and Playback Transceiver Instrument 42
4207 PowerPC and FPGA I/O Processor - VME/VXS 45
Handbooks and Brochures

Click here Putting FPGAs to Work for Software Radio Hanbook
Click here Critical Techniques for High-Speed A/D Converters in Real-Time Systems Handbook
Click here High-Speed Switched Serial Fabrics Improve System Design Handbook
Click here Model 4207 PowerPC and FPGA I/O Processor Board Brochure
52

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®

Software Defined Radio Handbook

Copyright © 1998, 2001, 2003, 2006, 2008 Pentek Inc.

SDR (Software Defined Radio) has revolutionized electronic systems for a

In order to fully appreciate the benefits of SDR, a conventional analog receiver

Nyquist’s Theorem and Sampling A Simple Technique to Visualize Sampling

Before we look at SDR and its various implementa-

Sampling Basics Baseband Sampling

Sampling Bandpass Signals

Let’s consider bandpass signals like the IF frequency

No Signal Energy No Signal Energy

Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7

Analog Radio Receiver Block Diagram Analog Radio Receiver Mixer

SPEAKER RF INPUT SIGNAL

RF IF AMP DEMODULATOR AUDIO

SDR Receiver Block Diagram

Figure 9 shows a block diagram of a software SDR Receiver Mixer

thereby converting it into digital samples. These samples

DDC Local Oscillator and Decimation DDC Signal Processing

Tuning Freq Decimation

This process is called decimation and it means keeping

SDR Transmitter Block Diagram

Digital Digital Analog Analog

Interpolation Filter: Time domain Interpolation Filter: Frequency Domain

Fs/N Fs Digital Digital

DDC Processing DUC Processing

Translation Filtering Filtering Translation

A/D DIGITAL LOWPASS INTERPOLATE DIGITAL D/A

Freq uency Deci mation Inter polation Freq uency

Tuning Bandwidth Bandwidth Tuning

Key DDC and DUC Benefits SDR Tasks

Early Roles for FPGAs Legacy FPGA Design Methodologies

 Registers and gates § Successful designs required high-level

FPGAs: New Device Technology FPGAs: New Development Tools

§ 500+ MHz DSP Slices and Memory Structures

FPGAs for SDR FPGAs Bridge the SDR Application Space

Typical Pentek Products with Installed SDR IP Cores

FPGA Resource Comparison

Virtex-II Pro Virtex-4 Virtex-5

CompactPCI Board Full-length VMEbus Board

Multiband Transceivers with Virtex-II Pro FPGA

TIMING BUS XTL

Model 7140-420 PMC/XMC ● Model 7240-420 6U cPCI

Transceivers with 256-Channel Narrowband DDC Installed Core

Model 7140-430 PMC/XMC ● Model 7240-430 6U cPCI

Multiband Transceivers with Virtex-II Pro FPGA

Model 7141 PMC/XMC ● Model 7241 6U cPCI ● Model 7341 3U cPCI

TIMING BUS XTL

Model 7141-420 PMC/XMC ● Model 7241-420 6U cPCI ● Model 7341-420 3U cPCI

Transceivers with 256-Channel Narrowband DDC Installed Core

Model 7141-430 PMC/XMC ● Model 7241-430 6U cPCI ● Model 7341-430 3U cPCI

Multichannel Transceivers with Virtex-4 FPGAs

Model 7142 PMC/XMC ● Model 7242 6U cPCI ● Model 7342 3U cPCI

TIMING BUS XTL

LVDS Clock B TIMING BUS XTL VIRTEX-4 FPGA

P15 XMC P4 PMC

Model 7142-428 PMC/XMC ● Model 7242-428 6U cPCI ● Model 7342-428 3U cPCI

DIGITAL DOWNCONVERTER CORE

INTERPOLATION CORE XC4VSX55

Model 7151 PMC ● Model 7251 6U cPCI ● Model 7351 3U cPCI

Model 7152 PMC ● Model 7252 6U cPCI ● Model 7352 3U cPCI

Model 7153 PMC/XMC ● Model 7253 6U cPCI ● Model 7353 3U cPCI

Registers and gates § Successful designs required high-level