Vidyalankar

S.E. Sem. III [CMPN]

Electronic Devices and Linear Circuits
Prelim Question Paper Solutions (CR)

1. (a) For the given amplifier circuit find AV, 15V [20]
AI, R0 and RI.
Assume suitable value of β 2.2kΩ
100kΩ
C1
C2

10kΩ Vo
Vin 10kΩ
3.90Ω

Solution :
Assume
β = 100
V R
VB = CC 2 = 1.36 V
R1 + R 2
RB = 9.09 k
VB − VBE
IB = = 13.61 µA
R B + (1 + B)R E
IC = β × IB = 13.61 mA
IE = 1.375 mA
 26 mV 
hie = βre = 100  
 1.375 mA 
hie = 1.891Ω
hfe = 100
ib ic
+ +
hie Hfeib
Vi RB RC R L V0

RE
− −

ZB = hie + (1 + β) RE Z0′ = 10 k || 2.2kΩ

ZB = 41.28 kΩ Z0 = RC = 2.2 kΩ = 1.8 kΩ
Zi = RB || ZB = 7.4466 kΩ

− h feib(R C || R L ) − h te (R C || R L ) − h fe (R C || R L )
AV = = =
ib ZB ZB ZB
AV = −4.36
I 0 V0 / R L Z
AI = = = A V i = −3.246
Ii Vi / Zi RL
(2) Vidyalankar : S.E. – EDLC

1. (b) Compare BJJ and FET amplifier circuits. [5]

Solution :
BJT AMPR FET AMPR
1. Provides larger gain. 1. Provides small gain
2. Low input impedance 2. High input impedance
3. BJT is basically current controlled 3. FET is basically voltage controlled
amplifier. amplifier.
4. ‘β’ is most important factor. 4. ‘gm’ is important factor.
5. Large loading effect. 5. Less loading effect.
2. (a) For the network find VGS, ID, VDS, AV, AV, A0 , RI. 20V [10]
Vp = −3V
IDSS = 8mA
910kΩ 2.2 kΩ
C1 Vo
C2

Vin 110kΩ 1.1kΩ CS

Solution :
VDD R 2
VG = = 2.157
R1 + R 2
RG = R1 | | R2 = 98.13 kΩ
VGS = VG − IDRs
2
 VGS 
ID = IDSS 1 − V 
 P 
2
 [2.157 − ID 1.1] 
= 8 1 − 
 −3 
8
=
9
[ 5.175 − 1.1 I D ]
2

8
ID =  (5.175)2 − (2) (5.175)(1.1) ID + (1.1) 2 I D
2 
9 
0 = 1.0756 I2D − 11.12 I D + 26.780
ID1 = 6.519 mA ID2 = 3.819 mA

VDS = VDD − ID (RS + RD)

VDS1 = VDD − ID1 (RS + RD) = −1.512 V } ∵ VDS should be +Ve
VDS2 = VDD − ID2 (RS + RD) = 7.397 V
∴ Correct ID = 3.819 mA and VDS 7.937 V

VGS = VG − ID RS
= 2.157 − (3.819) (1.1)
VGS = −2.01 V
 V 
gm = g m0 1 − GS 
 VP 
2 I DSS
gm0 =
| Vp |
 Prelim Question Paper Solutions (3)

(2) (8m)  2.04 

gm = 1−
(3)  3 
gm = 1706 µ

G D
+ + ID +
Vi RG Vgs rd RD
gm Vgs
V0

− − −
ZG = ∞ ZD − rd = 50 kΩ Z0 = rd | | RD
Z0 = RG = 98.13 kΩ (assume) = 50 k | | 2.2 k
= 2.107 k Ω
AV = −gm (rd | | RD)
= −1706 × 10−6 [2.107 × 103]
= −3.569

2. (b) Explain block diagram of OPAMP and give necessary expression for each block. [10]
Solution :
Block diagram of Op−Amp
IN
−
i/p i/p stage 2nd Stage Translator o/p stage o/p
+
NI
dual i/p dual i/p emitter follower Complementary
balanced o/p unbalanced o/p with constant symmetry
diff. amplifier diff. amplifier current bias class AB amplifier
The input stage is a dual input balanced output high gain differential amplifier, and has a very high input
resistance. This is done by making use of darlington connection or by FET as input stage. The output of
the 1st differential amplifier is used to drive dual input unbalanced output differential amplifier. Because
of direct coupling, the dc voltage at the output of intermediate stage is above ground potential. Therefore
a level shifter is used at the output of 2nd stage to shift the dc level at the output of the intermediate stage
down to zero with respect to ground. The level translator is an emitter follower using constant current
bias. The final stage is a push pull complementary symmetry amplifier, which increases the output
voltage swing and increases the current supplying capability of op−amp. VCC
First stage : Consists of transistors, which form the first
differential amplifier stage, using constant current bias
provided by transistor at the emitter and associated
resistances. This 1st stage has inverting and non−inverting V0
input and hence can be driven with two input's or a single Q1 Q2
V1 V2
input. The 1st stage establishes.
(1) high input resistance
(2) high voltage gain Q3
(3) rejects common signals
(4) eliminates drift Q4
(5) provides high CMRR
−Vee
(4) Vidyalankar : S.E. – EDLC

Second Stage : The second differential amplifier is driven from the output of first differential amplifier
and uses an emitter bias. This will also amplify the signals. Because of direct coupling used, the dc
potential at the collector is well above ground. Hence even if there is no input there is a dc signal output.
This is undesirable because it reduces the output swing.
Level Translator
Because of direct coupling used.
(1) dc level at the emitter rises from stage to stage. This increase in dc level tend to shift the operating
point of succeeding stage and hence limits the output voltage swing and distort the output signal.
(2) This will lead to error in dc signals, when used for dc applications. Hence a level shifting stage is
included to shift the output dc level at the second stage down to zero level. The output of the second
differential stage is fed to an emitter follower stage with constant current bias. Hence a positive
voltage at the collector of second stage can produce zero volts at the junction of R1 and R2 with
proper selection of components.

3. (a) Explain operation of Schmitt trigger with hysteresis diagram. [8]

Solution :
Vin
V0 A C
Vin
R1 t

B
R2
+Vsat
t
V R −Vsat
± Vref = ± sat 2
R1 + R 2
V0 Hysteresis

Vin
−Vref Vref H = Vref − (−Vref)
2 Vsat R 2
=
R1 + R 2
Vin < Vref Vin > Vref
Dead zone
−Vref < Vin < Vref

3. (b) Define (i) Output offset voltage (ii) Input bias current [6]
(iii) CMRR (iv) PSRR
Solution :
(i) Output offset voltage :
Whenever input terminal of opamp are grounded ideally out put should be zero. Practically some
amount of voltage is produced due to presence of noise at the input terminal. This voltage is called as
output offset voltage.
(ii) Input Bias Current : IB
An input bias current IB is defined as the average of the two input bias currents IB1 and IB2.
I +I
i.e. I B = B1 B2
2
I B1 → dc bias current flowing into NI input.
 Prelim Question Paper Solutions (5)

I B2 → dc bias current flowing into IN input. +VCC

IB2
Both input terminals are grounded, and IB1 and IB2
are two base currents of two transistors of the first
IB1
stage differential amplifiers. Even if both
transistors are identical, IB1 and IB2 will not be
−Vcc
equal, because of the internal impedance of the
two terminals.
RF
For 741, IB is 500 nA max at ± 15 V supply. IB is R
very small and it will cause a significant output
offset voltage. To reduce this offset, an offset V0
minimizing resistor is connected to the non Vin
inverting terminal, whose value is given by R OM =
RRF/RF + R ROM

Thus the two inputs will see the same driving point resistance and hence output offset due to IB can be
reduced.

(iii) CMRR :
When same input voltages are applied to the two terminals, the op−amp is said to be working in
common mode. Since op−amp amplifies only the difference, no common mode signal appear at the
output. But due to some imperfections in the op−amp, some common mode signal appears at the
output and that voltage gain.
A C = Voc / Vc A d = Vod / Vd

CMRR is defined as the ratio of differential gain to common mode gain and is usually expressed in
dB.
CMRR = 20 log10 | A d / A c | dB
Usually high values of CMRR is preferred and it is a function of frequency. It decreases as frequency
increases.
(iv) PSRR :
Power Supply Rejection Ratio V0 PSRR = ∆Vios
∆V

Variation in input offset wrt

Variation in power supply

3. (c) Realize using op Amp [6]

V0 = 2V1 + 5V2 + 7V3 − V4

RF (10 kΩ) RF (10 kΩ)

Solution : RF 10 kΩ
R1 R1 (5 kΩ)
V1 R
V4 (10 kΩ) R2 (2 kΩ)
V2
R3(1.33 kΩ) (10 kΩ)
V3 V0

−V4 R4 (10 kΩ)

(6) Vidyalankar : S.E. – EDLC

4. (a) Explain IC555 as astable multi−vibrator. [10]

Solution : V CC

RA
8 4 2/3 VCC
7
RB
5
6 5 3 V0
1/3 VCC
5
2
1 5 TON TOFF
C
100pF T
TON = 0.693 (RA + RB )C
TOFF = 0.693 (RB)C
T = 0.639 (RA + 2RB)C
TON
%D= × 100
T

4. (b) Design a square wave generator for frequency of 2KHz and 80% duty cycle [10]
Solution :
f = 2KHz
1
T= = 0.5 msec Let C = 0.1µF
2K
T 0.5 × 10−3
RA + 2RB = = = 7215 Ω
0.693 (C) 0.693(0.1µ)
RA + 2RB = 7 215
T
% D = ON × 100
T
R + RB
∴0.80 = A
R A + 2R B RA = 4.329 kΩ
RA + RB = 5772 RB = 1.443 kΩ

5. (a) Explain current limiting and fold back protection in 723 [8]
Solution :

Current Limit Protection :

If the current limit protection is not given, and if the load demands more current e.g. under short circuit
conditions, the IC tries to provide it at a constant output voltage getting hotter all the time. This may
ultimately burn the IC.

The IC is therefore, provided with a current limit facility. Current limiting refers to the ability of a
regulator to prevent the load current from increasing above a preset value. The output voltage remains
constant for load current below Ilimit. As current approaches the limit, the output voltage drops. The
current limit Ilimit is set by connecting an external resistor RCL between the terminals CL and CS as shown
in fig. The CL terminal also connected to Vo and Cs terminal to the load.
 Prelim Question Paper Solutions (7)
Vo
ILOAD Vo Vsense
VC + – RL = 15 Ω
Q2
RCL
6Ω
CS
CL L 15V
O VLOAD 2Ω
+ VBE A
D Ilimit
Q1 –
O
2.5 A Io
Error ILOAD
Amp
(b) Characteristic curve
(a)
The load current produces a small voltage drop Vsense across RCL. This voltage Vsense is applied directly
across the base emitter junction of Q1. When this voltage is approximately 0.5 V, transistor Q1 begins to
turn ON. A part of current from error amplifier goes to the collector of Q1, thereby decreasing the base
current of Q2. This in turn, reduces the emitter current of Q2. So any increase in load current will get
nullified.

If the ILOAD decreases, VBL of Q1 drops, repeating the cycle in such a manner that the load current is held
constant to produce a voltage across RCL sufficient to turn ON Q1. This voltage is typically 0.5 V or 0.65
V.
Vsense 0.5V
So, Ilim it = =
R CL R CL

This method of current limiting is also referred to as current sensing technique.

5. (b) Design a regulator using IC723 for V0 = 5V, I0 = 100mA, Vin = 15, Vsense = 0.7V, ISC = 150 mA. [12]
Solution :
V0 = 5V
I0 = 100 mA
∴LVLI Design
Vin

Vref − V0
12 11 RSC R1 =
I
Vref V0 o/p
7 −5
R1 7 = = 2kΩ
Vref = 7V CL 1 mA
I = 1mA NINV 2 V 5
R2 3 CS R2 = 0 = = 5kΩ
R3 I 1mA
R3 = R1 || R2
7 13 100 pF = 5k || 2 k = 1.33 kΩ
hhh

Vsen sec 0.7

RSC = =
ISC 150 mA
RSC = 4.67 Ω
(8) Vidyalankar : S.E. – EDLC

6. (a) Explain practical differentiator circuit. [8]

Solution :
CF Z f(s)
Z i(s) R1 C1 RF

+Vcc
dVin
~ Vin V0 = − R F C1
dt
-VCC
if RFC1 > R1C1 or RFCF

R0M RL

Fig. (c) : Practical Differentiator

Expression for output voltage of basic differentiator
Apply KCL at node V2.
Ic = IB2 + IF ∵ IB2 = 0
Ic = IF
d Vc V2 − V0
C1 =
dt RF

But Vc = Vin − V2
d ( Vin − V2 ) V2 − V0
C1 =
dt RF
But V1 = V2 = 0, because A is very large (virtual ground).
dVin V
C1 =− 0 .
dt RF

dVin
V0 = − R F C1 ………(A)
dt

Thus the output voltage is equal to the RFC1 times, the negative instantaneous rate of change of input
voltage Vin with time. Thus minus sign indicates that a 180° phase shift of the output waveform V0 with
respect to the input signal.

6. (b) Explain successive approximation ADC [7]

Solution :
Successive approximation analog to digital converter :
Fig. shows the schematic and the conversion chain for 4 bit converter of this type. Successive
approximation register (SAR) is the heart of this converter. The SAR sets the MSB to the DAC input on
the first clock cycle, the second MSB on the second clock input and so on. Every time a particular bit is
set, the bit set prior to this is either kept set or reset depending upon whether the DAC output obtained by
setting the present bit is less than or greater than the analog input. The SAR proceeds to the LSB in this
manner to get the desired output. Each conversion in an n−bit converter of this type takes n clock cycles.
It is the most widely used technique for constructing high speed, high resolution analog to digital
converter.
 Prelim Question Paper Solutions (9)

(c) Design a differentiator for frequency of 5KHz [5]

Solution :
RF V0
C1 20dB

V0 0 f
Vin fa

−20dB
1
fa = fa = 5KHz
2πR F C1
1
RF = Let C = 0.01µF
2π(5 × 10 )(0.01 × 10−6 )
3

RF = 3.183 kΩ

7. (a) Explain PLL [10]

Solution :
A phase locked loop (PLL) is defined as a control mechanism by which the frequency and phase of the
incoming signal is synchronised with the frequency and phase of the VCO.
The phase locked loop consists of three blocks.
1. Phase detector
2. Low pass filter
3. Voltage controlled oscillator
The amplifier may or may not be a part of PLL. The block diagram of PLL is shown below.

fs Phase Ve(t) Low pass Filter Ve′ (t)

Vin = Vinsinωt Amplifier
input Detector (LPF)
A

Voltage controlled
f0
oscillator (VCO) Vd(t)

The PLL passes through three modes of operation to go into lock condition.
(10) Vidyalankar : S.E. – EDLC

Before the application of the input, the VCO operates at a frequency depending upon the external
resistance and capacitor. This is called the free running frequency f 0′ of the VCO. This mode of operation
of the PLL is called the free running mode.

On the application of an external input Vin sin ωs t, the output of the phase detector, has the sum and
difference frequency components. [fs + f0 and fs ~ f0].
The phase detector compares the input frequency fs with the feedback frequency f0. The output of the
phase detector is proportional to the phase difference ‘θ’ between fs and f0. The output of the phase
detector has a dc component, called the error voltage (Ve(t)).
The low pass filter passes the low frequency component [fin ~ f0] and blocks the high frequency
component. (fin + f0) and error voltage Ve′ (t) is obtained and is give as the control input to the VCO so
that the frequency of the VCO approaches the frequency of the incoming signal. This mode of operation
when the VCO frequency changes and approaches the incoming signal frequency is called the Capture
mode.
When the two inputs to the phase detector are equal, the output of the phase detector has an error voltage
which is just sufficient to keep the VCO operate at the frequency of the incoming signal fs. This mode of
operation is the Lock mode.
The design of VCO should be such that fin + f0 and fs ~ f0 component are significantly apart. The action of
the loop is to make ‘θ’ take just that value which is required to generate the DC control voltage necessary
to change value to fin.
This allows the PLL to track any frequency changes of the input signal, once lock has been acquired.
Lock Range :
The range of frequencies of the input signal over which a PLL can maintain a lock is called the lock range.

Capture Range :
The range of frequencies of the input signal over which a PLL can acquire lock is called the capture range.
The greatest capture range possible is equal to the lock range but capture range is less than lock range.
The capture of an input signal does not take place as soon as the signal is applied but takes finite time,
called the pull-in-time. It depends on the initial frequency and phase difference between the input and the
VCO signal as well as on the overall loop gain.

Phase Detector
The phase detector compares the input frequency and VCO frequency and generates a dc voltage that is
proportional to the phase difference between two frequencies.
Phase detectors are classified as Analog and digital phase detectors depending on the type of circuit used.

Analog Phase Detector fi fi + f0

A mixer can be used as an analog phase detector. The mixer
Mixer
gives output which has the sum and difference frequency
f0 fi − f0
component of the two inputs.
Vac
The dc voltage of the output waveform depends on the phase
difference (θ) between he input signals. The dc output decreases
Vmax
with the increase in phase angle.

Vmin
θ
0° 90° 180°
 Prelim Question Paper Solutions (11)

Transfer Characteristics Ve(t)

When the PLL is in block, a frequency
shift at the input is transferred to a voltage
level shift at the VCO control terminal. Slowly increasing
The following characteristics shows the f 0′ f2 input frequency
voltage frequency characteristics of the
PLL.
Ve(t)
Capture Range Fig.(a)
2 ∆fC
The input is assumed to be a sine wave
f4 Slowly decreasing
whose frequency is swept over a broad
frequency range and the vertical axis f 0′ f3 input frequency
corresponds to the error voltage Ve(t).

In figure (a), the incoming input frequency Fig.(b)

is slowly increasing. The loop does not Lock Range
respond till the input frequency reaches 2∆fL
f1.s
This frequency f1 corresponds to the Lower edge of the capture range. After this, the loop immediately
locks on to the input signal causing a negative jump of error voltage (since input frequency is less than
VCO frequency). As the input signal frequency is further increased beyond f1, fe(t) varies with frequency
1
with a slop equal to the reciprocal of the VCO gain, and goes positive when input frequency is greater
K
than VCO frequency. The loop tracks the input until the input frequency reaches f2 which corresponds to
the upper edge of the Lock range. Then the PLL loses track of the input frequency. It is no more in the
Lock state.
If the input frequency is slowly swept back, the cycle repeats itself. The PLL recaptures signal of
frequency f3 and traces it down to frequency f4. f3 is called the upper edge of the capture range and f4 is
the lower edge of the Lock range.
The frequency range between f1 and f3 corresponds to the total capture range
i.e. f3 − f1 = 2 ∆fc and
the frequency range between f2 and f4 corresponds to the total lock range.
f2 − f4 = 2 ∆ fL.
The PLL has an inherent selectivity about the free running frequency. It would respond to frequencies
which are separated from f 0′ by less than ∆fc or ∆fL depending on whether the loop starts with or without
an initial lock condition.

7. (b) Instrumentation Amplifier using 3−Op−amp [10]

Solution :
In a number of industrial and consumer application, one is required to measure and control physical
quantity. Some examples are measurement and control of temperature, humidity, water flow, light
intensity etc. These physical quantities are usually measured with the help of transducer and the
transducer is frequently located some distance away from the measurement system. The signal level at the
transducer side are often low and their source impedance are high. So the output of transducer has to be
amplified so that it can drive the indicator or display system. This function is performed by
instrumentation amplifier. That instrumentation amplifier should have following characteristics.
(12) Vidyalankar : S.E. – EDLC

v1 + V0′
A1
v1
− R4
R1
R3
v1
−

R2 +
v2 V0
R3
R1
− R4
v2 A2
v2 + V0′′

Differential amplifier with three OP-AMP used in instrumentation amplifier.

1. It should have differential inputs.
2. It should have high input impedance and common mode rejection ratio.
3. The amplifier should be provided with simple gain adjustment.
4. It should have low output impedance.

In this circuit OP-AMP 1 and OP-AMP 2 are basically connected in non-inverting configuration. The
only change is that instead of grounding inverting terminal of both OP-AMP [as in non-inverting OP-
AMP] they are connected to resistor R2.

Effectively the inverting terminal of OP-AMP 1 is fed by a voltage V1 through R2 and the inverting
terminal of OP-AMP 2 is fed by a voltage V2 through R2. This is obvious by virtual ground concept.

Analysis of above circuit :

R4  ″
V0 = V0 − V0′  ………(1)
R3  
 R1  R1
But V0′ = 1 +  V1 − V2
 R2  R2
 R 
V0″ = 1 + 1  V2 − 1 V1
R
………(2)
 R2  R2

Substitute (2) in (1),

R  2R   2R  
V0 = 4  1 + 1  V2 − 1 + 1  V1 
R 3  R2   R 2  
R4  2R1 
V0 = 1 +  [ V2 − V1 ]
R3  R2 

V0 R  2R 
A = = 4 1 + 1  .
V2 − V1 R 3  R2 

The gain may be easily adjusted without disturbing circuits symmetry by varying the resistance R2.
 Prelim Question Paper Solutions (13)

7. (c) Features of practical Op−amp [10]

Solution :
An ideal op−amp exhibits the following electrical characteristics.
(a) Infinite voltage gain
(b) Infinite input resistance Ri, so that any signal source can drive it and there is no loading of the
preceding stage.
(c) Zero output resistance R0, so that output can drive an infinite number of other devices.
(d) Zero offset voltage, hence can be direct coupled.
(e) Infinite BW, so that frequencies from 0 to ¥ Hz can be amplified without attenuation.
(f) Infinite CMRR, so that common mode noise is zero.
(g) Infinite slew rate, so that output voltage changes simultaneously with input.

Practical Characteristics of Op−Amp (µA 741)

(a) Large voltage gain (of the order of 2 × 105)
(b) Very high input resistance (1 MΩ to 10 MΩ)
(c) Low output resistance (10 Ω to 100 Ω)
(d) Non zero output offset voltage (as high supply voltage)
(e) High CMRR (80 − 120 dB)
(f) Small bandwidth (5 Hz approximately since the gain bandwidth product is a constant)
(g) Finite slew rate (5 V/µsec.)
7. (d) CE−Configuration of BJT [10]
Solution :
1) Experimental setup to study V−I characteristics of CE transistor
C
IB IC
B

E
VCE
(0−1)V (0−10)V
VBE

2) Input characteristics IB
VBE = f (IB , VCE ) (µA)
VCE = 2V VCE = 5V

VBE (V)
0
Input characteristics is similar to that of PN junction diode, IB increases with increase in VBE because
the input junction resembles a PN junction. When VCE increases, IB increases due to the phenomenon
called early effect. When VCE increases, junction width increases, base width decreases, due to the
decrease in recombination in base, the base current IB decreases.
IC
3) Output characteristics (mA)
IC = f (IB , VCE ) IB = 20 µA

IB = 10 µA

VCE(V)
0
(14) Vidyalankar : S.E. – EDLC

From the transistor output characteristics, it can be seen that IC is independent of VCE but depends on
IB. Hence transistor operate as a current controlled current source (CCCS). The slope in the output
characteristic is due to early effect. The slope shows that the transistor is not an ideal current source.

4) Transfer characteristics of CE transistor IC (mA)

It is a graph drawn with IC verses IB keeping VCE constant.

IB
0
(µA)
5) Current gain of CE transistor
i) βac is defined as the ac current gain, it is the ratio of the change in the collector current to the
change in base current, keeping VCE constant.
∆ IC
βac = , VCE constant
∆ IB
ii) β DC is defined as the dc current gain, it is the ratio of the collector current to the base current
keeping VCE constant.
IC
β DC = , VCE constant
IE
β is in the range of 50 to 500.

Note : β is temperature dependent and it increases by 1% per °C. It varies from device
to device (1 : 3)

6) Input resistance and output resistance of CE transistor

By definition,
∆VBE
Ri = VCE constant = 1/slope of input characteristics (typically 1 to 5 kΩ)
∆Ι Β
∆VCE
Ro = I B constant = 1/slope of output characteristics (typically > 50 kΩ)
∆I C

From the transistor working,

IC = α IE + ICBO where α is that part of injected carriers reaching the collector.

= α (IC + I B ) + I CBO
(1 − α) IC = αI B + I CBO

α I
IC = IB + CBO
1− α 1− α
∴ IC = β IB + (1 + β) ICBO

∴ IC = β IB + I CEO where ICEO = (1 + β) ICBO

(l) Thermal Runaway in Transistor (Effect of leakage current)

The junction temperature of a transistor can increase due to the increase in ambient temperature or
due to self heating. The transistor collector current is given by
IC = β IB + (1 + β) ICBO
 Prelim Question Paper Solutions (15)

ICBO is temperature dependent, ICBO doubles for 10°C rise in temperature in Si transistor. Hence if
the collector junction temperature (Tj) increases, the minority leakage current ICBO increases, this
increases IC , hence the power dissipation in transistor (PD) increases. Since power is dissipated in
the form of heat, the junction temperature further increases, further increasing IC.
Tj ↑ ICBO ↑ IC ↑ PD ↑

Thus due to thermal regeneration, IC increases to a very high value causing damage to the transistor
(burn out). This phenomenon is by which IC increases with temperature is called as thermal
regeneration. The process by which transistor undergoes damage is called thermal runaway.
If the rate at which power dissipated in transistor is equal to the rate at which power radiated outside,
then junction temperature remains constant. This is achieved by using Heat Sink.
Note : Thermal bias stability is very important in the case of BJT.

(m) Regions of operaton of CE transistor

Consider the output characteristics of common emitter transistor as shown.
The output characteristic of CE transistor can be divided into 3 regions
1) Cut off region
In this region, the emitter base junction and the collector base junction are reverse biased. In
ideal case IC = 0, but practically IC = (1 + β) ICBO (a minority leakage current through transistor).
This is the non linear region of its characteristics. In this region, transistor operate as an open
switch. This region is also called as OFF state of transistor.
IC
(mA) IB = 30 µA

Saturation region
Active IB = 20 µA
Region
(ON state)
IB = 10 µA
IB = 0
0 VCE (V)
Cut−off region (OFF state)
2) Active region
In this region, the emitter base junction is forward biased and collector base junction is reverse
biased. If IB is kept constant, then IC is relatively independent of VCE. If VCE is kept constant, then
change in IC is proportional to change in IB, i c ∝ i b , i c = β i b , i c is the amplified base current.
This is the linear region of its characteristics. In this region, transistor operates as an amplifier
and also the transistor operate as a current controlled current source. [CCCS]
3) Saturation region
In this region, the emitter base junction and collector base junction are forward biased. Here IC
increases with VCE, but i c is not proportional to i b (due to high level injection of carriers into the
base). This is the non linear region of its characteristics. In this region, transistor operate as a
closed switch. This region is also said to be the ON state of transistor.

(n) Advantages and Disadvantages of BJT

BJTs when compared to FETs, have the advantages of possessing good current gain hfe, good
transconductance gm. They have the disadvantages of poor stability of operating point with
temperature, high noise, poor distortion, high intermodulation products, low input impedance when
used in CE or CB comfigurations, and a risk of thermal runaway.