EE141

EE141-Fall 2003
Digital Integrated
Circuits
Instructor: Borivoje Nikolić

TuTh 9:30-11
203 McLaughlin

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What is this class all about?

‰ Introduction to digital integrated circuits.
ƒ CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay,
noise margins, and power dissipation. Sequential
circuits. Arithmetic, interconnect, and memories.
Design methodologies.
‰ What will you learn?
ƒ Understanding, designing, and optimizing digital
circuits with respect to different quality metrics:
cost, speed, power dissipation, and reliability

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Practical Information
‰ Instructor
ƒ Prof. Borivoje Nikolic
570 Cory Hall, 643-9297, bora@eecs.berkeley.edu
Office hours: Mo 1pm-2:30pm, Th 1:30-2:30pm
‰ TAs:
ƒ Vladimir Petkov, vlpetkov@eecs.berkeley.edu
ƒ Nuntachai Poobuapheun, nuntachp@eecs.berkeley.edu
ƒ Gang Liu, liugang@eecs.berkeley.edu
Office hours: 353 Cory
‰ Web page:
http://bwrc.eecs.berkeley.edu/Classes/ICDesign/EE141_f03/

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Discussions and Labs

‰ Discussion sessions
ƒ M 3-4pm, 285 Cory
ƒ F 4-5pm, 203 McLaughlin
‰ Labs (353 Cory)
ƒ M 9am-12pm
ƒ Tu 9:30am-12:30pm
ƒ W 12-3pm
ƒ W 3-6pm
ƒ F 11am-2pm

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Class Organization
‰ 10 Assignments
‰ One design project with three phases
‰ Labs: 6 software, 1 hardware
‰ 2 midterms, 1 final
ƒ Midterm 1: Thursday, October 2, evening
ƒ Midterm 2: Thursday, November 6, evening
ƒ Final: December 12, 8-11am

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Grading Policy
‰ Homeworks: 10%
‰ Labs: 10%
‰ Projects: 20%
‰ Midterms: 30%
‰ Final: 30%

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Class Material
‰ Textbook: “Digital Integrated Circuits – A
Design Perspective”, 2nd ed, by J. Rabaey, A.
Chandrakasan, B. Nikolic
‰ Class notes: Web page
‰ Lab Reader:
Available on the web page!
Selected material will be made available from Copy
Central
‰ Check web page for the availability of tools

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The Web Site

‰ Class and lecture notes
‰ Assignments and solutions
‰ Lab and project information
‰ Exams
‰ Many other goodies …
‰ The sole source of information
‰ http://www-inst.eecs.berkeley.edu/~ee141
Print only what you need: Save a tree!

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Software
‰ MicroMagic
ƒ Schematic editor: Sue
ƒ Layout editor: Max
ƒ Online documentation and tutorials
‰ HSPICE and IRSIM for simulation

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Getting Started
‰ Assignment 1: Getting SPICE to work –see
web-page on Thursday
‰ Due next Wednesday, September 3, 5pm
ƒ Drop box outside 275 Cory
‰ NO discussion sessions or labs this week.
‰ First discussion sessions in Week 2
‰ First Software Lab in Week 3

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Digital Integrated Circuits

‰ Introduction: Issues in digital design
‰ The CMOS inverter
‰ Combinational logic structures
‰ Sequential logic gates
‰ Design methodologies
‰ Interconnect: R, L and C
‰ Timing
‰ Arithmetic building blocks
‰ Memories and array structures

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Introduction
‰ Why is designing
digital ICs different
today than it was
before?
‰ Will it change in
future?

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The First Computer

The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470

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ENIAC - The first electronic computer (1946)

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The Transistor Revolution

First transistor
Bell Labs, 1948

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The First Integrated Circuits

Bipolar logic
1960’s

ECL 3-input Gate

Motorola 1966

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Intel 4004 Micro-Processor

1971
1000 transistors
1 MHz operation

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Intel Pentium (IV) microprocessor

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Moore’s Law

zIn 1965, Gordon Moore noted that the

number of transistors on a chip doubled
every 18 to 24 months.
zHe made a prediction that
semiconductor technology will double its
effectiveness every 18 months

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Moore’s Law
16
COMPONENTS PER INTEGRATED FUNCTION

15
14
13
12
LOG2 OF THE NUMBER OF

11
10
9
8
7
6
5
4
3
2
1
0
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975

Electronics, April 19, 1965.

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Evolution in Complexity

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Transistor Counts
1 Billion
K
Transistors
1,000,000

100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
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Moore’s law in Microprocessors

1000
Transistors (MT)
100 2X growth in 1.96 years!

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year

Transistors on Lead Microprocessors double every 2 years

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Die Size Growth

100
Die size (mm)

P6
10 486 Pentium ® proc
386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year

Die size grows by 14% to satisfy Moore’s Law

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Frequency
10000
Doubles every
Frequency (Mhz) 1000 2 years
P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years

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Power Dissipation
100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Lead Microprocessors power continues to increase

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Power will be a major problem

100000
18KW
10000 5KW
Power (Watts) 1.5KW
1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year

Power delivery and dissipation will be prohibitive

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Power density
10000
Rocket
Power Density (W/cm2)

Nozzle
1000
Nuclear
Reactor
100

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year

Power density too high to keep junctions at low temp

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Not Only Microprocessors

Cell
Phone

Small Power
Signal RF RF

Digital Cellular Market

(Phones Shipped) Power
Management

1996 1997 1998 1999 2000

Analog
Units 48M 86M 162M 260M 435M Baseband

Digital Baseband
(DSP + MCU)

(data from Texas Instruments)

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Productivity Trends
Logic Transistor per Chip (M)

10,000
10,000,000 100,000
100,000,000
1,000 Logic Tr./Chip 10,000
1,000,000 10,000,000
(K) Trans./Staff - Mo.

Tr./Staff Month.
100
100,000 1,000
1,000,000
Complexity

Productivity

10 58%/Yr. compounded 100

10,000 Complexity growth rate 100,000

1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x 21%/Yr. compound
xx Productivity growth rate
x
0.01
10 0.1
100
0.001
1 0.01
10
1981
1983
1985
1987
1989
1991
1993
1995

1999
2001

2005
2007
1997

2003

2009

Source: Sematech

Complexity outpaces design productivity

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Why Scaling?
‰ Technology shrinks by 0.7/generation
‰ With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
‰ Cost of a function decreases by 2x
‰ But …
ƒ How to design chips with more and more functions?
ƒ Design engineering population does not double every
two years…
‰ Hence, a need for more efficient design methods
ƒ Exploit different levels of abstraction
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Design Abstraction Levels

SYSTEM

MODULE

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

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This Class
‰ Introduces basic metrics for design of
integrated circuits – how to measure delay,
power, etc.
‰ Groups layout rectangles into transistors and
wires
ƒ Transistors and wires into gates
ƒ Gates into functions
‰ Need to verify that the assumptions are valid

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Next Tuesday
‰ Introduces basic metrics for design of
integrated circuits – how to measure
delay, power, cost, etc.
‰ Brief intro to IC manufacturing and
design

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