Professional Documents
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OUTLINE
Design Approach
Process Technology
MOSIS Design Rules
Primitive Cells, Basic Cells, Macro Cells
Projects
Maskmaking
References
Homework
With millions of
transistors per chip it is
impossible to
design with no errors
without computers to
check layout, circuit
performance, process
design, etc.
Problem Specification
Behavioral Design
Functional and Logic Design
Circuit Design
Physical Design (Layout)
Gate-Level Model
Geometric Model
PROCESS SELECTION
NMOSFET PMOSFET
N+ Poly
0.75 µm Aluminum
6000 Å
Field Oxide
N+ D/S LDD P+ D/S n+ well
p+ well LDD contact
contact P-well N-well
Channel Stop
NMOSFET PMOSFET
N+ Poly P+ Poly
N+ D/S P+ D/S
p+ well n+ well
contact contact
LDD
P-well N-well LDD
OTHER LAYERS
Design Layers Other Design Layers 81
N-WELL (42) P+ Resolution (87) 43
ACTIVE (43) STI Resolution (82)
POLY (46) Stop Resolution (84) STI
P-SELECT (44) Vt Resolution (85)
N-SELECT (45) 85 Active Resolution (83)
CC (25) N+ Resolution (88) 46 44
METAL 1 (49) 2.0 2.0 49
VIA (50) 1.5 1.5
45
1.0 1.0 42
METAL 2 (51)
84 Nmos Vt 87 Poly
2.0 2.0 2.0 2.0
LAYOUT RULES
http://www.mosis.com/design/rules/
Well Active in p-well Poly
1
10 6 3
Active
3 n+ n+
p+ Poly 2
5 2
Diff 3 Poly
9 Same well edge
Potential Potential n-Substrate 5 3 3
(Outside well) 2
p+ n+
active 1 3 contact to poly metal
2 1
2
3
2
3
2 2
1
2 p select
If λ = 1 µm then contact is 1
2 µm x 2 µm
Rochester Institute of Technology
Microelectronic Engineering
http://www.mosis.com/design/rules/
metal two
2
1
MOSIS Educational Program
3
2
MOSIS REQUIREMENTS
RIT PROCESSES
PRIMITIVE CELLS
Primitive Cells
Inverter
NOR2
NOR3
NOR4
NAND2
NAND3
NAND4
Etc.
CMOS INVERTER
Vin Vout
+V
Idd
PMOS
Vin Vout
NMOS
CMOS
TRUTH TABLE
VIN VOUT W = 40 µm
0
1
1
0
Ldrawn = 2.5µm
Rochester Institute of Technology
Microelectronic Engineering
Lpoly = 1.0µm
Leff = 0.35 µm
© December 31, 2007 Dr. Lynn Fuller Page 24
CMOS VLSI DESIGN
VA VA
VOUT VOUT
VB VB
VA VB VOUT VA VB VOUT
0 0 1 0 0 1
+V 0 1 0 0 1 1
1 0 0 1 0 1 +V
1 1 0 1 1 0
VOUT VOUT
VA
VB
VA VB
Rochester Institute of Technology
Microelectronic Engineering
BASIC CELLS
Basic Cells
XOR
D FF XOR
JK FF Input A
Data Latch Port in A’
A’B
B XOR
Port out
Input B
Port in
XOR = A’B+AB’
A
AB’
B’
XOR
XOR
FILP-FLOPS
R S Q
R Q
0 0 Qn-1
RS FLIP FLOP 0 1 1
QBAR 1 0 0
S
1 1 INDETERMINATE
D FLIP FLOP
Q
DATA QBAR
CLOCK
Q=DATA IF CLOCK IS HIGH
IF CLOCK IS LOW Q=PREVIOUS DATA VALUE
Rochester Institute of Technology
Microelectronic Engineering
T FLIP FLOP
T Qn-1 Q
Q 0 0 0
T 0 1 1
1 0 1
QBAR 1 1 0
JK FLIP FLOP
PROJECTS
Multiplexer
Full Adder
Binary Counter I0 A’B’I0
A’
A
I1 A’BI1
Q
I2 AB’I2
B B’
ABI3
I3
4:1 Multiplexer
MULTIPLEXER
DE MULTIPLEXER
Q0
A
Q1
De-multiplexer I
Q2
B
Q3
DE MULTIPLEXER
FULL ADDER
SUM
FULL ADDER
46
47
48
49
50
51
52
53
54
55
56
40
57
FILE FORMATS
NMOSFET PMOSFET
N+ Poly 0.75 µm Aluminum
LVL 6 – P-LDD
LVL 1 – n-WELL
6000 Å
Field Oxide LVL 7 – N-LDD
p+ well N+ D/S LDD LDDP+ D/S n+ well
contact LVL 2 - ACTIVE
contact P-well N-well
Channel Stop
LVL 8 - P+ D/S
N-type Substrate 10 ohm-cm LVL 3 - STOP
POLY
ACTIVE P SELECT LVL 9 - N+ D/S
CC LVL 4 - PMOS VT
METAL LVL 8 - CC
LVL 5 - POLY
N SELECT
N-WELL 11 PHOTO
LEVELS LVL 9 - METAL
RIT ADVANCED CMOS
POLY
P SELECT LVL 4 - VTP
ACTIVE LVL 10 – P+D/S
CC
METAL
LVL 5 - VTN LVL 11 - CC
N SELECT
N-WELL
REFERENCES