EEEB273/ Electronics II - Analog IC Biasing and Active Loads (Part 2)

Analog Integrated Circuit (IC) biasing and active

loads (Part 2) – MOSFET Current Sources
Field-effect transistor IC’s are biased with current sources in the same way
as bipolar circuits.

Basic Two-Transistor MOSFET Current Source

• M1 is always biased in the

saturation region because the drain
and gate terminals are connected.
• Assuming λ = 0,

I REF = K n1 (VGS − VTN 1 )

2
(2.1)

which gives:
I REF (2.2)
VGS = VTN 1 +
K n1
Figure 1: Basic two-transistor
MOSFET current source. • Transistor M2 should also always
be biased in the saturation region
such that the load current is:

I O = K n 2 (VGS − VTN 2 )
2
(2.3)

• Hence, substituting eq. (2.2) into (2.3),

2
⎡ I ⎤ (2.4)
I O = K n 2 ⎢ REF + VTN 1 − VTN 2 ⎥
⎣ K n1 ⎦
• If M1 and M2 are identical transistors, then VTN1 = VTN2 and Kn1 =
Kn2. Hence, eq. (2.4) becomes:
I O = I REF
(2.5)
• However, if the transistors are matched except for the aspect ratios
(width-to-length ratio):
(W L )2
IO = ⋅I
(W L )1 REF (2.6)
controlled by the designer
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 EEEB273/ Electronics II - Analog IC Biasing and Active Loads (Part 2)

• Output resistance, ro:

o Taking into account the finite output resistance of both M1 and M2,
i.e. λ ≠ 0:
IO
=
(W L )2 ⋅ (1 + λVDS 2 ) (2.7)
I REF (W L )1 (1 + λVDS 1 )

o Normally λVDS1 (= λVGS1) << 1, and if (W L )2 = (W L )1 , then the

output resistance of the current source is:
−1
⎡ dI ⎤
= ro 2 = [λI O ] (2.8)
−1
Ro = ⎢ O ⎥
⎣ dV DS 2 ⎦

where ro2 = output resistance of the transistor M2.

As with BJT current sources, MOSFET current sources require a large

output resistance for excellent stability.

Reference Current

In BJT circuits, the reference current is generally established by the bias

voltages and resistor. However, MOSFETs can be configured to act like a
resistor. Hence, the reference current in MOSFET current mirrors is
established by using additional transistors.

In the current mirror of Figure 2,

M3 is diode-connected.
Transistors M1 and M3 are in series
(assume λ = 0):
IREF = ID1 = ID3
K n1 (VGS 1 − VTN 1 ) = K n 3 (VGS 3 − VTN 3 )
2 2

Therefore, by rearranging:

(W L )3 ⎛ (W L )3 ⎞⎟
VGS 1 = ⋅ VGS 3 + ⎜⎜1 − ⎟ ⋅ VTN
(W L )1 ⎝ (W L )1 ⎠
*
Figure 2: MOSFET current where it is assumed that VTN, μn and Cox are
source. identical in all transistors.

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From the circuit, VGS 1 + VGS 3 = V + − V − . Therefore, substituting this into *,

(W L )3 ⎛
⎜1 −
(W L )3 ⎞
⎟
(W L )1 ⎜ (W L )1 ⎟
VGS 1 = ⋅ (V − V ) + ⎝
+ − ⎠ ⋅V = V (2.9)
(W L )3 ⎛
⎜1 +
(W L )3 ⎞
⎟
TN GS 2

1+
(W L )1 ⎜
⎝ (W L )1 ⎟⎠

Finally, for λ = 0, the load current is given by:

k n' ⎛ W ⎞
= ⎜ ⎟ (VGS 2 − VTN )
2
I O = I D2 (2.10)
2 ⎝ L ⎠2

Hence, since the designer has control over the width-to-length ratios of the
transistors, there is considerable flexibility in the design of MOSFET current
sources.

**Design Example 10.8, Ex. 10.8

Improved Current Source Circuits

A) Cascode Current Mirror

• Ro is greater than that of the two-transistor circuit.

• Assumption: all the transistors are matched.
• Hence, IO ≅ IREF.

Figure 3: MOSFET cascode current mirror (Figures

L (a) and (b) are equivalent circuits of the cascode
current mirror for determining output resistance).

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Gate voltages of M2 and M4 are constant, which implies these terminals (K

and L in Figure 3) are signal ground, i.e. ac short circuit.

Figure 3(b) is the ac equivalent circuit for calculating the output resistance
for the cascode current source.

From Figure 3(b), summing currents at the output node yields:

⎛ V x − (− V gs 4 ) ⎞
I x = g mV gs 4 + ⎜⎜ ⎟⎟
⎝ ro 4 ⎠

and since V gs 4 = − I x ro 2 , the output resistance is given by:

Vx
RO = = ro 4 + ro 2 (1 + g m ro 4 ) ≅ g m ro 4 ro 2 (2.11)
Ix

Normally, g m ro 4 >> 1 the cascode output resistance is much larger

compared to that of the two-transistor current source.

Advantage: Increases current source stability with changes in output

voltage.

** Example 10.9, Ex. 10.9

B) Wilson Current Mirror

• VDS of M1 and M2 are not equal.

V DS 1 = VGS 2 + VGS 3
V DS 2 = VGS 2

• Since λ ≠ 0, IO / IREF is slightly

different from the aspect ratios.

Figure 4: MOSFET Wilson

current source.

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 EEEB273/ Electronics II - Analog IC Biasing and Active Loads (Part 2)

C) Modified Wilson Current Mirror

• Additional transistor M4.

• Hence, VDS of M1 and M2 are now

equal.

V DS 1 = VGS 2 + VGS 3 − VGS 4 = VGS 2 = V DS 2

• For constant IREF , VDS of M1, M2 and M4

are held constant.

Figure 5: Modified MOSFET

Wilson current source.

Primary advantage of both Wilson current mirror’s: INCREASE in

output resistance, i.e. further stabilises the load current IO.

Output resistance of Wilson current source: RO = g m ro 3 ro 2

Output Voltage Swing

The minimum output voltage, VO (min), of the current mirror influences

the maximum symmetrical output voltage swing of the load circuit
being biased.

The minimum output voltage for the two-

transistor current mirror (see Figure 1):

VO (min) = V − + VDS (sat) (2.12)

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 EEEB273/ Electronics II - Analog IC Biasing and Active Loads (Part 2)

For the cascode current mirror (see Figure 3):

VO (min) = V D 4 (min)
By definition: V D = VG − VGS + V DS

Therefore, VO (min) = VG 4 − VGS 4 + V DS 4 (sat)

From circuit, assuming matched transistors:

VG 4 = V − + VGS 1 + VGS 3
VGS 1 = VGS 2 = VGS 3 = VGS 4 = VGS

Substituting for VG4 and VGS4 into the VO(min):

VO (min) = V − + (VGS + V DS 4 (sat) ) (2.13)

Example: VGS = 0.75V , VTN = 0.50V . VDS (sat) = VGS − VTN = 0.25 V
• two-transistor current mirror: VO (min) = V − + 0.25V
• cascode current mirror: VO (min) = V − + 1.0V

Note: Increase in VO (min) means reduced maximum output voltage

swing of the load circuit, which is critical in low-power applications.

D) Wide-Swing Current Mirror

• Does not limit output
voltage swing.
• Maintains high output
resistance.
• All transistors identical
except for the different
width-to-length ratios (as
in Figure 6).
• M3 and M4 together act like a
single diode connected-
transistor to create VG3.
• With M4, VDS3 is matched to
VDS2.
Figure 6: Wide swing MOSFET
cascode current mirror.
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The minimum output voltage at drain of M1 is:

VO (min) = V D1 (min) = VG1 − VGS 1 + V DS 1 (sat)

From circuit: VG1 = VGS 5

M5 is 1/4th the size of M1 - M4: (VGS 5 − VTN ) = 2(VGSi − VTN ) ,
Therefore, the minimum output voltage is thus:
VO (min) = V D1 (min) = VG1 − VGS 1 + V DS 1 (sat)
= VGS 5 − VGS 1 + (VGS 1 − VTN )
= VGS 5 − VTN
(2.14)
VO (min) = 2(VGSi − VTN ) = 2V DSi (sat)

Bias-Independent Current Source

• PMOS devices are matched, hence

ID1 = ID2

• Therefore, for transistors M1 and

M2:
I D1 = I D 2
k n' ⎛W ⎞ k n' ⎛ W ⎞
⎜ ⎟ VGS 1 − VTN = ⎜ ⎟ (VGS 2 − VTN )
( )2 2

2 ⎝ L ⎠1 2 ⎝ L ⎠2

• Also, KVL at Loop 1:

VGS 2 = VGS 1 − I D 2 R .
Loop 1 • By substituting the latter equation
into the former and solving for R:

1 ⎛
⎜1 −
(W L )1 ⎞⎟ (2.15)
R=
Figure 7: Wide swing MOSFET
cascade current mirror. K n1 I D1 ⎜
⎝ (W L )2 ⎟⎠

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• R will establish ID1 = ID2 (which are independent of supply voltages

V+ and V- as long as M2 and M3 are biased in the saturation region)
• ID1 and ID2 then establishes VGS1 and VSG3
• VGS1 and VSG3 also be applied to M5 and M6 to establish the load
currents IO1 and IO2.

Therefore,

• Similar BJT bias-independent current mirror design exists but

will not be covered here.

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