METU-EEE EE 314-Digital Electronics Laboratory

2. NMOS AND BJT INVERTING CIRCUITS

I. INTRODUCTION

1. Objectives
In this experiment, the characteristics of the NMOS and BJT inverter circuits will be
analyzed and compared.

II. PRELIMINARY WORK

1. Read Chapter 1 and sections 4.1 and 4.2, and 17.1-17.3 of “Digital Integrated
Circuits” by T.A. Demassa and Z. Ciccone.
2. Consider the following NMOS inverter circuit, where K=0.5mA/V2 Vt=1.5V for the
NMOS transistor.

Figure 1-1. NMOS inverter circuit schematic.

Sketch the expected voltage transfer characteristic by calculating the output voltage (V o)
for Vin= 0, 1, 2, 3, 4, and 5 V.
3. Consider the circuit in Figure 1.1 and think about the rise and fall times of this inverter
circuit when a square wave signal is applied at the input. Answer these questions
based on your reasoning from the circuit.
i) Do you think that the rise time of the circuit depends on the magnitude of the
supply voltage, VDD?
ii) Does the rise time or the fall time depend on the values of the drain resistor and
the capacitance at the output?
iii) Does the rise time increase or decrease, if a resistor is connected in parallel to the
capacitance at the output?
iv) What are the parameters likely to determine the fall time?

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Vcc Vcc
Rise
Fall
RC RC
Vcc Vcc
Vout Vout
0 RB 0 RB
CL CL
Vin Vin

Figure 1-2. Schematics showing the rise and fall transitions for a basic BJT inverter.

4. Now, consider BJT inverter circuits in Figure 1.2; and estimate the circuit parameters
that will affect rise and fall times of a basic BJT inverter. If the BJT is turned on in any
of the following stages, you can assume that it stays in forward-active region
throughout the transitions.
Also, assume that the voltage changes will be roughly linear during the transitions.
While this is a gross assumption and the actual rise & fall times will be different from
estimated ones; it is nonetheless an instructive exercise to learn how and why rise, fall
and propagation delay times will change.
i) What is the operating state of the BJT during rise time? Assume that the input
signal changes instantly to low value, right before the transition.
ii) Continuing from the first step, what will the rise time depend on?
iii) Now, determine the operating state of the BJT during fall time. Again, assume
that the input switches instantaneously to high value, right before the transition.
iv) From part iii, determine the parameters that fall time will depend on.
v) Compare the dependencies and expressions you found for rise and fall times of
the inverter. Are there any discrepancies, and if so what are they?

5. Simulate the following circuit on any suitable SPICE simulator (such as LTSPICE,
MultiSim or Electronics Workbench) with K=0.5 mA/V2 and K=0.05 mA/V2 for the
MOSFET. Set Vt=1.5 V. To observe the transfer characteristics use DC Sweep option
of your simulator. Sweep V2 from 0 to 5V with 0.05V increments at each step. If you
are not familiar with DC sweep capabilities of SPICE simulators or SPICE simulators in
general; then you can find a good tutorial for LTSpice simulator at:
http://www.mems.eee.metu.edu.tr/courses/ee313/EE313_spice_tutorial.pdf

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METU-EEE EE 314-Digital Electronics Laboratory

Figure 1-3. Sample schematic diagram of the NMOS inverter in EWB.

For each K value, determine VOH, VOL, VIL, VIH and noise margins. Bring the print out
of DC Sweep output for each K and also the schematic. Comment on the
dependence of the inverter performance on K.

III. EXPERIMENT
In this experiment we will characterize the inverter circuits constructed with the n-channel
MOSFETs in the CD4007 MOS array chip. The chip includes 3 n-channel and 3 p-channel
enhancement mode MOSFETs as shown in Figure 3. The K and V t values for the n-channel
MOSFETs are measured to be approximately 0.5 mA/V2 and 1.5 V, respectively under zero
substrate reverse bias.

Figure 1-3. Pin diagram for CD4007 MOS array chip.

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Resistor Loaded NMOS Inverter

1. Measurement

Construct the circuit shown below. Note that, Pin 14 of CD4007 is connected to +25 V
output of the power supply and pin 7 is connected to ground.

Figure 1-4. EWB schematic for the resistor loaded NMOS inverter.

2. HP VEE Program for Measuring the Transfer Characteristic

i) Construct the following configuration on HP VEE by taking the following details

into consideration. We will use this configuration to measure the transfer
characteristic of the NMOS inverter under various conditions.

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Figure 1-5. HP VEE configuration.

ii) Plug & Play driver “vgs” controls the +6 V output of the power supply (connected
to the gate of the MOSFET). Set the current limit to 10 mA.
iii) Plug & Play Driver „vdd‟ controls the +25 V output of the power supply (connected
to the drain through the 10 K resistor). Set current limit to 100 mA.
iv) Plug & Play driver “voltmeter” controls the multimeter in DC voltage measuring
mode which measures the output (drain) voltage.
v) X vs Y plot displays the transfer characteristic (VD vs VG). Use a marker and
arrange the „Traces‟ section to have the trace plotted with symbols () only.
Create an Autoscale Control Input for this object and connect it to the sequence
output pin of the For Range Object controlling vdd. This will ensure that the plot is
autoscaled when the program ends.
vi) Save the program under the name “mosinvtr”.

3. Measuring the Transfer Characteristic

i) Turn the output of the power supply on and run the program constructed above.
Wait until the program is completed and observe the transfer characteristics on
the X vs Y Plot. Get a print out of the transfer characteristic.
ii) Find the following voltage levels when VDD=5 V (Use the marker and the zoom
facility).
 VOH: mimimum output high voltage
 VOL: maximum output low voltage
 VIH: minimum input voltage which provides a low output voltage
 VIL: maximum input voltage which provides a high output voltage

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iii) Calculate the noise margin of the inverter for VDD=5, 7.5 and 10 V. Which supply
voltage is better for protection from extraneous noise voltages that may alter the
output level?
iv) When VOL values for two different supply voltages are compared under the same
gate voltage, VOL seems to be larger for higher VDD. Why?
v) Estimate the resistance of the MOSFET when it is ON (the output is at the low
level).
vi) Now connect a 10 K resistor (RL) between the drain of the MOSFET and ground.
Run the HP VEE program and observe the transfer characteristic. Compare the
noise margins with those obtained without RL. Comment on the results.

4. Dynamic Response

In this part of the experiment, we will investigate the dependence of the dynamic
response of the inverter on load capacitance, load resistance and supply voltage.

i) Construct the circuit shown below.

Figure 1-6. EWB schematic of the circuit.

ii) Set the output impedance of the function generator to High Z. Set the waveform
to a square wave with 5 VPP amplitude, 2.5 V offset and 1 kHz frequency.
iii) Observe the input and output waveforms on the scope.
iv) Measure and record the rise and fall times of the inverter.
v) Measure and record the propagation delay times, PHL and PLH for the inverter.
vi) Connect a 100 pF capacitor between the drain of the MOSFET and ground.
Measure and record the rise and fall times and compare the results with those
measured without the capacitor. Comment on the results.
vii) Measure and record the rise and fall times under VDD=7.5 V and VDD=10 V.
Compare the results with those taken under VDD=5 V. Comment on the results.

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The rise time does not change significantly with increasing supply voltage. Why
not?
viii) Decrease the supply voltage to 5 V. Connect a 10 k resistor between the drain of
the MOSFET and ground and measure and record the rise and fall times of the
inverter. Compare the results with those obtained without the resistor. Why do the
rise and fall times decrease when this resistor is connected?

BJT Inverter

Construct the following BJT inverter circuit by using an npn BJT in the CA3046 BJT array
chip. Connect pin 13 to ground. Set the output of the function generator to High Z. Set
the waveform at the function generator output to a triangle wave with 5 V PP amplitude
and 2.5 V offset at a frequency of 1 kHz. Connect input to channel A1 and output to
channel A2 of the scope.

Figure 1-7. EWB schematic for the BJT inverter and the ping diagram for CA3046.

i) Observe the transfer characteristic of the inverter by using the scope in the X-Y
mode. Use the potentiometer to change the base resistance and observe the
change in the transfer characteristic by considering the noise margins. Compare
the noise margins with those of the NMOS inverter. Comment on the results.
ii) Change the waveform at the output of the function generator to a square wave
and observe the input and output signals on the scope. Set the potentiometer to 0
. Measure and record the rise and fall times. Compare the results with those of
the NMOS inverter. Now increase the potentiometer resistance and observe the
change in the rise and fall times. Comment on the results.
iii) Compare the overall performance of the BJT inverter with that of the NMOS
inverter.

IC LIST FOR EXPERIMENT 1

CA3046 BJT Array
CD4007 MOSFET Array

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