Digital Systems

7.
1 Frequency Counters
A frequency counter, being a digital instrument, is limited in its frequency range by the
speed of its logic circuitry. Today the state of the art in high-speed logic allows the
construction of counters with a frequency range of around 500 MHz. Continuing advances
in IC technology should extend this range beyond 1 GHz in the not-too-distant future.
The designer of an automatic counter must look to some form of down-conversion in order to
extend frequency measurement beyond 500 MHz. Four techniques are available today
to provide this down-conversion:
• Prescaling, with a range of 1.5 GHz;
• Heterodyne Converter. Frequency measurements as high as 20 GHz are fairly common.
• Transfer Oscillator, used in counters with ranges to 23 GHz;
• Harmonic Heterodyne Converter, a new technique which can provide
measurements
to 40 GHz.
7.1a Down-Conversion Techniques

Prescaling
Prescaling involves a simple division of the input frequency, resulting in a lower frequency
signal which can be counted in digital circuitry. The frequency measured by the counter
section is related to the input simply by the integer N. A display of the correct frequency
is accomplished either by multiplying the counter’s contents by N or by increasing the
counter’s gate time by a factor of N. Typically, N ranges from 2 to 16. Modern frequency
counters using this technique are capable of measuring up to 1.3 GHz. Recent
developments in solid-state technology might extend this range into the low microwave
range within a few years.
Heterodyne Converter
Heterodyne down-conversion centers about a mixer which beats the incoming microwave fre-
quency against a high-stability local oscillator signal, resulting in a difference frequency
which is within the conventional counter’s 500-MHz bandwidth.
Figure 7.1 is the block diagram of an automatic microwave counter using the heterodyne
down-
conversion technique. The down-converter section is enclosed by the dotted line.
Outside the
dotted line is the block diagram of a conventional counter, with the addition of a new
block called
the processor. The decision-making capability of a processor is necessary here in order
to lead the counter through its measurement algorithm. The high stability local oscillator
of Figure 7.2 is
generated by first multiplying the frequency of the instrument’s time base to a
convenient funda-
mental frequency (designated fin), typically 100 to 500 MHz. This fin is directed to a
harmonic
generator which produces a “comb line” of frequencies spaced at fin extending to the full
fre-
quency range of the counter. One line of this comb, designated Kfin, is then selected by
the micro-
wave filter and directed to the mixer. Emerging from the mixer is a video frequency equal
to
fx - Kfin. This video frequency is amplified and sent to the counter. The display shows the
sum of
the video frequency and Kfin, which is provided by the processor. (The processor stores
the value
of K, since it is in control of the microwave filter.)
The signal detector block in Figure 7.1 is necessary for determining the correct K value.
In practice, the processor will begin with K =1 and will “walk” the value of K through the
comb line until the signal detector determines that a video frequency is present. At this
point the acquisition routine is terminated and measurement can begin.
The remaining block in Figure 7.1 which has not been discussed is the automatic gain control
(AGC) circuit. This circuit provides a degree of noise immunity by desensitizing the video
amplifier such that only the strongest frequency components of the video signal will enter
the Schmitt
trigger and be counted.
A key ingredient in automating the heterodyne down-conversion process is the

microwave filter. Two filters used for this purpose are (1) a YIG filter, and (2) an array of
thin-film filters which are selected by PIN diode switches.
- Kf
fvideo fx in Schmitt Main Counting
Mixer Video Amp Trigger Gate Register
− Kf
Unknown Input (fx) fx in
Kfin dc
Amp
YIG/PIN Display
Switch Filter AGC
Amp Main Gate
FF
Signal
fin Detector
Harmonic Multiplier
Generator
Filter Processor
Control
Time Time Base

Base Dividers
Figure 7.1. Block diagram of the heterodyne down-conversion technique.
Transfer Oscillator
The transfer oscillator uses the technique of phase locking a low frequency oscillator
to the microwave input signal. The low frequency oscillator can then be measured in a
conventional counter, and all that remains to be accomplished is to determine the
harmonic relationship between that frequency and the input.
Figure 7.2 is the block diagram of an automated transfer oscillator. Once again, the
down conversion circuitry is contained within the dotted line.
The input signal at frequency fx is shown being phase-locked to a voltage controlled

oscillator (VCO 1) in the upper portion of the converter section. Once phase lock is
achieved, the relationship between the input and the VCO frequency is given by
fx = NF1 − Fif 1 (7.1)
where N is an integer.
The quadrature detector assures that lock occurs at NF1 - Fif1 and not NF1+ Fif1.
The lower sampler and portion of the converter section is used for determination of N.
By offsetting F1 by a known frequency, F0, the output of VCO 2 is given by
F2 = F 1 − F0 (7.2)
This signal is used to drive the lower sampler whose output frequency, Fif2, is given by
Fif2 = NF 2 - fx (7.3)
Hence,
Fif2 = Fif1 − NF0 (7.4)
This output from the lower sampler at Fif2 is mixed with Fif1 to generate NF0. N is then deter-
mined in a ratio counter with NF0 and F0 as inputs. Once determined, N is then used to
extend the time base while F1 is being measured. By offsetting the display by Fif1,
equation (7.1) is solved and the unknown frequency fx displayed.
Fif1 From Time Base

Sampler Video Amp
fx Fif
F1 REF
VCO 1 Phase Reference

Detector Oscillator
Amp
Power
fx Divider Quadrature
Detector
VCO 2 F0
fx F2 Fif2 Fif REF
NF0
Sampler Video
Amp 2 Mixer
Schmitt
Trigger Main Counting
Gate Register
Main Gate Display

FF
Time Time Base

Base Dividers N Counter
Figure 7.2. Block diagram of the transfer oscillator down-conversion technique.
Harmonic Heterodyne Converter

The harmonic heterodyne converter, as its name implies, is a hybrid of the previous two tech-
niques. A counter using this block diagram (Figure 7.3) will acquire the input microwave
frequency in the manner of the transfer oscillator, but it will then make frequency
measurements like a
heterodyne converter.
Figure 36 shows the input fx being directed to a sampler, with the resulting down-
converted video signal fif = fx - Nfs amplified and sent to the counter. The sampling
frequency fs is created by a processor-controlled synthesizer.
The acquisition routine for this down-converter consists of tuning the synthesizer fs until
the signal
detector finds a video signal fif of the appropriate frequency range (defined by the
bandpass filter).
Next, the harmonic number N must be determined, as in the transfer oscillator. One
method of
finding N is to use a second sampler loop, as with the transfer oscillator (Figure 7.2) or
similar
technique. A second method is to step the synthesizer back and forth between two
closely-spaced
frequencies and observe the differences in counter readings; it is then a simple task for
the proces-
sor to calculate N.
fif Schmitt
fx Sampler Video Amp Trigger
Main Gate Counting

Band-Pass FF Register
fs Filter
Time Base Display

Dividers
Signal
Synthesizer Detector
Time Base
Oscillator
Processor
Figure 7.3. Block diagram of the harmonic heterodyne down-conversion technique.
A frequency measurement is accomplished by the processor’s multiplying the known

synthesizer frequency fs by N, adding the result to the video frequency fif measured in
the counting register, and displaying the answer: fx = Nfs + fif. In this process the
harmonic heterodyne converter
resembles the heterodyne converter, since the sampler is effectively mixing the Nth
harmonic of a very stable source with the input to produce a video difference frequency.
The harmonic heterodyne converter has the potential to be constructed at a lower

cost than the previous two techniques because it can be designed with just one
microwave component (the
sampler) and the control, decisions, and calculations can be performed by a low-cost
microprocessor.
7.1b Comparison of Performance of the Down-Conversion Technique

In this section, we will briefly examine the performance trade-offs among the three down-
conversion techniques which allow measurements over 1.5 GHz: heterodyne
converter, transfer oscillator and harmonic heterodyne converter.
The performance criteria to be used for the comparison include the following:
• Measurement speed
• Accuracy
• Sensitivity and Dynamic Range
• Signal-to-Noise Ratio
• FM tolerance
• AM tolerance
• Amplitude Discrimination
Measurement Speed
The time required for a microwave counter to perform a measurement may be divided
into two
parts:
• Acquisition Time — The time necessary for the counter to detect the
microwave signal
and prepare to make a measurement: and
• Gate Time — The duration of the counter’s gate required to measure to a given resolution.
Accuracy
The accuracy of microwave counter measurements is limited by two factors:

• The −1 counter error.
• Time base errors.
For a gate time of one second, the transfer osciIlator is limited to about 1 • 10-8
resolution (for 100-MHz clock). The heterodyne and harmonic heterodyne converters are
limited to about
1 • 10-9, at which point the short-term instabilities of common crystal oscillators
become the limiting factor. With the higher stability of an oven oscillator, these two
converters are capable of resolving 1 • 10-10 at microwave frequencies.
Sensitivity and Dynamic Range
As shown in Figure 7.4, there is little difference in sensitivity specifications among the
three downconversion techniques. A good microwave counter will have sensitivity of
about -25 dBm for most measurements.
Input Level
+20 dBm
Maximum Measured Input
0 dBm
-20 dBm Sensitivity:
Harmonic Heterodyne Converter

HP 5340A Typical
Heterodyne Converter
-40 dBm
Transfer Oscillator
5 GHz 10 GHz 15 GHz 20 GHz
Figure 7.4. Available microwave counter sensitivity specifications. Maximum measured input (regardless
of
down-conversion technique) is typically +7 dBm, although some counters allow measurements to +20
dBm.
The dynamic range of a microwave counter is a measure of the separation of the

sensitivity specification and the highest level input signal which can be counted reliably. A
typical value for this
upper level is +7 dBm, as shown in Figure 7.4.
Signal-to-Noise Ratio
An important consideration in choosing a microwave counter is the signal-to-noise

environment of
the measurement. A transfer oscillator or harmonic heterodyne converter counter will be
capable
of measuring the signal if the peak carrier exceeds the noise floor by 20 dB. A typical
heterodyne
converter counter will require 40 dB or greater separation to allow accurate
measurement.
FM Tolerance
All modern microwave counters are capable of measuring today’s microwave sources
with their inherent incidental frequency modulation. In general, although the transfer
oscillator is capable of measuring microwave frequencies with all common forms of FM
modulation, the heterodyne and harmonic heterodyne have an advantage in the area of
FM tolerance.
AM Tolerance
A second form of modulation encountered during microwave measurements is amplitude

modulation. The heterodyne converter’s tolerance to amplitude modulation is limited by
its AGC circuitry when such a circuit is employed in the counter design. A practical
limitation of AM tolerance for the heterodyne converter is around 50 percent AM. The
transfer oscillator and the harmonic
heterodyne converter suffer no such limitations with respect to AM. Typically, they can
measure a carrier at a level of -10 dBm with 95 percent AM. The only requirement is that
the trough of the waveform be within the counter’s sensitivity specification.
Amplitude Discrimination
Frequently a microwave counter will be called upon to measure a signal in the

presence of other lower level signals. The ability to perform this measurement directly
is referred to as amplitude discrimination.
All modern microwave counters incorporate amplitude discrimination in their designs. This
capability is one of the key features of the transfer oscillator and harmonic heterodyne
converter.
These counters are typically capable of always finding the most prominent component of
the
spectrum, provided that it is at least 2 dB above nearby signals and at least 10 dB above
signals at
the far end of the counter’s frequency range. Figure 7.5 illustrates these measurement
capabilities.
2 dB (typical) 5 dB (typical) 10 dB (typical)
200 MHz 1 GHz 18 GHz
Figure 7.5. Amplitude discrimination capabilities of the transfer oscillator and harmonic heterodyne
converter.
Each drawing indicates the required level separation in order for the counter to distinguish the greater
signal.
The heterodyne converter is capable of amplitude discrimination of widely separated

signals, but for signals in the same frequency band it is limited by the AGC circuitry.
Typical AGC circuitry found in modern heterodyne converters provide discrimination
between signals which lie from 4 dB to 30 dB apart, located in the same band.
Summary of Comparison
A summary of the performance trade-offs based on the criteria discussed above is

presented in Figure 7.6. Bold type indicates that the technique enjoys a significant
performance advantage. It should be noted that these comparisons are made on the
basis of typical specifications; a comparison of the individual instruments may produce
different results in some categories.
Harmonic
Characteristic Heterodyne Converter Transfer Oscillator Heterodyne Converter
Frequency Range 20 GHz 23 GHz 40 GHz
Measurement Speed 150 ms acquisition 150 ms acquisition 350 ms acquisition

1/R gate N/R gate 1/R gate
Accuracy Time base limited Time base limited Time base limited
Sensitivity/ -30 dBm/35-50 dB -35 dBm/40 dB -30 dBm/35-50 dB
Dynamic Range
Signal-to-Noise Ratio 40 dB 20 dB 20 dB
FM Tolerance 30-40 MHz peak-peak 1-10 MHz peak-peak 10-50 MHz peak-peak
AM Tolerance Less than 50% Greater than 90% Greater than 90%
Amplitude 4-30 dB 2 -10 dB 2 -10 dB
Discrimination
Figure 7.6. Summary of the performance of the three principal microwave counter down-conversion techniques.
7.2 Analog-to-digital converter
4-channel stereo multiplexed analog-to-digital converter WM8775SEDS made by

Wolfson Microelectronics placed on X-Fi Fatal1ty Pro sound card
An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device which

converts continuous signals to discrete digital numbers. The reverse operation is
performed by a digital-to-analog converter (DAC).
Typically, an ADC is an electronic device that converts an input analog voltage (or
current) to a digital number proportional to the magnitude of the voltage or current.
However, some non-electronic or only partially electronic devices, such as rotary
encoders, can also be considered ADCs. The digital output may use different coding
schemes, such as binary, Gray code or two's complement binary.
7.2a Resolution
The resolution of the converter indicates the number of discrete values it can produce
over the range of analog values. The values are usually stored electronically in binary
form, so the resolution is usually expressed in bits. In consequence, the number of
discrete values available, or "levels", is usually a power of two. For example, an ADC
with a resolution of 8 bits can encode an analog input to one in 256 different levels,
8
since 2 = 256. The values can represent the ranges from 0 to 255 (i.e. unsigned
integer) or from -128 to 127 (i.e. signed integer), depending on the application.
Resolution can also be defined electrically, and expressed in volts. The voltage
resolution of an ADC is equal to its overall voltage measurement range divided by the
number of discrete intervals as in the formula:
Where:
Q is resolution in volts per step (volts per output code),

EFSR is the full scale voltage range = VRefHi − VRefLo,
M is the ADC's resolution in bits, and
N is the number of intervals, given by the number of available levels (output
codes), which is: N = 2M
Some examples may help:
• Example 1
o Full scale measurement range = 0 to 10 volts
o ADC resolution is 12 bits: 212 = 4096 quantization levels (codes)
o ADC voltage resolution is: (10V - 0V) / 4096 codes = 10V / 4096 codes
0.00244 volts/code 2.44 mV/code
• Example 2
o Full scale measurement range = -10 to +10 volts
o ADC voltage resolution is: (10V - (-10V)) / 16384 codes = 20V / 16384
codes 0.00122 volts/code 1.22 mV/code
• Example 3
o Full scale measurement range = 0 to 8 volts
o ADC voltage resolution is: (8 V − 0 V)/8 codes = 8 V/8 codes = 1
volts/code = 1000 mV/code
In practice, the smallest output code ("0" in an unsigned system) represents a voltage
range which is 0.5X of the ADC voltage resolution (Q)(meaning half-wide of the ADC
voltage Q ) while the largest output code represents a voltage range which is 1.5X of
the ADC voltage resolution (meaning 50% wider than the ADC voltage resolution). The
other N − 2 codes are all equal in width and represent the ADC voltage resolution (Q)
calculated above. Doing this centers the code on an input voltage that represents the
Mth division of the input voltage range. For example, in Example 3, with the 3-bit ADC
spanning an 8 V range, each of the N divisions would represent 1 V, except the 1st ("0"
code) which is 0.5 V wide, and the last ("7" code) which is 1.5 V wide. Doing this the "1"
code spans a voltage range from 0.5 to 1.5 V, the "2" code spans a voltage range from
1.5 to 2.5 V, etc. Thus, if the input signal is at 3/8ths of the full-scale voltage, then the
ADC outputs the "3" code, and will do so as long as the voltage stays within the range of
2.5/8ths and 3.5/8ths. This practice is called "Mid-Tread" operation. This type of ADC
can be modeled mathematically as:
The exception to this convention seems to be the Microchip PIC processor, where all M
steps are equal width. This practice is called "Mid-Rise with Offset" operation.
In practice, the useful resolution of a converter is limited by the best signal-to-noise

ratio that can be achieved for a digitized signal. An ADC can resolve a signal to only a
certain number of bits of resolution, called the "effective number of bits" (ENOB). One
effective bit of resolution changes the signal-to-noise ratio of the digitized signal by 6
dB, if the resolution is limited by the ADC. If a preamplifier has been used prior to A/D
conversion, the noise introduced by the amplifier can be an important contributing
factor towards the overall SNR.
7.2b Response type
Linear ADCs
Most ADCs are of a type known as linear[1] The term linear as used here means that
the range of the input values that map to each output value has a linear relationship
with the output value, i.e., that the output value k is used for the range of input values
from
m(k + b)
to
m(k + 1 + b),
where m and b are constants. Here b is typically 0 or −0.5. When b = 0, the ADC is
referred to as mid-rise, and when b = −0.5 it is referred to as mid-tread.
Non-linear ADCs
If the probability density function of a signal being digitized is uniform, then the signal-
to-noise ratio relative to the quantization noise is the best possible. Because this is
often not the case, it is usual to pass the signal through its cumulative distribution
function (CDF) before the quantization. This is good because the regions that are more
important get quantized with a better resolution. In the dequantization process, the
inverse CDF is needed.
This is the same principle behind the companders used in some tape-recorders and
other communication systems, and is related to entropy maximization.
For example, a voice signal has a Laplacian distribution. This means that the region
around the lowest levels, near 0, carries more information than the regions with higher
amplitudes. Because of this, logarithmic ADCs are very common in voice
communication systems to increase the dynamic range of the representable values
while retaining fine-granular fidelity in the low-amplitude region.
An eight-bit A-law or the μ-law logarithmic ADC covers the wide dynamic range and has
a high resolution in the critical low-amplitude region, that would otherwise require a 12-
bit linear ADC.
7.2c Accuracy
An ADC has several sources of errors. Quantization error and (assuming the ADC is
intended to be linear) non-linearity is intrinsic to any analog-to-digital conversion. There
is also a so-called aperture error which is due to a clock jitter and is revealed when
digitizing a time-variant signal (not a constant value).
These errors are measured in a unit called the LSB, which is an abbreviation for least
significant bit. In the above example of an eight-bit ADC, an error of one LSB is 1/256 of
the full signal range, or about 0.4%.
7.2d Quantization error
Quantization error is due to the finite resolution of the ADC, and is an unavoidable
imperfection in all types of ADC. The magnitude of the quantization error at the
sampling instant is between zero and half of one LSB.
In the general case, the original signal is much larger than one LSB. When this happens,
the quantization error is not correlated with the signal, and has a uniform distribution.
Its RMS value is the standard deviation of this distribution, given by
In the eight-bit ADC example, this represents 0.113% of the full signal range.
At lower levels the quantizing error becomes dependent of the input signal, resulting in
distortion. This distortion is created after the anti-aliasing filter, and if these distortions
are above 1/2 the sample rate they will alias back into the audio band. In order to make
the quantizing error independent of the input signal, noise with an amplitude of 1
quantization step is added to the signal. This slightly reduces signal to noise ratio, but
completely eliminates the distortion. It is known as dither.
Non-linearity
All ADCs suffer from non-linearity errors caused by their physical imperfections,
resulting in their output to deviate from a linear function (or some other function, in the
case of a deliberately non-linear ADC) of their input. These errors can sometimes be
mitigated by calibration, or prevented by testing.
Important parameters for linearity are integral non-linearity (INL) and differential non-
linearity (DNL). These non-linearities reduce the dynamic range of the signals that can
be digitized by the ADC, also reducing the effective resolution of the ADC.
Aperture error
Imagine that we are digitizing a sine wavex(t) = Asin(2πf0t). Provided that the
actual sampling time uncertainty due to the clock jitter is Δt, the error caused by this
phenomenon can be estimated as .
One can see that the error is relatively small at low frequencies, but can become
significant at high frequencies.This effect can be ignored if it is relatively small as
compared with quantizing error. Jitter requirements can be calculated using the
following formula: , where q is a number of ADC bits.

input frequency
ADC
resolution
in bit
1 Hz 44.1 kHz 192 kHz 1 MHz 10 MHz 100 MHz 1 GHz
8 1243 µs 28.2 ns 6.48 ns 1.24 ns 124 ps 12.4 ps 1.24 ps
10 311 µs 7.05 ns 1.62 ns 311 ps 31.1 ps 3.11 ps 0.31 ps
12 77.7 µs 1.76 ns 405 ps 77.7 ps 7.77 ps 0.78 ps 0.08 ps
14 19.4 µs 441 ps 101 ps 19.4 ps 1.94 ps 0.19 ps 0.02 ps
16 4.86 µs 110 ps 25.3 ps 4.86 ps 0.49 ps 0.05 ps –
18 1.21 µs 27.5 ps 6.32 ps 1.21 ps 0.12 ps – –
20 304 ns 6.88 ps 1.58 ps 0.16 ps – – –
24 19.0 ns 0.43 ps 0.10 ps – – – –
32 74.1 ps – – – – – –
This table shows, for example, that it is not worth using a precise 24-bit ADC for sound
recording if there is not an ultra low jitter clock. One should consider taking this
phenomenon into account before choosing an ADC.
7.2e Sampling rate

The analog signal is continuous in time and it is necessary to convert this to a flow of
digital values. It is therefore required to define the rate at which new digital values are
sampled from the analog signal. The rate of new values is called the sampling rate or
sampling frequency of the converter.
A continuously varying bandlimited signal can be sampled (that is, the signal values at
intervals of time T, the sampling time, are measured and stored) and then the original
signal can be exactly reproduced from the discrete-time values by an interpolation
formula. The accuracy is limited by quantization error. However, this faithful
reproduction is only possible if the sampling rate is higher than twice the highest
frequency of the signal. This is essentially what is embodied in the Shannon-Nyquist
sampling theorem.
Since a practical ADC cannot make an instantaneous conversion, the input value must
necessarily be held constant during the time that the converter performs a conversion
(called the conversion time). An input circuit called a sample and hold performs this
task—in most cases by using a capacitor to store the analog voltage at the input, and
using an electronic switch or gate to disconnect the capacitor from the input. Many ADC
integrated circuits include the sample and hold subsystem internally.
7.2f Aliasing
All ADCs work by sampling their input at discrete intervals of time. Their output is
therefore an incomplete picture of the behaviour of the input. There is no way of
knowing, by looking at the output, what the input was doing between one sampling
instant and the next. If the input is known to be changing slowly compared to the
sampling rate, then it can be assumed that the value of the signal between two sample
instants was somewhere between the two sampled values. If, however, the input signal
is changing rapidly compared to the sample rate, then this assumption is not valid.
If the digital values produced by the ADC are, at some later stage in the system,
converted back to analog values by a digital to analog converter or DAC, it is desirable
that the output of the DAC be a faithful representation of the original signal. If the input
signal is changing much faster than the sample rate, then this will not be the case, and
spurious signals called aliases will be produced at the output of the DAC. The frequency
of the aliased signal is the difference between the signal frequency and the sampling
rate. For example, a 2 kHz sine wave being sampled at 1.5 kHz would be reconstructed
as a 500 Hz sine wave. This problem is called aliasing.
To avoid aliasing, the input to an ADC must be low-pass filtered to remove frequencies
above half the sampling rate. This filter is called an anti-aliasing filter, and is essential
for a practical ADC system that is applied to analog signals with higher frequency
content.
Although aliasing in most systems is unwanted, it should also be noted that it can be
exploited to provide simultaneous down-mixing of a band-limited high frequency signal
(see undersampling and frequency mixer).
7.2g Dither
In A to D converters, performance can usually be improved using dither. This is a very
small amount of random noise (white noise) which is added to the input before
conversion. Its amplitude is set to be about half of the least significant bit. Its effect is to
cause the state of the LSB to randomly oscillate between 0 and 1 in the presence of
very low levels of input, rather than sticking at a fixed value. Rather than the signal
simply getting cut off altogether at this low level (which is only being quantized to a
resolution of 1 bit), it extends the effective range of signals that the A to D converter
can convert, at the expense of a slight increase in noise - effectively the quantization
error is diffused across a series of noise values which is far less objectionable than a
hard cutoff. The result is an accurate representation of the signal over time. A suitable
filter at the output of the system can thus recover this small signal variation.
An audio signal of very low level (with respect to the bit depth of the ADC) sampled
without dither sounds extremely distorted and unpleasant. Without dither the low level
always yields a '1' from the A to D. With dithering, the true level of the audio is still
recorded as a series of values over time, rather than a series of separate bits at one
instant in time.
A virtually identical process, also called dither or dithering, is often used when
quantizing photographic images to a fewer number of bits per pixel—the image
becomes noisier but to the eye looks far more realistic than the quantized image, which
otherwise becomes banded. This analogous process may help to visualize the effect of
dither on an analogue audio signal that is converted to digital.
Dithering is also used in integrating systems such as electricity meters. Since the values
are added together, the dithering produces results that are more exact than the LSB of
the analog-to-digital converter.
Note that dither can only increase the resolution of a sampler, it cannot improve the
linearity, and thus accuracy does not necessarily improve.
7.2h Oversampling
Usually, signals are sampled at the minimum rate required, for economy, with the result
that the quantization noise introduced is white noise spread over the whole pass band
of the converter. If a signal is sampled at a rate much higher than the Nyquist
frequency and then digitally filtered to limit it to the signal bandwidth then there are 3
main advantages:
• digital filters can have better properties (sharper rolloff, phase) than analogue
filters, so a sharper anti-aliasing filter can be realised and then the signal can be
downsampled giving a better result
• a 20 bit ADC can be made to act as a 24 bit ADC with 256× oversampling
• the signal-to-noise ratio due to quantization noise will be higher than if the
whole available band had been used. With this technique, it is possible to obtain
an effective resolution larger than that provided by the converter alone
7.2i Relative speed and precision

The speed of an ADC varies by type. The Wilkinson ADC is limited by the clock rate
which is processable by current digital circuits. Currently, frequencies up to 300 MHz
are possible. The conversion time is directly proportional to the number of channels. For
a successive approximation ADC, the conversion time scales with the logarithm of the
number of channels. Thus for a large number of channels, it is possible that the
successive approximation ADC is faster than the Wilkinson. However, the time
consuming steps in the Wilkinson are digital, while those in the successive
approximation are analog. Since analog is inherently slower than digital, as the number
of channels increases, the time required also increases. Thus there are competing
processes at work. Flash ADCs are certainly the fastest type of the three. The
conversion is basically performed in a single parallel step. For an 8-bit unit, conversion
takes place in a few tens of nanoseconds.
There is, as expected, somewhat of a trade off between speed and precision. Flash
ADCs have drifts and uncertainties associated with the comparator levels, which lead to
poor uniformity in channel width. Flash ADCs have a resulting poor linearity. For
successive approximation ADCs, poor linearity is also apparent, but less so than for
flash ADCs. Here, non-linearity arises from accumulating errors from the subtraction
processes. Wilkinson ADCs are the best of the three. These have the best differential
non-linearity. The other types require channel smoothing in order to achieve the level of
the Wilkinson.
The sliding scale principle

The sliding scale or randomizing method can be employed to greatly improve the
channel width uniformity and differential linearity of any type of ADC, but especially
flash and successive approximation ADCs. Under normal conditions, a pulse of a
particular amplitude is always converted to a certain channel number. The problem lies
in that channels are not always of uniform width, and the differential linearity decreases
proportionally with the divergence from the average width. The sliding scale principle
uses an averaging effect to overcome this phenomenon. A random, but known analog
voltage is added to the input pulse. It is then converted to digital form, and the
equivalent digital version is subtracted, thus restoring it to its original value. The
advantage is that the conversion has taken place at a random point. The statistical
distribution of the final channel numbers is decided by a weighted average over a
region of the range of the ADC. This in turn desensitizes it to the width of any given
channel.
7.2j ADC structures

These are the most common ways of implementing an electronic ADC:
• A direct conversion ADC or flash ADC has a bank of comparators sampling the
input signal in parallel, each firing for their decoded voltage range. The
comparator bank feeds a logic circuit that generates a code for each voltage
range. Direct conversion is very fast, capable of gigahertz sampling rates, but
usually has only 8 bits of resolution or fewer, since the number of comparators
needed, 2N - 1, doubles with each additional bit, requiring a large expensive
circuit. ADCs of this type have a large die size, a high input capacitance, high
power dissipation, and are prone to produce glitches on the output (by
outputting an out-of-sequence code). Scaling to newer submicrometre
technologies does not help as the device mismatch is the dominant design
limitation. They are often used for video, wideband communications or other fast
signals in optical storage.
• A successive-approximation ADC uses a comparator to reject ranges of voltages,
eventually settling on a final voltage range. Successive approximation works by
constantly comparing the input voltage to the output of an internal digital to
analog converter (DAC, fed by the current value of the approximation) until the
best approximation is achieved. At each step in this process, a binary value of
the approximation is stored in a successive approximation register (SAR). The
SAR uses a reference voltage (which is the largest signal the ADC is to convert)
for comparisons. For example if the input voltage is 60 V and the reference
voltage is 100 V, in the 1st clock cycle, 60 V is compared to 50 V (the reference,
divided by two. This is the voltage at the output of the internal DAC when the
input is a '1' followed by zeros), and the voltage from the comparator is positive
(or '1') (because 60 V is greater than 50 V). At this point the first binary digit
(MSB) is set to a '1'. In the 2nd clock cycle the input voltage is compared to 75 V
(being halfway between 100 and 50 V: This is the output of the internal DAC
when its input is '11' followed by zeros) because 60 V is less than 75 V, the
comparator output is now negative (or '0'). The second binary digit is therefore
set to a '0'. In the 3rd clock cycle, the input voltage is compared with 62.5 V
(halfway between 50 V and 75 V: This is the output of the internal DAC when its
input is '101' followed by zeros). The output of the comparator is negative or '0'
(because 60 V is less than 62.5 V) so the third binary digit is set to a 0. The
fourth clock cycle similarly results in the fourth digit being a '1' (60 V is greater
than 56.25 V, the DAC output for '1001' followed by zeros). The result of this
would be in the binary form 1001. This is also called bit-weighting conversion,
and is similar to a binary search. The analogue value is rounded to the nearest
binary value below, meaning this converter type is mid-rise (see above).
Because the approximations are successive (not simultaneous), the conversion
takes one clock-cycle for each bit of resolution desired. The clock frequency
must be equal to the sampling frequency multiplied by the number of bits of
resolution desired. For example, to sample audio at 44.1 kHz with 32 bit
resolution, a clock frequency of over 1.4 MHz would be required. ADCs of this
type have good resolutions and quite wide ranges. They are more complex than
some other designs.
• A ramp-compare ADC produces a saw-tooth signal that ramps up, then quickly
falls to zero. When the ramp starts, a timer starts counting. When the ramp
voltage matches the input, a comparator fires, and the timer's value is recorded.
Timed ramp converters require the least number of transistors. The ramp time is
sensitive to temperature because the circuit generating the ramp is often just
some simple oscillator. There are two solutions: use a clocked counter driving a
DAC and then use the comparator to preserve the counter's value, or calibrate
the timed ramp. A special advantage of the ramp-compare system is that
comparing a second signal just requires another comparator, and another
register to store the voltage value. A very simple (non-linear) ramp-converter
can be implemented with a microcontroller and one resistor and capacitor [2].
Vice versa a filled capacitor can be taken from an integrator, time-to-amplitude
converter, phase detector, sample and hold circuit, or peak and hold circuit and
discharged. This has the advantage that a slow comparator cannot be disturbed
by fast input changes.
• The Wilkinson ADC was designed by D. H. Wilkinson in 1950. The Wilkinson ADC
is based on the comparison of an input voltage with that produced by a charging
capacitor. The capacitor is allowed to charge until its voltage is equal to the
amplitude of the input pulse. (A comparator determines when this condition has
been reached.) Then, the capacitor is allowed to discharge linearly, which
produces a ramp voltage. At the point when the capacitor begins to discharge, a
gate pulse is initiated. The gate pulse remains on until the capacitor is
completely discharged. Thus the duration of the gate pulse is directly
proportional to the amplitude of the input pulse. This gate pulse operates a
linear gate which receives pulses from a high-frequency oscillator clock. While
the gate is open, a discrete number of clock pulses pass through the linear gate
and are counted by the address register. The time the linear gate is open is
proportional to the amplitude of the input pulse, thus the number of clock pulses
recorded in the address register is proportional also. Alternatively, the charging
of the capacitor could be monitored, rather than the discharge. [3][4]
• An integrating ADC (also dual-slope or multi-slope ADC) applies the unknown
input voltage to the input of an integrator and allows the voltage to ramp for a
fixed time period (the run-up period). Then a known reference voltage of
opposite polarity is applied to the integrator and is allowed to ramp until the
integrator output returns to zero (the run-down period). The input voltage is
computed as a function of the reference voltage, the constant run-up time
period, and the measured run-down time period. The run-down time
measurement is usually made in units of the converter's clock, so longer
integration times allow for higher resolutions. Likewise, the speed of the
converter can be improved by sacrificing resolution. Converters of this type (or
variations on the concept) are used in most digital voltmeters for their linearity
and flexibility.
• A delta-encoded ADC or Counter-ramp has an up-down counter that feeds a
digital to analog converter (DAC). The input signal and the DAC both go to a
comparator. The comparator controls the counter. The circuit uses negative
feedback from the comparator to adjust the counter until the DAC's output is
close enough to the input signal. The number is read from the counter. Delta
converters have very wide ranges, and high resolution, but the conversion time
is dependent on the input signal level, though it will always have a guaranteed
worst-case. Delta converters are often very good choices to read real-world
signals. Most signals from physical systems do not change abruptly. Some
converters combine the delta and successive approximation approaches; this
works especially well when high frequencies are known to be small in
magnitude.
• A pipeline ADC (also called subranging quantizer) uses two or more steps of
subranging. First, a coarse conversion is done. In a second step, the difference
to the input signal is determined with a digital to analog converter (DAC). This
difference is then converted finer, and the results are combined in a last step.
This can be considered a refinement of the successive approximation ADC
wherein the feedback reference signal consists of the interim conversion of a
whole range of bits (for example, four bits) rather than just the next-most-
significant bit. By combining the merits of the successive approximation and
flash ADCs this type is fast, has a high resolution, and only requires a small die
size.
• A Sigma-Delta ADC (also known as a Delta-Sigma ADC) oversamples the desired
signal by a large factor and filters the desired signal band. Generally a smaller
number of bits than required are converted using a Flash ADC after the Filter.
The resulting signal, along with the error generated by the discrete levels of the
Flash, is fed back and subtracted from the input to the filter. This negative
feedback has the effect of noise shaping the error due to the Flash so that it
does not appear in the desired signal frequencies. A digital filter (decimation
filter) follows the ADC which reduces the sampling rate, filters off unwanted
noise signal and increases the resolution of the output. (sigma-delta modulation,
also called delta-sigma modulation)
• A Time Interleaved ADC uses M parallel ADCs where each ADC sample data
every M:th cycle of the effective sample clock. This result in that the sample rate
is increased M times compared to what each individual ADC can manage. In
practice the individual differences between the M ADCs degrade the overall
performance reducing the SFDR. However, technologies exist to correct for
these time-interleaving mismatch errors.
• There can be other ADCs that use a combination of electronics and other
technologies:
• A Time-stretch analog-to-digital converter (TS-ADC) digitizes a very wide
bandwidth analog signal, that cannot be digitized by a conventional electronic
ADC, by time-stretching the signal prior to digitization. It commonly uses a
photonic preprocessor frontend to time-stretch the signal, which effectively
slows the signal down in time and compresses its bandwidth. As a result, an
electronic backend ADC, that would have been too slow to capture the original
signal, can now capture this slowed down signal. For continuous capture of the
signal, the frontend also divides the signal into multiple segments in addition to
time-stretching. Each segment is individually digitized by a separate electronic
ADC. Finally, a digital signal processor rearranges the samples and removes any
distortions added by the frontend to yield the binary data that is the digital
representation of the original analog signal.
7.2k Commercial analog-to-digital converters
These are usually integrated circuits.
Most converters sample with 6 to 24 bits of resolution, and produce fewer than 1
megasample per second. Thermal noise generated by passive components such as
resistors masks the measurement when higher resolution is desired. For audio
applications and in room temperatures, such noise is usually a little less than 1 μV
(microvolt) of white noise. If the Most Significant Bit corresponds to a standard 2 volts of
output signal, this translates to a noise-limited performance that is less than 20~21
bits, and obviates the need for any dithering. Mega- and gigasample per second
converters are available, though (Feb 2002). Megasample converters are required in
digital video cameras, video capture cards, and TV tuner cards to convert full-speed
analog video to digital video files. Commercial converters usually have ±0.5 to ±1.5
LSB error in their output.
In many cases the most expensive part of an integrated circuit is the pins, because they
make the package larger, and each pin has to be connected to the integrated circuit's
silicon. To save pins, it's common for slow ADCs to send their data one bit at a time over
a serial interface to the computer, with the next bit coming out when a clock signal
changes state, say from zero to 5V. This saves quite a few pins on the ADC package,
and in many cases, does not make the overall design any more complex. (Even
microprocessors which use memory-mapped IO only need a few bits of a port to
implement a serial bus to an ADC.)
Commercial ADCs often have several inputs that feed the same converter, usually
through an analog multiplexer. Different models of ADC may include sample and hold
circuits, instrumentation amplifiers or differential inputs, where the quantity measured
is the difference between two voltages.
Applications
Application to music recording
ADCs are integral to current music reproduction technology. Since much music
production is done on computers, when an analog recording is used, an ADC is needed
to create the PCM data stream that goes onto a compact disc or digital music file.
The current crop of AD converters utilized in music can sample at rates up to 192
kilohertz. Many people[citation needed] in the business consider this an overkill and
pure marketing hype, due to the Nyquist-Shannon sampling theorem. Simply put, they
say[citation needed] the analog waveform does not have enough information in it to
necessitate such high sampling rates, and typical recording techniques for high-fidelity
audio are usually sampled at either 44.1 kHz (the standard for CD) or 48 kHz
(commonly used for radio/TV broadcast applications). However, this kind of bandwidth
headroom allows the use of cheaper or faster anti-aliasing filters of less severe filtering
slopes. The proponents of oversampling assert that such shallower anti-aliasing filters
produce less deleterious effects on sound quality, exactly because of their gentler
slopes. Others prefer entirely filterless AD conversion, arguing that aliasing is less
detrimental to sound perception than pre-conversion brickwall filtering. Considerable
literature exists on these matters, but commercial considerations often play a
significant role. Most[citation needed] high-profile recording studios record in 24-
bit/192-176.4 kHz PCM or in DSD formats, and then downsample or decimate the signal
for Red-Book CD production.
Other applications
AD converters are used virtually everywhere where an analog signal has to be
processed, stored, or transported in digital form. Fast video ADCs are used, for example,
in TV tuner cards. Slow on-chip 8, 10, 12, or 16 bit ADCs are common in
microcontrollers. Very fast ADCs are needed in digital oscilloscopes, and are crucial for
new applications like software defined radio.
Electrical Symbol
7.3 Digital-to-analog converter
8-channel digital-to-analog converter Cirrus Logic CS4382 placed on Sound Blaster X-Fi
Fatal1ty
In electronics, a digital-to-analog converter (DAC or D-to-A) is a device for converting a

digital (usually binary) code to an analog signal (current, voltage or electric charge).
An analog-to-digital converter (ADC) performs the reverse operation.
7.3a Basic ideal operation
Ideally sampled signal. Signal of a typical interpolating DAC output

A DAC converts an abstract finite-precision number (usually a fixed-point binary
number) into a concrete physical quantity (e.g., a voltage or a pressure). In particular,
DACs are often used to convert finite-precision time series data to a continually-varying
physical signal.
A typical DAC converts the abstract numbers into a concrete sequence of impulses that
are then processed by a reconstruction filter using some form of interpolation to fill in
data between the impulses. Other DAC methods (e.g., methods based on Delta-sigma
modulation) produce a pulse-density modulated signal that can then be filtered in a
similar way to produce a smoothly-varying signal.
By the Nyquist–Shannon sampling theorem, sampled data can be reconstructed
perfectly provided that its bandwidth meets certain requirements (e.g., a baseband
signal with bandwidth less than the Nyquist frequency). However, even with an ideal
reconstruction filter, digital sampling introduces quantization error that makes perfect
reconstruction practically impossible. Increasing the digital resolution (i.e., increasing
the number of bits used in each sample) or introducing sampling dither can reduce this
error.
7.3b Practical operation

Instead of impulses, usually the sequence of numbers update the analogue voltage at
uniform sampling intervals.
These numbers are written to the DAC, typically with a clock signal that causes each
number to be latched in sequence, at which time the DAC output voltage changes
rapidly from the previous value to the value represented by the currently latched
number. The effect of this is that the output voltage is held in time at the current value
until the next input number is latched resulting in a piecewise constant or 'staircase'
shaped output. This is equivalent to a zero-order hold operation and has an effect on
the frequency response of the reconstructed signal.
Piecewise constant signal typical of a zero-order (non-interpolating) DAC output.

The fact that practical DACs output a sequence of piecewise constant values or
rectangular pulses would cause multiple harmonics above the nyquist frequency. These
are typically removed with a low pass filter acting as a reconstruction filter.
However, this filter means that there is an inherent effect of the zero-order hold on the
effective frequency response of the DAC resulting in a mild roll-off of gain at the higher
frequencies (often a 3.9224 dB loss at the Nyquist frequency) and depending on the
filter, phase distortion. Not all DACs have a zero order response however. This high-
frequency roll-off is the output characteristic of the DAC, and is not an inherent property
of the sampled data.
7.3c Applications
7.3c1 Audio
Top-loading CD player and external digital-to-analog converter.

Most modern audio signals are stored in digital form (for example MP3s and CDs) and in
order to be heard through speakers they must be converted into an analog signal. DACs
are therefore found in CD players, digital music players, and PC sound cards.
Specialist stand-alone DACs can also be found in high-end hi-fi systems. These normally
take the digital output of a CD player (or dedicated transport) and convert the signal
into a line-level output that can then be fed into a pre-amplifier stage.
Similar digital-to-analog converters can be found in digital speakers such as USB
speakers, and in sound cards.
7.3c2 Video
Video signals from a digital source, such as a computer, must be converted to analog
form if they are to be displayed on an analog monitor. As of 2007, analog inputs are
more commonly used than digital, but this may change as flat panel displays with DVI
and/or HDMI connections become more widespread. A video DAC is, however,
incorporated in any Digital Video Player with analog outputs. The DAC is usually
integrated with some memory (RAM), which contains conversion tables for gamma
correction, contrast and brightness, to make a device called a RAMDAC.
A device that is distantly related to the DAC is the digitally controlled potentiometer,
used to control an analog signal digitally.
7.3d DAC types

The most common types of electronic DACs are:
the Pulse Width Modulator, the simplest DAC type. A stable current or voltage is
switched into a low pass analog filter with a duration determined by the digital input
code. This technique is often used for electric motor speed control, and is now
becoming common in high-fidelity audio.
Oversampling DACs or Interpolating DACs such as the Delta-Sigma DAC, use a pulse
density conversion technique. The oversampling technique allows for the use of a lower
resolution DAC internally. A simple 1-bit DAC is often chosen because the oversampled
result is inherently linear. The DAC is driven with a pulse density modulated signal,
created with the use of a low-pass filter, step nonlinearity (the actual 1-bit DAC), and
negative feedback loop, in a technique called delta-sigma modulation. This results in an
effective high-pass filter acting on the quantization (signal processing) noise, thus
steering this noise out of the low frequencies of interest into the high frequencies of
little interest, which is called noise shaping (very high frequencies because of the
oversampling). The quantization noise at these high frequencies are removed or greatly
attenuated by use of an analog low-pass filter at the output (sometimes a simple RC
low-pass circuit is sufficient). Most very high resolution DACs (greater than 16 bits) are
of this type due to its high linearity and low cost. Higher oversampling rates can either
relax the specifications of the output low-pass filter and enable further suppression of
quantization noise. Speeds of greater than 100 thousand samples per second (for
example, 192kHz) and resolutions of 24 bits are attainable with Delta-Sigma DACs. A
short comparison with pulse width modulation shows that a 1-bit DAC with a simple
first-order integrator would have to run at 3 THz (which is physically unrealizable) to
achieve 24 meaningful bits of resolution, requiring a higher order low-pass filter in the
noise-shaping loop. A single integrator is a low pass filter with a frequency response
inversely proportional to frequency and using one such integrator in the noise-shaping
loop is a first order delta-sigma modulator. Multiple higher order topologies (such as
MASH) are used to achieve higher degrees of noise-shaping with a stable topology.
the Binary Weighted DAC, which contains one resistor or current source for each bit of
the DAC connected to a summing point. These precise voltages or currents sum to the
correct output value. This is one of the fastest conversion methods but suffers from
poor accuracy because of the high precision required for each individual voltage or
current. Such high-precision resistors and current-sources are expensive, so this type of
converter is usually limited to 8-bit resolution or less.
the R-2R ladder DAC, which is a binary weighted DAC that uses a repeating cascaded
structure of resistor values R and 2R. This improves the precision due to the relative
ease of producing equal valued matched resistors (or current sources). However, wide
converters perform slowly due to increasingly large RC-constants for each added R-2R
link.
the Thermometer coded DAC, which contains an equal resistor or current source
segment for each possible value of DAC output. An 8-bit thermometer DAC would have
255 segments, and a 16-bit thermometer DAC would have 65,535 segments. This is
perhaps the fastest and highest precision DAC architecture but at the expense of high
cost. Conversion speeds of >1 billion samples per second have been reached with this
type of DAC.
Hybrid DACs, which use a combination of the above techniques in a single converter.
Most DAC integrated circuits are of this type due to the difficulty of getting low cost,
high speed and high precision in one device.
the Segmented DAC, which combines the thermometer coded principle for the most
significant bits and the binary weighted principle for the least significant bits. In this
way, a compromise is obtained between precision (by the use of the thermometer
coded principle) and number of resistors or current sources (by the use of the binary
weighted principle). The full binary weighted design means 0% segmentation, the full
thermometer coded design means 100% segmentation.
7.3e DAC performance

DACs are at the beginning of the analog signal chain, which makes them very important
to system performance. The most important characteristics of these devices are:
Resolution: This is the number of possible output levels the DAC is designed to
reproduce. This is usually stated as the number of bits it uses, which is the base two
logarithm of the number of levels. For instance a 1 bit DAC is designed to reproduce 2
(21) levels while an 8 bit DAC is designed for 256 (28) levels. Resolution is related to the
Effective Number of Bits (ENOB) which is a measurement of the actual resolution
attained by the DAC.
Maximum sampling frequency: This is a measurement of the maximum speed at which
the DACs circuitry can operate and still produce the correct output. As stated in the
Nyquist–Shannon sampling theorem, a signal must be sampled at over twice the
frequency of the desired signal. For instance, to reproduce signals in all the audible
spectrum, which includes frequencies of up to 20 kHz, it is necessary to use DACs that
operate at over 40 kHz. The CD standard samples audio at 44.1 kHz, thus DACs of this
frequency are often used. A common frequency in cheap computer sound cards is 48
kHz – many work at only this frequency, offering the use of other sample rates only
through (often poor) internal resampling.
Monotonicity: This refers to the ability of DACs analog output to increase with an
increase in digital code or the converse. This characteristic is very important for DACs
used as a low frequency signal source or as a digitally programmable trim element.
THD+N: This is a measurement of the distortion and noise introduced to the signal by
the DAC. It is expressed as a percentage of the total power of unwanted harmonic
distortion and noise that accompany the desired signal. This is a very important DAC
characteristic for dynamic and small signal DAC applications.
Dynamic range: This is a measurement of the difference between the largest and
smallest signals the DAC can reproduce expressed in decibels. This is usually related to
DAC resolution and noise floor.
Other measurements, such as Phase distortion and Sampling Period Instability, can also
be very important for some applications.
7.3f DAC figures of merit
• Static performance:
o DNL (Differential Non-Linearity) shows how much two adjacent code
analog values deviate from the ideal 1LSB step [1]
o INL (Integral Non-Linearity) shows how much the DAC transfer
characteristic deviates from an ideal one. That is, the ideal characteristic
is usually a straight line; INL shows how much the actual voltage at a
given code value differs from that line, in LSBs (1LSB steps).
o Gain
o Offset
o Noise is ultimately limited by the thermal noise generated by passive
components such as resistors. For audio applications and in room
temperatures, such noise is usually a little less than 1 μV (microvolt) of
white noise. This limits performance to less than 20~21 bits even in 24-
bit DACs, and cannot be corrected unless one resorts to extremely low
temperatures to create superconductivity: clearly an impractical
proposition.
• Frequency domain performance
o SFDR (Spurious Free Dynamic Range) indicates in dB the ratio between
the powers of the converted main signal and the greatest undesired spur
o SNDR (Signal to Noise and Distortion Ratio) indicates in dB the ratio
between the powers of the converted main signal and the sum of the
noise and the generated harmonic spurs
o HDi (i-th Harmonic Distortion) indicates the power of the i-th harmonic of
the converted main signal
o THD (Total harmonic distortion) is the sum of the powers of all HDi
o if the maximum DNL error is lessthan 1 LSB,then D/A converter is
guaranteed to be monotonic.
However many monotonic converters may have a maximum DNL greater than 1 LSB.
• Time domain performance

o Glitch Energy
o Response Uncertainty
o TNL (Time Non-Linearity)
7.4 Digital Voltmeters (DVM)
Two digital voltmeters. Note the 40 microvolt difference between the two
measurements, an offset of 34 parts per million.
The first digital voltmeter was invented and produced by Andrew Kay of Non-Linear
Systems (and later founder of Kaypro) in 1954.
Digital voltmeters are usually designed around a special type of analog-to-digital

converter called an integrating converter. Voltmeter accuracy is affected by many
factors, including temperature and supply voltage variations. To ensure that a digital
voltmeter's reading is within the manufacturer's specified tolerances, they should be
periodically calibrated against a voltage standard such as the Weston cell.
Digital voltmeters necessarily have input amplifiers, and, like vacuum tube voltmeters,
generally have a constant input resistance of 10 megohms regardless of set
measurement range.
Digital Voltmeters (DVMs) are a special case of A/Ds. DVMs are voltmeters - i.e. they
measure voltage - and are general purpose instruments commonly used to measure
voltages in labs and in the field. DVMs display the measured voltage using LCDs or
LEDs to display the result in a floating point format. They are an instrument of choice
for voltage measurements in all kinds of situations.
Obviously, if voltage measurements are taken and the results are displayed
digitally with LED or LCD displays, the instrument has to contain an A/D converter.
Digital voltmeters have some characteristics that you might need to understand.
• Digital voltmeters usually have scales that are 0-0.3v, 0-3v, 0-30v, 0-300v, etc.
It is not clear why those ranges were chosen but they are commonplace. Now, consider
some of the implications of these facts.
Example
E1 Consider a voltmeter built around a 10 bit A/D converter. We will assume the
following.
• The range of the voltmeter is from 0-3v, and it does DC voltage measurements.
It does not measure negative voltages.
Then, with 10 bits we can draw these inferences.
• Ten bits will produce 210 intervals. That's 1024 intervals.

• If there are 1024 intervals over a range of 3v, each interval will be 3/1024 = .
00293v.
• It is easier to compute the displayed voltage if the interval is adjusted to .003v.
o That would make the range 0-3.072v. (That's .003 x 1024.)
o If you are measuring a voltage that varies around 3v, that would allow
you to keep the range the same, but still change the range (if the
instrument also has a 0-30v range, for instance) when the voltage got
large enough. Manufacturers like to build in a little "hysteresis" to
prevent constant range changes in situations like that and it might be
especially hard on auto-ranging meters.
• If you wanted to measure negative voltages and have the range be from -3v to
+3v, you would have intervals of .006v, and the meter would measure from
-3.072v to +3.072v.
If you wanted to measure voltages on a 0-30v scale, you would probably use a voltage
divider or some other way to reduce the voltage by a factor of (exactly) 10 (i.e., multiply
it by exactly 0.1) and then use the same converter as on the 0-3v scale.
If we could use a 12 bit A/D, then some conclusions would change.
Twelve bits will produce 212 intervals. That's 4096 intervals.
If there are 4096 intervals over a range of 3v, each interval will be 3/4096 = .000732v.
It is easier to compute the displayed voltage if the interval is adjusted to .0075v.
That would make the range 0-3.072v - just as it was in the case of the 10 bit converter,
That produces the same advantages as you had with the 10 bit converter.
If you wanted to measure negative voltages and have the range be from -3v to +3v,
you would have intervals of .0015v, and the meter would measure from -3.072v to
+3.072v.
A Note on Voltmeter Specifications
In the example you saw a few typical voltmeter possibilities. For some reason
voltmeters have had scales like 0-3v, 0-30v, etc. for a long time. You might have
expected 0-1v and 0-10v, etc. to be more common. However, that's not the way it is,
and it probably won't change any time soon. That situation has led to some interesting
ways to specify voltmeters.
If you had a voltmeter that had a 0-1v range, and it had ten bits, it would probably
be designed to have a range from 0-1.024v, and it would measure voltages in steps of .
001v. Then, the measurement results would be things like 0.314v or 0.582v, things like
that. Displayed values would all have exactly three decimal places, and the instrument
would be referred to as a 3 digit meter. If you use the same converter on a 0-10v scale
(and put the voltage through a 0.1x voltage divider!), then the results would be things
like 3.14v or 5.82v. You would get exactly the same number of significant figures, and
you would still refer to the meter as a 3 digit meter.
Let's think about this situation.
If you have a voltmeter with a 0-1v scale that can read increments of .001v the meter is
a 3 digit meter.
If you have a voltmeter with a 0-1v scale that can read increments of .0001v the meter
is a 4 digit meter.
is a 4 digit meter.
is a 5 digit meter.
Now, what if you have a meter that has a 0-3v scale that can read increments of .001v?
How many digits is that meter?
The Number Of Digits In A DVM
You need to be able to answer the question in the last section. When you buy a
meter it may tell you the number of digits and you need to know what that means,
especially when the scales are 0-3v, etc. Here is the story.
A meter that reads in increments of .001v and has a 0-1v range is a 3 digit meter.
Notice the logarithmic nature of the relationship, summarized in this table.
Digits
Range (v)
(for .001v)
0-1 3
0-10 4
0-100 5
If the high limit of the scale is 3, that's almost halfway between 1 and 10 on a
logarithmic scale. (The mid point is really at the square root of ten.) A meter that has a
range of 0-3v is said to be a 3 1/2 digit meter when it has intervals of .001v. That's
halfway between 3 and 4 digits.
There is another way to look at the question of digits. If you have a meter that has
a 0-10v scale that reads in increments of .01v that's a 3 bit meter. That meter has
1000 steps, and 1000=103. Let's repeat the table from above, but include the log10 of
the number of steps.
Digits
Range #Steps log10(#Steps)
(for .001v)
0-1v 3 1000 3
0-10v 4 10,000 4
0-30v 4.5? 30,000 4.47
0-100v 5 100,000 5
We included an extra row for a 0-30v meter. We also included the number of
steps and a suggestion for the number of digits we can claim for the meter. It looks
reasonable to call a 0-30v meter with 30,000 steps a 4.5 digit meter, and that's the way
they are sold.
That's it for digits in a voltmeter. That's the way that they are specified, and that's
what you pay for when you buy a DVM. The number of digits is determined by the
number of bits in the A/D, and we need to look at that idea just a little bit more.
7.5 Digital pattern generator

A digital pattern generator is a piece of electronic test equipment or software used to
generate digital electronics stimuli. Digital electronics stimuli are a specific kind of
electrical waveform varying between two conventional voltages that correspond to two
logic states (‘low state’ and ‘high state’, ‘0’ and ‘1’). The main purpose of a digital
pattern generator is to stimulate the inputs of a digital electronic device. For that
reason, the voltage levels generated by a digital pattern generator are often compatible
with digital electronics I/O standards – TTL, LVTTL, LVCMOS and LVDS, for instance.
Digital pattern generators are sometimes referred to as ‘pulse generator’ or ‘pulse

pattern generator’ which may be able to function as digital pattern generators as well.
Hence, the distinction between the two types of equipments may not be clear. A digital
pattern generator is a source of synchronous digital stimulus; the generated signal is
interesting for testing digital electronics at logic level - this is why they are also called
'logic source'. A pulse generator is of purpose to generate electrical pulse of different
shapes; they are mostly used for tests at an electrical or analog level.
Digital pattern generator can produce either repetitive, or single-shot signals in which
case some kind of triggering source is required (internal or external).
7.5a Types of digital pattern generators

Digital pattern generators are today available as stand-alone units, add-on hardware
modules for other equipment such as a [logic analyzer] or as PC-based equipment.
Stand-alone units are self-contained devices that include everything from the user
interface to define the patterns that should be generated to the electronic that actually
generates the output signal.
Some test equipment manufacturers propose pattern generators as add-on modules for
logic analyzers (see for example the PG3A module for Tektronix' TLA7000 series of logic
analyzers). In this case, the pattern generator is the 'generation counterpart' to the
analysis functionality offered by logic analyzers.
PC-based digital pattern generators are connected to a PC through peripheral ports

such as PCI, USB and/or Ethernet (see for example the 'Wave Generator Xpress' from
Byte Paradigm, connected through USB). They use the PC as user interface for defining
and storing the digital patterns to be sent.
7.5b Features
Digital pattern generators are primarily characterized by a number of digital channels, a
maximum rate and the supported voltage standards.
• The number of digital channels defines the maximum width of any pattern
generated - typically, 8-bits, 16-bits, 32 bits pattern generator. A 16-bits pattern
generator is able to generate arbitrary digital samples on from 1 to 16 bits.
• The maximum rate defines the minimum time interval between 2 successive
patterns. For instance, a 50 MHz (50 MSample/s) digital pattern generator is able
to output a new pattern every 20 nanoseconds.
• The supported voltage standards ultimately define the set of electronic devices
a digital pattern generator can be used with. Concretely, the voltages and the
transition characteristics of the signal at the output of the digital pattern
generator will be compliant to these voltage standards. Examples of supported
voltage standards: TTL, LVTTL, LVCMOS, LVDS.
Most digital pattern generator add features such as the ability to generate a repetitive
sequence or a digital clock signal at a specified frequency, the ability to use an external
clock input and triggering options, to start pattern generation upon the reception of an
event from an external input.
7.5c Common applications

• Digital electronics and embedded system testing and debugging
• Stimulation of digital signal processing hardware
• Digital-to-analog converter stimulation
Special purpose digital pattern generators

Video digital pattern generators are digital pattern generators dedicated to the
generation of a specific test pattern in a specific digital video format such as DVI or
HDMI.
7.5.1 Arbitrary waveform generator
The B&K Precision model 4078 Dual Channel Arbitrary Waveform Generator uses Direct
Digital Synthesis to generate waveforms up to 400,000 points
An arbitrary waveform generator (AWG) is a piece of electronic test equipment used to

generate electrical waveforms. These waveforms can be either repetitive or single-shot
(once only) in which case some kind of triggering source is required (internal or
external). The resulting waveforms can be injected into a device under test and
analyzed as they progress through the device, confirming the proper operation of the
device or pinpointing a fault in the device.
Unlike function generators, AWGs can generate any arbitrarily defined waveshape as
their output. The waveform is usually defined as a series of "waypoints" (specific
voltage targets occurring at specific times along the waveform) and the AWG can either
jump to those levels or use any of several methods to interpolate between those levels.
For example, a 50% duty cycle square wave is easily obtained by defining just two
points: At t0, set the output voltage to 100% and at t50%, set the output voltage back
to 0. Set the AWG to jump (not interpolate) between these values and the result is the
desired square wave. By comparison, a triangle wave could be produced from the same
data simply by setting the AWG to linearly interpolate between these two points.
Because AWGs synthesize the waveforms using digital signal processing techniques,
their maximum frequency is usually limited to no more than a few gigahertz[1]. The
output connector from the device is usually a BNC connector and requires a 50 or 75
ohm termination.
AWGs, like most signal generators, may also contain an attenuator, various means of
modulating the output waveform, and often contain the ability to automatically and
repetitively "sweep" the frequency of the output waveform (by means of a voltage-
controlled oscillator) between two operator-determined limits. This capability makes it
very easy to evaluate the frequency response of a given electronic circuit.
Some AWGs also operate as conventional function generators. These would include
standard waveforms such as sine, square, ramp, triangle, noise and pulse. Some units
include additional built-in waveforms such as exponential rise and fall times, sinx/x,
cardiac. Some AWG's allow users to retrieve waveforms from a number of digital and
mixed-signal oscilloscopes. Some AWG's may display a graph of the waveform on their
screen - a graph mode. Some AWG's have the ability to generate a pattern of words
from multiple bit output connector to simulate data transmission, combining the
properties of both AWG's and Digital Pattern Generator's.
AWGs may also be contained within musical synthesizers.
Digital electronics engineers sometimes refer to 'digital patterns' as 'waves' or

'waveforms'. Hence, an 'Arbitrary Digital Waveform Generator' can refer to a Digital
Pattern Generator, another type of Signal generator
7.5.2 Pulse generator
Pulse generators in a physics laboratory
A pulse generator can either be an internal circuit or a piece of electronic test

equipment used to generate pulses.
Simple pulse generators usually allow control of the pulse repetition rate (frequency),
pulse width, delay with respect to an internal or external trigger and the high- and low-
voltage levels of the pulses. More-sophisticated pulse generators may allow control over
the rise time and fall time of the pulses. Pulse generators may use digital techniques,
analog techniques, or a combination of both techniques to form the output pulses. For
example, the pulse repetition rate and duration may be digitally controlled but the pulse
amplitude and rise and fall times may be determined by analog circuitry in the output
stage of the pulse generator. With correct adjustment, pulse generators can also
produce a 50% duty cycle square wave. Pulse generators are generally single-channel
providing one frequency, delay, width and output. To produce multiple pulses, these
simple pulse generators would have to be ganged in series or in parallel.
A new family of pulse generators can produce multiple-channels of independent widths

and delays and independent outputs and polarities. Often called digital delay/pulse
generators, the newest designs even offer differing repetition rates with each channel.
These digital delay generators are useful in synchronizing, delaying, gating and
triggering multiple devices usually with respect to one event. One is also able to
multiplex the timing of several channels onto one channel in order to trigger or even
gate the same device multiple times.
A new class of pulse generator offers both multiple input trigger connections and
multiple output connections. Multiple input triggers allows experimenters to synchronize
both trigger events and data acquisition events using the same timing controller.
Pulse generators are available for generating output pulses having widths (durations)
ranging from minutes down to under 1 picosecond. In general, generators for pulses
with widths over a few microseconds employ digital counters for timing these pulses,
while widths between approximately 1 nanosecond and several microseconds are
typically generated by analog techniques such as RC (resistor-capacitor) networks or
switched delay lines. Pulse generators capable of generating pulses with widths under
approximately 100 picoseconds are often termed "microwave pulsers", and typically
generate these ultra-short pulses using Step recovery diode (SRD) or Nonlinear
Transmission Line (NLTL) methods (see, for example, [1]). Step Recovery Diode pulse
generators are inexpensive but typically require several volts of input drive level and
have a moderately high level of random jitter (usually undesirable variation in the time
at which successive pulses occur). NLTL-based pulse generators generally have lower
jitter, but are more complex to manufacture, and are not suited for integration in low-
cost monolithic ICs. A new class of microwave pulse generation architecture, the RACE
(Rapid Automatic Cascode Exchange) pulse generation circuit [2],[3], is implemented
using low-cost monolithic IC technology and can produce pulses as short as 1
picosecond, and with a repetition rates exceeding 30 billion pulses per second. These
pulsers are typically used in military communications applications, and low-power
microwave transceiver ICs. Such pulsers, if driven by a continuous frequency clock, will
as microwave comb generators, having output freqency components at integer
multiples of the pulse repetition rate, and extending to well over 100 gigahertz (see, for
example,[4]).
Pulse generators are generally voltage sources, with true current pulse generators
being available only from a few suppliers. Light pulse generators are the optical
equivalent to electrical pulse generators with rep rate, delay, width and amplitude
control. The output in this case is light typically from a LED or laser diode.
These pulses can then be injected into a device under test and used as a stimulus or
clock signal or analyzed as they progress through the device, confirming the proper
operation of the device or pinpointing a fault in the device. Pulse generators are also
used to drive devices such as switches, lasers and optical components, modulators,
intensifiers as well as resistive loads.The output of a pulse generator may also be used
as the modulation signal for a signal generator. Non-electronic applications include
those in material science, medical, physices and chemistry.
7.5.3 Signal generator

A signal generator, also known variously as a signal generator, function generator, tone
generator, arbitrary waveform generator, digital pattern generator or frequency
generator is an electronic device that generates repeating or non-repeating electronic
signals (in either the analog or digital domains). They are generally used in designing,
testing, troubleshooting, and repairing electronic or electroacoustic devices; though
they often have artistic uses as well.
There are many different types of signal generators, with different purposes and
applications (and at varying levels of expense); in general, no device is suitable for all
possible applications.
Traditionally, signal generators have been embedded hardware units, but since the age
of multimedia-PCs, flexible, programmable software tone generators have also been
available.
7.5.3a General purpose signal generators
Function generators
Leader Instruments LSG-15 signal generator
A function generator is a device which produces simple repetitive waveforms. Such

devices contain an electronic oscillator, a circuit that is capable of creating a repetitive
waveform. (Modern devices may use digital signal processing to synthesize waveforms,
followed by a digital to analog converter, or DAC, to produce an analog output). The
most common waveform is a sine wave, but sawtooth, step (pulse), square, and
triangular waveform oscillators are commonly available as are arbitrary waveform
generators (AWGs). If the oscillator operates above the audio frequency range (>20
kHz), the generator will often include some sort of modulation function such as
amplitude modulation (AM), frequency modulation (FM), or phase modulation (PM) as
well as a second oscillator that provides an audio frequency modulation waveform.
Function generators are typically used in simple electronics repair and design; where
they are used to stimulate a circuit under test. A device such as an oscilloscope is then
used to measure the circuit's output. Function generators vary in the number of outputs
they feature, frequency range, frequency accuracy and stability, and several other
parameters.
7.5.3b Arbitrary waveform generators

Arbitrary waveform generators, or AWGs, are sophisticated signal generators which
allow the user to generate arbitrary waveforms, within published limits of frequency
range, accuracy, and output level. Unlike function generators, which are limited to a
simple set of waveforms; an AWG allows the user to specify a source waveform in a
variety of different ways. AWGs are generally more expensive than function generators,
and are often more highly limited in available bandwidth; as a result, they are generally
limited to higher-end design and test applications.
7.5.3c Special purpose signal generators

A tone generator and a probe for locating a specific pair of wires amongst many, for
example in a punch block.
In addition to the above general-purpose devices, there are several classes of signal
generators designed for specific applications.
7.5.3c.1 Tone generators and audio generators

A tone generator is a type of signal generator optimized for use in audio and acoustics
applications. Tone generators typically include sine waves over the audio frequency
range (20 Hz–20 kHz). Sophisticated tone generators will also include sweep generators
(a function which varies the output frequency over a range, in order to make frequency-
domain measurements), multitone generators (which output several tones
simultaneously, and are used to check for intermodulation distortion and other non-
linear effects), and tone bursts (used to measure response to transients). Tone
generators are typically used in conjunction with sound level meters, when measuring
the acoustics of a room or a sound reproduction system, and/or with oscilloscopes or
specialized audio analyzers.
Many tone generators operate in the digital domain, producing output in various digital
audio formats such as AES-3, or SPDIF. Such generators may include special signals to
stimulate various digital effects and problems, such as clipping, jitter, bit errors; they
also often provide ways to manipulate the metadata associated with digital audio
formats.
The term synthesizer is used for a device that generates audio signals for music, or that
uses slightly more intricate methods.
7.5.3c.2 Video signal generators

A video signal generator is a device which outputs predetermined video and/or
television waveforms, and other signals used to stimulate faults in, or aid in parametric
measurements of, television and video systems. There are several different types of
video signal generators in widespread use. Regardless of the specific type, the output of
a video generator will generally contain synchronization signals appropriate for
television, including horizontal and vertical sync pulses (in analog) or sync words (in
digital). Generators of composite video signals (such as NTSC and PAL) will also include
a colorburst signal as part of the output. Video signal generators are available for a wide
variety of applications, and for a wide variety of digital formats; many of these also
include audio generation capability (as the audio track is an important part of any video
or television program or motion picture).
7.6 Frequency synthesizer

A frequency synthesizer is an electronic system for generating any of a range of
frequencies from a single fixed timebase or oscillator. They are found in many modern
devices, including radio receivers, mobile telephones, radiotelephones, walkie-talkies,
CB radios, satellite receivers, GPS systems, etc. A frequency synthesizer can combine
frequency multiplication, frequency division, and frequency mixing (the frequency
mixing process generates sum and difference frequencies) operations to produce the
desired output signal.
7.6a Types
Three types of synthesizer can be distinguished. The first and second type are routinely
found as stand-alone architecture: Direct Analog Synthesis (also called a mix-filter-
divide architecture [1] as found in the 1960s HP 5100A) and by comparison the more
modern Direct Digital Synthesis (DDS) (Table-Look-Up). The third type are routinely
used as communication system IC building-blocks: indirect digital (PLL) synthesizers
including integer-N and fractional-N. [2]
7.6b Digiphase Synthesizer

It is in some ways similar to a DDS, but it has architectural differences. One of its big
advantages is to allow a much finer resolution than other types of synthesizers with a
given reference frequency. [3]
7.6c History
Although frequency as the inverse of a wave period is a relatively recent idea[4], the
origins of frequency synthesis can be found in the much older concept of angular
velocity.[4] The wheel trains of timekeeping devices have gear ratio relationships that
were well-studied at least as far back as the time of Christian Huygens, who died in
1695.[4]
Prior to widespread use of synthesizers, radio and television receivers relied on manual
tuning of a local oscillator. Some might remember the classic turret tuner commonly
used in television receivers prior to the 1980s. Variations in temperature and aging of
components caused frequency drift. Automatic frequency control (AFC) solves some of
the drift problem, but manual retuning was often necessary. Since transmitter
frequencies are well known and very stable, an accurate means of generating fixed,
stable frequencies would solve the problem.
A simple and effective solution employs the use of many stable resonators or
oscillators, one for each tuning frequency. Quartz crystals offer good stability and are
often used for this purpose. This "brute force" technique is practical when only a
handful of frequencies are required, but quickly becomes costly and impractical in many
applications. For example, the FM radio band in many countries supports 100 individual
frequencies from about 88 MHz to 108 MHz. Cable television can support even more
frequencies or channels over a much wider band. A large number of crystals increases
cost and requires greater space.
Many coherent and incoherent techniques have been devised over the years. Some
approaches include phase locked loops, double mix, triple mix, harmonic, double mix
divide, and direct digital synthesis (DDS). The choice of approach depends on several
factors, such as cost, complexity, frequency step size, switching rate, phase noise, and
spurious output.
Coherent techniques generate frequencies derived from a single, stable master

oscillator. In most applications, crystal oscillator are common, but other resonators and
frequency sources can be used. Incoherent techniques derive frequencies from a set of
several stable oscillators. [5] The vast majority of synthesizers in commercial
applications use coherent techniques due to simplicity and low cost.
Synthesizers used in commercial radio receivers are largely based on phase-locked
loops or PLLs. Many types of frequency synthesiser are available as integrated circuits,
reducing cost and size. High end receivers and electronic test equipment use more
sophisticated techniques, often in combination.
7.6d System analysis and design

A well-thought-out design procedure is considered to be the first significant step to a
successful synthesizer project. [6] In the System design of a frequency synthesizer,
Mannassewitsch states that there are as many "best" design procedures as there are
experienced synthesizer designers. [7] System analysis of a frequency synthesizer
involves output frequency range (or frequency bandwidth or tuning range), frequency
increments (or resolution or frequency tuning), frequency stability (or phase stability,
compare spurious outputs), phase noise performance (e.g., spectral purity), switching
time (compare settling time and rise time), and size, power consumption, and cost. [8]
[9] James A. Crawford says that these are mutually contradictive requirements[9]
Trial-and-error superseded by calculation and control theory

The trial and error method was once the work-horse for designers of frequency
synthesizers [4].
This began to change with the works of Floyd M. Gardner (his 1966 Phaselock
techniques) and Venceslav F. Kroupa (his 1973 Frequency Synthesis)[4].
Mannassewitsch calls this the Brute-force approach.[10] Techniques and formulae have
been provided by Dean Banerjee [11].
Gearbox approach
Surprisingly sophisticated mathematical techniques analogous to mechanical gear ratio
relationships can be employed in frequency synthesis when the frequency synthesis
factor is composed of multiplicative integers in the numerator and denominator. [4] This
method allows for effective planning of distribution and suppression of spectral spurs.
Modulo-N approach
Variable frequency synthesizers including DDS are routinely designed using this
method.
7.6e Principle of PLL synthesizers

A phase locked loop does for frequency what the Automatic Gain Control does for
voltage. It compares the frequencies of two signals and produces an error signal which
is proportional to the difference between the input frequencies. The error signal is then
low pass filtered and used to drive a voltage-controlled oscillator (VCO) which creates
an output frequency. The output frequency is fed through a frequency divider back to
the input of the system, producing a negative feedback loop. If the output frequency
drifts, the error signal will increase, driving the frequency in the opposite direction so as
to reduce the error. Thus the output is locked to the frequency at the other input. This
input is called the reference and is derived from a crystal oscillator, which is very stable
in frequency. The block diagram below shows the basic elements and arrangement of a
PLL based frequency synthesizer.
The key to the ability of a frequency synthesizer to generate multiple frequencies is the
divider placed between the output and the feedback input. This is usually in the form of
a digital counter, with the output signal acting as a clock signal. The counter is preset to
some initial count value, and counts down at each cycle of the clock signal. When it
reaches zero, the counter output changes state and the count value is reloaded. This
circuit is straightforward to implement using flip-flops, and because it is digital in
nature, is very easy to interface to other digital components or a microprocessor. This
allows the frequency output by the synthesizer to be easily controlled by a digital
system.
Example
Suppose the reference signal is 100 kHz, and the divider can be preset to any value
between 1 and 100. The error signal produced by the comparator will only be zero when
the output of the divider is also 100 kHz. For this to be the case, the VCO must run at a
frequency which is 100 kHz x the divider count value. Thus it will produce an output of
100 kHz for a count of 1, 200 kHz for a count of 2, 1 MHz for a count of 10 and so on.
Note that only whole multiples of the reference frequency can be obtained with the
simplest integer N dividers. Fractional N dividers are readily available [11].
7.6f Practical considerations

In practice this type of frequency synthesiser cannot operate over a very wide range of
frequencies, because the comparator will have a limited bandwidth and may suffer from
aliasing problems. This would lead to false locking situations, or an inability to lock at
all. In addition, it is hard to make a high frequency VCO that operates over a very wide
range. This is due to several factors, but the primary restriction is the limited
capacitance range of varactor diodes. However, in most systems where a synthesiser is
used, we are not after a huge range, but rather a finite number over some defined
range, such as a number of radio channels in a specific band.
Many radio applications require frequencies that are higher than can be directly input to
the digital counter. To overcome this, the entire counter could be constructed using
high-speed logic such as ECL, or more commonly, using a fast initial division stage
called a prescaler which reduces the frequency to a manageable level. Since the
prescaler is part of the overall division ratio, a fixed prescaler can cause problems
designing a system with narrow channel spacings - typically encountered in radio
applications. This can be overcome using a dual-modulus prescaler.[11]
Further practical aspects concern the amount of time the system can switch from
channel to channel, time to lock when first switched on, and how much noise there is in
the output. All of these are a function of the loop filter of the system, which is a low-pass
filter placed between the output of the frequency comparator and the input of the VCO.
Usually the output of a frequency comparator is in the form of short error pulses, but
the input of the VCO must be a smooth noise-free DC voltage. (Any noise on this signal
naturally causes frequency modulation of the VCO.). Heavy filtering will make the VCO
slow to respond to changes, causing drift and slow response time, but light filtering will
produce noise and other problems with harmonics. Thus the design of the filter is
critical to the performance of the system and in fact the main area that a designer will
concentrate on when building a synthesiser system
7.7 Design and Implementation of a 4-bit ALU

a. Problem Statement:
An Arithmetic and Logic Unit (ALU) is a combinational circuit that performs logic and
arithmetic micro-operations on a pair of n-bit operands (ex. A[3:0] and B[3:0]). The
operations performed by an ALU are controlled by a set of function-select inputs. In this
lab you will design a 4-bit ALU with 3 function-select inputs: Mode M, Select S1 and S0
inputs. The mode input M selects between a Logic (M=0) and Arithmetic (M=1)
operation. The functions performed by the ALU are specified in Table I.
Table 1: Functions of ALU

M = 0 Logic
S1 S0 C0 FUNCTION OPERATION (bit wise)
0 0 X AiBi AND
0 1 X A i + Bi OR
1 0 X Ai⊕ Bi XOR
1 1 X (Ai⊕ Bi)’ XNOR
M = 1 Arithmetic
S1 S0 C0 FUNCTION OPERATION
0 0 0 A Transfer A
0 0 1 A+1 Increment A by 1
0 1 0 A+B Add A and B
0 1 1 A+B+1 Increment the sum of A and B by 1
1 0 0 A + B' A plus one's complement of B
1 0 1 A-B Subtract B from A (i.e. B' + A + 1)
1 1 0 A' + B B plus one's complement of A
1 1 1 B-A B minus A (or A' + B + 1)
A block diagram is given in Figure 7.7.
Figure 7.7: Block diagram of the 4-bit ALU.
When doing arithmetic, you need to decide how to represent negative numbers. As is
commonly done in digital systems, negative numbers are represented in two’s
complement. This has a number of advantages over the sign and magnitude
representation such as easy addition or subtraction of mixed positive and negative
numbers. Also, the number zero has a unique representation in two’s complement. The
two’s complement of a n-bit number N is defined as,
2n - N = (2n - 1 - N) + 1
The last representation gives us an easy way to find two’s complement: take the bit wise
complement of the number and add 1 to it. As an example, to represent the number -5,
we take two’s complement of 5 (=0101) as follows,
5 0 1 0 1 --> 1 0 1 0 (bit wise complement)
+ 1
1 0 1 1 (two’s complement)
Numbers represented in two’s complement lie within the range -(2n-1) to +(2n-1 - 1). For a
4-bit number this means that the number is in the range -8 to +7. There is a potential
problem we still need to be aware of when working with two's complement, i.e. over- and
underflow as is illustrated in the example below,
0 1 0 0 (=carry Ci)
+5 0 1 0 1
+4 + 0 1 0 0
+9 0 1 0 0 1 = -7!
also,
1 0 0 0 (=carry Ci)
-7 1 0 0 1
-2 + 1 1 1 0
-9 1 0 1 1 1 = +7!
Both calculations give the wrong results (-7 instead of +9 or +7 instead of -9) which is
caused by the fact that the result +9 or -9 is out of the allowable range for a 4-bit two’s
complement number. Whenever the result is larger than +7 or smaller than -8 there is an
overflow or underflow and the result of the addition or subtraction is wrong. Overflow
and underflow can be easily detected when the carry out of the most significant stage (i.e.
C4 ) is different from the carry out of the previous stage (i.e. C3).
You can assume that the inputs A and B are in two’s complement when they are
presented to the input of the ALU.
b. Design strategies
When designing the ALU we will follow the principle "Divide and Conquer" in order to
use a modular design that consists of smaller, more manageable blocks, some of which
can be re-used. Instead of designing the 4-bit ALU as one circuit we will first design a
one-bit ALU, also called a bit-slice. These bit-slices can then be put together to make a 4-
bit ALU.
There are different ways to design a bit-slice of the ALU. One method consists of writing
the truth table for the one-bit ALU. This table has 6 inputs (M, S1, S0, C0, Ai and Bi) and
two outputs Fi and Ci+1. This can be done but may be tedious when it has to be done by
hand.
An alternative way is to split the ALU into two modules, one Logic and one Arithmetic
module. Designing each module separately will be easier than designing a bit-slice as one
unit. A possible block diagram of the ALU is shown in Figure 7.8. It consists of three
modules: 2:1 MUX, a Logic unit and an Arithmetic unit.
Figure 7.8: Block diagram of a bit-slice ALU
c.Displaying the results.
In order the easily see the output of the ALU you will display the results on the seven-
segment displays and the LEDs (LD).
1. 1.The result of the logic operation can be displayed on the LEDs (LD). Use also
one of these LEDs to display the overflow flag V.
2. 2.Since you are working with a 4-bit representation for 2's complement numbers,
the maximum positive number is +7 and the most negative number is –8. Thus a
single seven-segment display can be used to show the magnitude of the number.
Use another seven-segment display for the “-“ sign (e.g. use segment “g”).
3. 3.There is one complication when using more than one of the seven-segment
displays on the Digilab board, as can be seens from the connections of the LED
segments of the displays. You will notice that the four seven-segment displays
share the same cathodes A, B, ..., G). This implies that one cannot directly
connect the signals for the segments of the magnitude and sign to these terminals,
since that would short the outputs of the gates which would damage the FPGA!.
How could you solve this problem? Sketch a possible solution in your lab
notebook. (Hint: You can alternate the signals applied to the cathodes between
those of the Magnitude and Sign displays. If you do this faster than 30 times per
second the eye will not notice the flickering. You will also need to alternate the
anode signals). What type of circuit will be needed to accomplish this? You can
make use of an on-chip clock, called OSC4 that provides clock signals of 8MHz,
500KHz, 590Hz and 15Hz.
4. 4.Figure 3 shows a schematic of the overall system, consisting of the ALU,
Decoder and Switching circuit, and Displays on the Digilab board.
Figure 7.9: Overall system, including the 4-bit ALU and display units.
d. Tasks:
Do the following tasks prior to coming to the lab. Write the answers to all questions in
your lab notebook prior to coming to the lab. There is no on-line submission for the pre-
lab. Ask the TA to sign pre-lab section in your lab notebook at the start of the lab
session. You will also need to include answer to the pre-lab questions in your lab report.
1. Design the MUX. You can choose to design the MUX with gates or by writing
HDL (VHDL) code. Choose one of the two methods and write the design down in
your lab notebook.
2. Design of the Logic unit. Here you also have several choices to design this unit:
a. Write truth table, derive the K-map and give the minimum gate implementation
b. Use a 4:1 MUX and gates
c. Write an HDL file
As part of the pre-lab, you can choose any of the three methods. Briefly justify why you
chose a particular design method. Explain the design procedure and give the logic
diagram or the HDL file. In case you use a MUX, you need also to give the schematic or
the HDL file for the MUX.
3. Design the arithmetic unit. Again, here you have different choices to design and
implement the arithmetic unit. A particularly attractive method is one that makes
use of previously designed modules, such as your Full Adder. The arithmetic unit
performs basically additions on a set of inputs. By choosing the proper inputs, one
can perform a range of operations. This approach is shown in Figure 7.10 The
only blocks that need to be designed are the A Logic and B Logic circuits. You
can make use of your previously designed full adder (MYFA).
Figure 7.10: Schematic block diagram of the arithmetic unit.
a. Give the truth tables for the Xi and Yi functions with as

inputs S1, S0 and Ai, and S1, S0 and Bi, respectively. Fill
out the following tables. Notice that in definition table I of
the ALU, the variable C0 acts as the Carry input.
Depending on the value of C0, one performs the function on
the odd or even entries of the definition table I. As an
example the first entry is "transfer A" (for C0=0) while the
second one is "A+1" (for C0=1); Similarly for A + B and A
+ B + 1, etc.
Xi Yi
S1 S0 Ai (A S1 S0 Bi (B
Logic) Logic)
0 0 0 . 0 0 0 .
0 0 1 . 0 0 1 .
0 1 0 . 0 1 0 .
0 1 1 . 0 1 1 .
1 0 0 . 1 0 0 .
1 0 1 . 1 0 1 .
1 1 0 . 1 1 0 .
1 1 1 . 1 1 1 .
Table II: Truth tables for the A and B logic circuits.
b. Give the K-map for Xi and Yi functions. Find the minimum realization for
Xi and Yi.
c. Draw the logic diagram for Xi and Yi.
d. Design the circuit that detects over- or underflow.
3. 4.Design the decoder for the seven-segment displays. Remember that the
segments of the display are active-low. The decoders should be designed in such a
way that when the Logic Mode (M=0) is selected, only the LEDs are active and
when the Arithmetic Mode (M=1) is selected only the seven-segment displays are
active.
4. 5.Design the switching circuit that is needed to use the two seven-segment
displays (see section c3 above).

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7.

7.1a Down-Conversion Techniques

A key ingredient in automating the heterodyne down-conversion process is the

Time Time Base

Figure 7.1. Block diagram of the heterodyne down-conversion technique.

The input signal at frequency fx is shown being phase-locked to a voltage controlled

Fif1 From Time Base

VCO 1 Phase Reference

Main Gate Display

Time Time Base

Figure 7.2. Block diagram of the transfer oscillator down-conversion technique.

Harmonic Heterodyne Converter

Main Gate Counting

Time Base Display

Figure 7.3. Block diagram of the harmonic heterodyne down-conversion technique.

A frequency measurement is accomplished by the processor’s multiplying the known

The harmonic heterodyne converter has the potential to be constructed at a lower

7.1b Comparison of Performance of the Down-Conversion Technique

The accuracy of microwave counter measurements is limited by two factors:

Sensitivity and Dynamic Range

Maximum Measured Input

-20 dBm Sensitivity:

Harmonic Heterodyne Converter

5 GHz 10 GHz 15 GHz 20 GHz

The dynamic range of a microwave counter is a measure of the separation of the

An important consideration in choosing a microwave counter is the signal-to-noise

A second form of modulation encountered during microwave measurements is amplitude

Frequently a microwave counter will be called upon to measure a signal in the

2 dB (typical) 5 dB (typical) 10 dB (typical)

200 MHz 1 GHz 18 GHz

The heterodyne converter is capable of amplitude discrimination of widely separated

A summary of the performance trade-offs based on the criteria discussed above is

Frequency Range 20 GHz 23 GHz 40 GHz

Measurement Speed 150 ms acquisition 150 ms acquisition 350 ms acquisition

4-channel stereo multiplexed analog-to-digital converter WM8775SEDS made by

An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device which

Q is resolution in volts per step (volts per output code),

In practice, the useful resolution of a converter is limited by the best signal-to-noise

7.2b Response type

phenomenon can be estimated as .

following formula: , where q is a number of ADC bits.

8 1243 µs 28.2 ns 6.48 ns 1.24 ns 124 ps 12.4 ps 1.24 ps

10 311 µs 7.05 ns 1.62 ns 311 ps 31.1 ps 3.11 ps 0.31 ps

12 77.7 µs 1.76 ns 405 ps 77.7 ps 7.77 ps 0.78 ps 0.08 ps

14 19.4 µs 441 ps 101 ps 19.4 ps 1.94 ps 0.19 ps 0.02 ps

16 4.86 µs 110 ps 25.3 ps 4.86 ps 0.49 ps 0.05 ps –

18 1.21 µs 27.5 ps 6.32 ps 1.21 ps 0.12 ps – –

20 304 ns 6.88 ps 1.58 ps 0.16 ps – – –

24 19.0 ns 0.43 ps 0.10 ps – – – –

7.2e Sampling rate

7.2i Relative speed and precision

The sliding scale principle

7.2j ADC structures

7.3 Digital-to-analog converter

In electronics, a digital-to-analog converter (DAC or D-to-A) is a device for converting a

An analog-to-digital converter (ADC) performs the reverse operation.

7.3a Basic ideal operation

Ideally sampled signal. Signal of a typical interpolating DAC output

7.3b Practical operation

Piecewise constant signal typical of a zero-order (non-interpolating) DAC output.

Top-loading CD player and external digital-to-analog converter.

7.3d DAC types