An Area- and Power-efficient Monolithic Buck Converter with

Fast Transient Response

Ying Wu, Sam Y. S. Tsui and Philip K. T. Mok
Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong
Abstract- A voltage-mode Buck converter with a novel to provide phase boost and offsets the complex pole (at fLCo)
Pseudo-Type III compensation is presented. It maintains the fast phase lag due to L-C output filter. In this way, the crossover
load transient response, as confirmed by the measured loop gain, frequency can be extended beyond fLCo to ~20% of switching
and 7μs settling time for 500mA load current step. It also trans- frequency (1MHz in this paper). For a typical power stage
forms the Type III compensator into a summation of an area- and
with fLCo = 34kHz, the size of passive components can be es-
power-efficient error amplifier plus a low-power band-pass filter.
Consequently, the area and power consumption of proposed com-
timated as follows: R3 and C1 are negligible as they are used to
pensator is reduced by 80% and 85%. generate high frequency poles. Assume fz1 = fz2 = fLCo, then
R1, R2, C3, C2 can be assigned to be 100kΩ, 100kΩ, 48pF, and
I. INTRODUCTION 48pF, respectively. These values can be implemented on-chip;
yet the area occupied would be quite large.
Voltage-mode control switching regulators are widely used
nowadays. In particular, in applications where fast dynamic Vo
response [1] and small equivalent series resistance (ESR) of Vg
Vx
Rl L Rfb1
Rc
output capacitor (e.g. ceramic capacitor) is preferred, Type III
Rld Vfb
compensation is usually employed to extend the loop gain
crossover frequency while maintaining the loop stability. Co Rfb2
Nonetheless, Type III compensator is often implemented off-
Pseudo-
chip [2]. While this may give more design flexibility to some Type III
customers, it can be an obstacle to further squeezing the size Dead- PWM compensator A(s)
of the power supply. On the other hand, integrating the passive time + comparator Vref
Vc
driver
components on-chip can be costly due to their large size re- Vrst
quired for generating low-frequency zeros. Moreover, the re- B(s)
Vpwm_rmp
quired high gain-bandwidth of the error amplifier driving the logic
compensator is undesirable since it consumes considerable Vart_rmp |A(s)|

amount of power in the control circuitry. Vm

f
This paper proposes a novel compensation method which Clk Ramp |B(s)|
mimics the frequency response of a Type III compensator, + Clk
while tremendously reduces the chip area and power con- f

sumption for implementing the compensator on-chip. This is Fig. 1. Proposed pseudo-type III compensated Buck converter
realized through innovations in both architectural and circuit C1
levels. In architectural level, the frequency response of Type R3 C3
III compensator is divided into low frequency and high fre- R2 C2
quency portions, with each portions handled by the low- R1
frequency path A(s) and high-frequency path B(s), respective-
ly, as shown in Fig. 1. The final Pseudo-Type III response is
then obtained by summing two signal paths at the inputs of the Vref
PWM comparators. Such a structure leads to new locations of f z1 =
1
fz2 =
1
2π R2C2 2π ( R1 + R3 ) C3
zeros, which may be used to reduce the on-chip passive com-
ponent size, and the gain-bandwidth requirement (and hence
power requirement) of the error amplifier. In circuit level, a
low-power band-pass filter and an area-efficient error amplifi-
er are designed and integrated on-chip, which complete a solu-
tion of a monolithic Type III compensator with reduced area
and power consumption.

II. LIMITATIONS OF TYPE III COMPENSATION1

Fig. 2 shows the schematic and frequency response of a
conventional Type III compensator, which generates two zeros
Fig. 2. Conventional Type III compensator
This work was partially supported by the Research Grant Council of Hong Kong SAR
Government, China under Project 617707.
 The requirement of gain-bandwidth of error amplifier is proposed compensator is only a fraction of fLCo. Hence, it is
another concern. As mentioned in [3], it is common that error around 2 orders of magnitude smaller than what is required in
amplifier has high gain-bandwidth around 10MHz to avoid conventional Type III compensator. A huge amount of power
pushing the compensator’s poles to lower frequency. To esti- is then saved for the same capacitive load.
mate the power required to achieve such a gain-bandwidth, a Secondly, as the second zero of C(s) is at lower frequency
behavioral model of a transconductance amplifier (i.e. a vol- than ωzbpf, the size of passive components used to generate
tage-controlled current source with output resistance Roea) is ωzbpf can be reduced. Denote that the desired C(s) second zero
used in Fig. 2 for AC simulation. It is found that the minimum is Kz times as high as the first zero; that is:
required Gm is around 2mA/V and the corresponding bias cur- ω z 2 _ c ( s ) = K zω z1_ c ( s ) . (6)
rent of input differential pair is about 400μA. It is desirable to Substituting (6) into (4), and after some algebra, we have:
reduce the current to tens of μA for better power efficiency.
ωzbpf = ω z 2 _ c ( s ) (1 + 1/ K z ) (7)
III. PROPOSED PSEUDO-TYPE III COMPENSATION and Geaω p 0 = ω z1_ c ( s ) ⎡⎣1 − 1/ ( K z + 1)⎤⎦ (8)
From Fig. 1, a small-signal model of the proposed pseudo- Hence, the time constant (i.e. ~size of passive components) to
type III compensation can be constructed as shown in Fig. 3. generate the second zero is reduced by 1/(Kz+1)x100%.
Based on Fig. 3, loop gain Tvo(s) can be derived as: Moreover, since (8) shows that the first zero is at higher fre-
b quency than Geaωp0, it reduces power consumption as Geaωp0 is
Tvo ( s ) = Gvd ( s ) [ A( s ) + B( s ) ] , (1) generated by Gm/C, but not 1/(RC) as said in last paragraph.
Vm
where b is the scaling factor given by Rfb2/(Rfb1+Rfb2), Vm is
the ramp amplitude, and Gvd(s) is the control-to-output transfer Gvd(s) Vo v o 1 + sRc Co
Gvd ( s ) = ≈ Vg
function determined by the power stage. Meanwhile, owing to d d s s2
1+ +
their low-pass and band-pass nature, A(s) and B(s) can be Q psω ps ω ps 2
1 b
represented as:
Vm 1+
Rl
⎛ s ⎞ ω ps =
1 Rld
Gbpf ⎜1 + ⎟ R
Gea ⎜ ω zbpf ⎟ LCo 1+ c
A( s ) = B( s) = ⎝ ⎠ , (2(a)-(b)) Rld
Vc
s ⎛ s ⎞⎛ s ⎞ -A(s) ⎛ Rc ⎞⎛ Rl ⎞
1+ ⎜1 + ⎟⎜1 + ⎟ ⎜1 + ⎟⎜1 + ⎟
ω po ⎜ ω p1 ⎟⎜ ω p 2 ⎟ Q ps = LCo
⎝ Rld ⎠⎝ Rld ⎠
⎝ ⎠⎝ ⎠ L ⎡ ⎛ R ⎞⎤
+ Co ⎢ Rc + Rl ⎜1 + c ⎟ ⎥
where the dc gain of bandpass filter, Gbpf, is set to unity in this Rld ⎣ ⎝ Rld ⎠ ⎦
B(s)
paper. From (2), it can be seen that the new “compensator”,
C(s) = [A(s) + B(s)], has 3 poles and 2 zeros as the Type III Fig. 3. Small-signal block diagram of the proposed converter
compensator. The high frequency poles of C(s) are the same
as those of B(s); yet the zeros of C(s) are not trivial to be lo-
cated at the first sight. Assuming Gea>>1, Geaωp0<ωzbpf<ωp1
<<ωp2, the numerator of C(s) can be written as:
⎧⎪ ⎡ 1 ⎤ 2⎡ 1 ⎤ ⎫⎪
Num [C ( s ) ] ≈ Gea ⎨1 + s ⎢ ⎥+s ⎢ ⎥⎬ (3)
⎪⎩ ⎣⎢ Geaω p 0 ⎦⎥ ⎣⎢ Gea ω p 0ω zbpf ⎦⎥ ⎪⎭
The zeros of C(s) can then be represented as:

ω zbpf ⎛ 4G ω ⎞
(4)
ωz _ c( s) ≈ ⎜1 ± 1 − ea p 0 ⎟
2 ⎜ ω zbpf ⎟
⎝ ⎠
For 4Geaωp0 < ωzbpf, it can be proved that two zeros of C(s)
are real, and bounded by the following limits:
Geaω p 0 < ω z1_ c ( s ) < ω zbpf / 2 < ω z 2 _ c( s ) < ω zbpf (5)
Fig. 4. Detailed frequency response of proposed compensator
Equation (5) and the locations of zeros can be illustrated
graphically by Fig. 4. From the above analysis, two findings
IV. CIRCUIT IMPLEMENTATION
should be noted. Firstly, the first zero is generated through
addition of two signal paths, rather than due to the time con- There are many different suggestions as to where to place
stant of an explicit pair of resistor and capacitor. If we use a two zeros in Type III compensator [4]-[5] (that is: designing
transconductance amplifier with capacitive load only, its gain- the Kz in last section and the location of zeros relative to fLCo).
bandwidth (~Gm/C) roughly determines the first zero of C(s). Noting that capacitor usually takes up more area than resistor
Hence, a large on-chip resistor for generating the first zero is in an on-chip environment, we have placed the two zeros
waived. Also, as the first zero is usually placed below fLCo and widely apart to minimize the area for passive components for
from (5), the required gain-bandwidth of error amplifier in the reasons to be explained shortly in the following paragraphs.
 Fig. 5 shows the current-mirror error amplifier with capa-
citive load (Cc), which is implemented in the form of MOS
capacitor in strong inversion by shorting the source, drain and
bulk terminals of NMOS transistor. This approach is feasible
in the proposed compensation as error amplifier output is very
stable and its dc value is determined by the sum of Vart_rmp and
scaled Vo as implied in Fig. 1. Hence, a minimum voltage of
ramp signal can be set to ensure that a gate voltage higher than
threshold voltage is applied to the MOS capacitor. On the con-
trary, in conventional Type III compensator, linear poly-poly
capacitor must be used to implement capacitors due to the
wide dynamic range and fast-moving nature of error amplifier
output. The capacitance per unit area of MOS capacitor is 5
times as large as that of poly-poly capacitor. Cc and Gm of the
error amplifier is 100pF (effective area = 20pF) and 2.9μA/V
respectively. The bias current required for input differential
pair is only 400nA. Consequently, the gain-bandwidth of pro-
posed error amplifier is around 4.6kHz.
Fig. 6 shows the proposed bandpass filter and the adder (as
shown in Fig. 1) in the form of a voltage-to-current (v-to-i)
converter. The amplifier, M1, Rbpf1, Rbpf2, and Cbpf form the
bandpass filter, while the amplifier, M1, and Rv2i constitute the
v-to-i converter. In this design, the amplifier and M1 are
reused and the filter and adder are combined to save power.
Only around 26μA current is used in total. The filter accepts
input from Vfb, and its output is at Vbpo; while the PMOS cur-
rent mirror copies the filter output signal current to add with
the artificial ramp current. M1 behaves like a unity gain source
follower around the filter loop, and gives a low impedance at
Vbpo. With this in mind, and assuming GbpARbpf2/(Rbpf1+Rbpf2)
>>1, the transfer function of filter can be written as:
B( s) ≈
( )
1 + s Rbpf 1 + Rbpf 2 Cbpf
⎛ 1 Rbpf 1 + Rbpf 2 ⎞
(1 + sRbpf 2Cbpf ) ⎜⎜1 + s G
bpAωobpA Rbpf 2
⎝ ⎠
and the dc gain and 3-dB bandwidth of amplifier (GbpA, and
ωobpA) are given by:
GbpA = Gmamp Roamp and ωbpA = Roamp Ccbpf (10(a)-(b))
Hence, for the system, ωzbpf, ωp1, and ωp2 are given by:
1 , 1 ,
ω zbpf = ω p1 ≈
( )
Rbpf 1 + Rbpf 2 Cbpf Rbpf 2 Cbpf
Rbpf 2
ω p 2 ≈ GbpAωobpA . (11)
Rbpf 1 + Rbpf 2
Equation (11) shows that in the proposed bandpass filter, pas-
sive components set the zero and first pole frequency, while
the second pole is determined by the gain-bandwidth of am-
plifier and the ratio of resistances. Since the amplifier only
drives the gate of a small source follower M1, even with a
small bias current of 4μA, fp2 is at high frequency (>1MHz).
Yet, it does not affect the noise sensitivity much as the gain in
pass-band of proposed bandpass filter is already set to a mod-
est value of 15dB by the choice of fzbpf and fp1. As a summary,
Rbpf1, Rbpf2, and Cbpf are 100kΩ, 20kΩ, and 10pF, respectively
and the resultant fzbpf is at 132kHz. fp1 is placed at output ca-
pacitor ESR frequency (~800kHz) to ensure good gain margin
beyond loop gain crossover frequency.
From the above discussion, it can be seen that pseudo-type
III compensation reduces the power consumption of the error
amplifier, and the area for passive components implementing
the bandpass filter. The latter benefit can be up to 50% when
Kz = 1 according to eq. (7). Furthermore, with the employment
of MOS capacitor in error amplifier, the area for implementing
the first zero can be reduced by 80%. Hence, when total area
reduction is the main goal, the two zeros are placed widely
apart. As a comparison, in the conventional Type III compen-
sator, R1, R2, C3, C2 can be assigned to be 300kΩ, 201kΩ,
4.1pF, and 162pF, respectively to achieve the same zero
placement and crossover frequency. The area for passive com-
ponents in pseudo-type III compensator is thus reduced by
about 80% compared to its equivalent Type III counterpart.
Vfb Vref Vc
Cc
Fig. 5. Schematic of error amplifier
Vfb
(9)
M1
Roamp
Ccbpf
Vbpo
Gmamp
⎟ Vinn
⎟ Vfb
Rbpf1 Vbpo (dB)
Rbpf2
Rv2i fzbpf fp1 fp2 freq
Cbpf
and
Fig. 6. Schematic of proposed band-pass filter
V. MEASUREMENT RESULTS
The proposed buck converter was implemented in AMS
0.35-μm CMOS process. Fig. 7 is the die photo of the proto-
type, which has a dimension of 1.2x1.1mm2 including pads.
The prototype works with input voltage ranging from 2.5V to
3.5V, with inductor and output capacitor chosen to be 4.7μH
and 4.7μF (with 20mΩ ESR), respectively. Unless otherwise
stated, all of the following results are obtained using input
voltage of 3V, and resistive load. Fig. 8 shows the steady-state
output of the prototype at different duty-ratios (Ds). It is ob-
served that the triangular ripple contributed by ESR is hardly
seen. Out of the smaller than 10mV ripple, the majority is ac-
tually contributed by the equivalent-series-inductance (ESL)
on PCB. Fig. 9 shows the measured efficiency at different
loading current and output voltage. High efficiency of no less
than 85.5% is measured for loading current as low as 50mA.
In fact, with the proposed low-power compensator, the limit-
ing factor in such operating region becomes the switching loss
rather than the power consumption in frequency compensator.
Fig. 10 shows the load transient response of the prototype.
The change in loading current is around 500mA. It can be seen
that the output voltage settles very fast (within 7μs) as conven-
tional Type III compensated regulator. Also shown in the fig-
ures is the summed waveform of bandpass filter and ramp
signal, Vpwm_rmp. It is observed that when Vo changes, Vpwm_rmp
performs the bandpass function to modestly amplify the
change in Vo to lower or raises the transient level of Vpwm_rmp.
Fig. 11 shows the bode plot of measured, analytical and simu-
lated loop gain based on the simulator presented in [6]. It can
be seen that the curves match each other very well, especially
Fig. 11. Measured, analytical and simulated loop gains
at low frequencies. There is some phase difference between
measured and simulated curve at high frequency beyond cros-
sover frequency. Hence, the small-signal model in this paper is VI. CONCLUSION
valid for design purpose. Conventional Type III compensator generates two zeros by
explicit R-C pairs, which gives rise to high passive component
counts, and large chip area if the passive components are inte-
grated on-chip. In addition, high gain (for good line/load regu-
Vo at D = 0.8
lation) and high gain-bandwidth error amplifier is required to
Vo at D = 0.5 maintain proper pole locations. The error amplifier thus tends
Vo at D = 0.27 to be power hungry.
The proposed Pseudo-Type III compensator decouples the
requirement of high gain and high gain-bandwidth into two
Vart_rmp
distinct signal paths and makes the design of low-power error
amplifier possible. The proposed bandpass filter also saves
Fig. 7. Die photo of prototype Fig. 8. Measured steady-state output power by combining the voltage adder with the buffer stage of
an amplifier. The new locations of zeros and the possibility of
98
97
Vout=1.2V using MOS capacitor significantly reduce area for passive
Vout=1.8V
96 Vout=2.4V components. The proposed compensator is analyzed in small-
95
94
signal domain, and is verified by simulation and measurement
93 result to be equivalent to its Type III counterpart. A prototype
Efficiency %

92
91
Vin=3V chip with 2 widely spaced zeros is fabricated and measured;
90 yet the proposed compensator can implement any zero loca-
89
tion with the benefit of reduced area and power.
88
87
86 REFERENCES
85
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