San José State University

Computer Engineering Department

CMPE 200, Computer Architecture, Spring 2011

Instructor: Haluk Katircioglu

Office Location: E283K

Telephone: (408)924-3820 no messaging

Email: Haluk.Katircioglu@sjsu.edu

Office Hours: M, W, F 4:30pm-5:30pm

Class Days/Time: M 6:00-8:45pm

Classroom: E341

Prerequisites: Classified graduate standing or graduate advisor consent.

Course Description

Design of CISC and RISC user instruction sets and micro-program instruction sets. Data
flow architecture: registers, ALU, shifter, I/O, memory, interrupt. Microcontroller
architecture and state machine.

Course Goals and Student Learning Objectives

 be able to demonstrate an understanding of advanced knowledge of the practice of
computer engineering from concept to analysis, design, validation and
deployment.
 be able to tackle complex engineering problems and tasks, using contemporary
engineering principles, methodologies and tools.
 be able to demonstrate leadership and the ability to participate in a teamwork
environment with different disciplines of engineering, science and business.
 be able to communicate effectively, in both oral and written forms.
Course Content Learning Outcomes
Upon successful completion of this course, students will be able to:
 Understand how assembly language instructions map to hardware operations:
data-path and control circuitry.
 Understand the classic pipelined RISC architecture, including analysis of
dependencies, stalls and hazards, and additionally single- and multi-cycle
controller design and cache architectures.

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  Understanding enhancements of the basic pipelined architecture such as
superscalar, Instruction Parallelism, Dynamic Branch Prediction, Out-of-order
execution and Register Renaming, Score-boarding and Tomasulo’s algorithm, etc.
 Examples from past computer designs, instructor’s experience in computer system
design companies
 Getting students participate in classroom discussions of possible solutions to
specific example problems

Required Texts/Readings
Textbook
John L. Hennessy and David A. Patterson. Computer Architecture - A Quantitative
Approach, 4th Edition, 2007 ISBN: 9780123704900
Other Readings
John L. Hennessy and David A. Patterson. Computer Organization and Design – The
Hardware/Software Interface 4th Edition, 2009 ISBN: 9780123744937
Other equipment / material requirements (optional)
Class notes will be provided by the instructor.

Classroom Protocol
Students will turn their cell phones off or put them on vibrate mode while in class. They
will not answer their phones in class. Students whose phones disrupt the course and do
not stop when requested by the instructor will be referred to the Judicial Affairs Officer
of the University.

We will take breaks during the class sessions. If you need to leave for any reason at other
times, please do so quietly. There is no need to ask permission. Students are expected to
stay in their seats during the entire exam period. If you have medical needs to move
during an exam, please inform me before the exam day.

Dropping and Adding

Students are responsible for understanding the policies and procedures about add/drop,
grade forgiveness, etc. Refer to the current semester’s Catalog Policies section at
http://info.sjsu.edu/static/catalog/policies.html. Add/drop deadlines can be found on the
current academic calendar web page located at
http://www.sjsu.edu/academic_programs/calendars/academic_calendar/. The Late Drop
Policy is available at http://www.sjsu.edu/aars/policies/latedrops/policy/. Students should
be aware of the current deadlines and penalties for dropping classes.

Information about the latest changes and news is available at the Advising Hub at
http://www.sjsu.edu/advising/.

Computer Architecture, CMPE 200, Spring 2011 Page 2 of 5

Assignments and Grading Policy
Grading: Midterm I 15%
Homework I 10%
Quiz I 10%
Midterm II 15%
Homework II 10%
Quiz II 10%
Final Exam 30%

The instructor may provide reference materials. To increase integrity, there may be more
than one version of an exam, and you will be assigned seating for the exam.

Grading Scale:
A+ 98 – 100%
A 90 – 97%
A- 88 – 89%
B+ 86 – 87%
B 80 – 85%
B- 78 – 79%
C 70 – 77%
D 60 – 69%
F 59% and less

(Any category may be changed by +/- 5 to 10% at the discretion of the instructor.)

University Policies
Academic integrity
Your commitment as a student to learning is evidenced by your enrollment at San Jose
State University. The University’s Academic Integrity policy, located at
http://www.sjsu.edu/senate/S07-2.htm, requires you to be honest in all your academic
course work. Faculty members are required to report all infractions to the office of
Student Conduct and Ethical Development. The Student Conduct and Ethical
Development website is available at http://www.sa.sjsu.edu/judicial_affairs/index.html.
Instances of academic dishonesty will not be tolerated. Cheating on exams or plagiarism
(presenting the work of another as your own, or the use of another person’s ideas without
giving proper credit) will result in a failing grade and sanctions by the University. For
this class, all assignments are to be completed by the individual student unless otherwise
specified. If you would like to include your assignment or any material you have
submitted, or plan to submit for another class, please note that SJSU’s Academic Policy
S07-2 requires approval of instructors.
Campus Policy in Compliance with the American Disabilities Act
If you need course adaptations or accommodations because of a disability, or if you need
to make special arrangements in case the building must be evacuated, please make an

Computer Architecture, CMPE 200, Spring 2011 Page 3 of 5

appointment with me as soon as possible, or see me during office hours. Presidential
Directive 97-03 requires that students with disabilities requesting accommodations must
register with the Disability Resource Center (DRC) at http://www.drc.sjsu.edu/ to
establish a record of their disability.

Computer Architecture, CMPE 200, Spring 2011 Page 4 of 5

 CMPE 200 / Computer Architecture, Spring 2011
Schedule

The schedule is subject to change with prior notice. The instructor may get ahead of the
schedule, and then review.

Table 1 Course Schedule

Week Date Topics, Readings, Assignments, Deadlines

1 Jan 31, 2011 An Overview of Computer Design - Introduction

2 Feb 7, 2011 Computer Architecture Fundamentals/ISA

3 Feb 14, 2011 ISA and Examples/Data Path

4 Feb 21, 2011 RISC/Single-clock, Multi-clock Control

5 Feb 28, 2011 QUIZ1, RISC/Multi-clock Control, Pipelines

6 Mar 7, 2011 Pipelines – HW1 due

7 Mar 14, 2011 Instruction Level Parallelism: Branch Prediction

8 Mar 21, 2011 Midterm I

9 Mar 28, 2011 SPRING RECESS

10 Apr 4, 2011 Instruction Level Parallelism: Dynamic Scheduling, Scoreboarding

11 Apr 11, 2011 QUIZ2, Instruction Level Parallelism: Tomosulo’s Algorithm

12 Apr 18, 2011 Register Renaming, Reorder Buffers – HW2 due

13 Apr 25, 2011 Midterm II

14 May 2, 2011 Memory Hierarchy, Caches

15 May 9, 2011 Memory Hierarchy, Caches

16 May 16, 2011 Review

Final
Exam May 23, 2011 E341, 17:15 – 19:30

Computer Architecture, CMPE 200, Spring 2011 Page 5 of 5