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dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING
KwgDwb‡Kkb BwÄwbqvwis wefvM
UNIVERSITY OF DHAKA
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E-MAIL: APECE@univdhaka.edu

Ref. No............................ May 30, 2010

Dated, the………………………….

Flash A/D Converter:

The flash converter is based on using a number of comparators and the highest-speed ADC available, but it requires
much more circuitry than the other types. The number of comparators needed for n-bit A/D conversion is 2n-1.
To understand the principle of operation of flash ADC, a three-bit flash converter is used in order to keep the circuitry
at a workable level.
+10V

3k
C7
7V I7
.
. .
1k
C6
6V I6
.
. .
1k
C5 MSB
5V
. I5 . C
. . .
Digital
1k Priority B output
4V C4 encoder .
. I4 .
. . A Analog in Comparator outputs Digital outputs
1k . VA C1 C2 C3 C4 C5 C6 C7 C B A
C3
3V
. I3 0-1V 1 1 1 1 1 1 1 0 0 0
. . 1-2V 0 1 1 1 1 1 1 0 0 1
1k 2-3V 0 0 1 1 1 1 1 0 1 0
C2
2V
. I2 3-4V 0 0 0 1 1 1 1 0 1 1
. . 4-5V 0 0 0 0 1 1 1 1 0 0
1k 5-6V 0 0 0 0 0 1 1 1 0 1
C1 6-7V 0 0 0 0 0 0 1 1 1 0
1V I1
.
. . >7V 0 0 0 0 0 0 0 1 1 1
1k
Analog input, VA
.

Fig.: Three-bit flash ADC – circuitry and truth table.

The three-bit flash converter uses seven comparators and the comparators are fed into an active-LOW priority
encoder that generates a binary output corresponding to the highest-numbered comparator output that is LOW.
The converter has a three-bit resolution and a step size of 1V. The analog signal, VA, to be digitized serves as one of
the inputs to each of the comparators.
The second input for each of the comparators is a reference input. The voltage divider sets up reference levels for
each comparator so that there are seven levels corresponding to 1V, 2V, 3V, . . ., and 7V. In general, the reference
voltages to be used for comparators are V/2n, 2V/2n, 3V/2n and so on, where V is the maximum amplitude of the
analog signal that the A/D converter can digitize and n is the number of bits in the digitized output.
The output status of various comparators depends upon the input analog signal VA. For instance, with VA<1V, all of
the comparator outputs C1 through C7 will be HIGH.
When VA is between 3 and 4V, outputs C1, C2 and C3 will be LOW and all others will be HIGH. The priority encoder
will respond only to the LOW at C3 and will produce a binary output CBA=011, which represents the digital equivalent
of VA, within the resolution of 1V.

Lec-07, Pg-01 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
 `~ivjvcbx t Telephone :
wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING
KwgDwb‡Kkb BwÄwbqvwis wefvM
UNIVERSITY OF DHAKA
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E-MAIL: APECE@univdhaka.edu

Ref. No............................ May 30, 2010

Dated, the………………………….

When VA is greater than 7V, C1 to C7 will all be LOW and the encoder will produce CBA=111 as the digital equivalent
of VA.
The flash ADC, described here, has a resolution of 1V because the analog input must change by 1V in order to bring
the digital output to its next step. To achieve finer resolutions, the number of input voltage levels and the number of
comparators must be increased.
The conversion time is the time it takes for a new digital output to appear in response to a change in analog input and
it depends only on the propagation delays of the comparators and encoder logic. For this reason, flash converters
have extremely short conversion times.

Digital Voltmeter:
A digital voltmeter converts an analog voltage to its BCD-code representation, which is then decoded and displayed
on some type of readout. Figure shows a three-digit DVM circuit that uses a digital-ramp ADC
Decoder/driver Decoder/driver Decoder/driver
and display and display and display

4-bit 4-bit 4-bit

register register register

Clock

BCD counter BCD counter

BCD counter
(MSD) (LSD)

BCD-to-Analog converter
F.S.=9.99V

VAX
- COMP
Analog input +
VA
VT=0.1mV

To RESET
inputs of Q2 Q1
counters
OS2 T OS1 T
Q2 Q1

Fig.: Continuous-conversion DVM using a digital-ramp ADC.

Three cascaded BCD counters provide the inputs to a three-digit BCD-to-analog converter that has a step size of
10mV and a full-scale output of 9.99V. Each BCD counter stage also drives a four-bit register that feeds a

Lec-07, Pg-02 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
 `~ivjvcbx t Telephone :
wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING
KwgDwb‡Kkb BwÄwbqvwis wefvM
UNIVERSITY OF DHAKA
XvKv wek¦we`¨vjq DHAKA-1000, BANGLADESH
XvKv-1000, evsjv‡`k FAX: 880-2-8615583
E-MAIL: APECE@univdhaka.edu

Ref. No............................ May 30, 2010

Dated, the………………………….

decoder/driver and a display. The contents of the BCD counters are transferred to the registers at the end of each
conversion cycle, so that the displays do not show the counters resetting and counting, but only the final count that
represents the unknown voltage.
VA

.
..
.
VAX ..

COMP
End of conversion
Time
Final count transferred to register
Q1
Reset counter to begin new conversion
Q2
Fig.: Waveform for a DVM.
As long as VAX<VA, the COMP output stays HIGH, and the clock pulses pass through the AND gate to the counter. As
the counter increments, the VAX signal increases at 10mV per step until it exceeds VA. At that point COMP goes LOW
to disable the AND gate and stop the counter, thereby ending the conversion.
The NGT of COMP triggers a one-shot (OS1) to produce a 1-µs pulse at Q1. The PGT of Q1 transfers the outputs of
the BCD counter stages to their respective registers to be stored and displayed.
The NGT of Q1 triggers a second one-shot (OS2) to produce a pulse that resets all the counters to 0. This brings VAX
back to 0 and COMP returns HIGH, allowing pulses into the counter to begin a new conversion cycle.
Thus, this DVM will perform one conversion right after another.
The storage registers will keep the displays from showing the conversion process. The display readings will change
only if VA changes, so that different counter contents are transferred to the registers at the end of the conversion
cycle.
The DVM can be modified to read input voltages over several ranges by using a suitable amplifier or attenuator
between VA and the comparator.
The DVM can be modified to operate as a DMM that can measure current and resistance as well as voltage.
To measure current, the unknown current is made to flow through a fixed reference resistor to produce a voltage.
To measure resistance, a fixed reference current is made to flow through the unknown resistance to develop a
voltage. The resulting voltage is then fed to the circuit to be measured and displayed.
AC voltages can also be measured by this DVM if they are first converted to a dc voltage.
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

Lec-07, Pg-03 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)