Professional Documents
Culture Documents
Abstract- In this paper, authors propose a novel on an expensive cost and their implementation becomes
competitive multilevel topology. It combines advantages very complicated.
of the flying capacitor and the cascaded H-bridge For inverter operation, when number of desired voltage
topologies. It presents several advantages which will be level exceeds three, cascaded H-bridge inverters topology
thereafter detailed. The proposed topology is becomes the optimal solution. This is due to their small
characterized by a reduced impact on the utility supply, number of switches and passive components. However, this
a good energetic efficiency and a small number of topology requires independent and isolated DC voltage
switches and passive components. It presents also the sources, which leads to the use of transformers.
possibility and the simplicity of changing the number of
voltage levels only by acting on-line on the ratio of the In the last few years, many optimizations have been
desired output voltages. An average model of the presented to improve their efficiency [4-10]. In these
proposed topology is performed and the control strategy papers, authors propose multilevel inverters synthesizing a
is designed to draw a nearly sinusoidal current in order large number of levels with improved output waveforms
to avoid the use of filters. The modeling and control characterized by a low distortion and smaller filter size.
strategy of the proposed topology were verified by In this paper, we propose a novel multilevel topology which
simulation. can be classified as a mid-point between the flying capacitor
and the cascaded H-bridge inverters topologies. Compared
Index terms: multilevel converters, harmonics, unit power to these topologies, the proposed one uses small number of
factor operation, average model switches. Moreover, in inverter mode, it permits to reduce
the number of transformers. In rectifier mode, it gives
multiple output voltages which are independents, so we can
I. INTRODUCTION
use the first as a DC bus and the other one as an auxiliary
Due to their ability to synthesize waveforms with a better output voltage. The impact of the proposed topology on the
harmonic spectrum and attain higher voltages, and to utility supply is very limited. With this topology,
overcome the limited semiconductor voltage and current modulation frequency can be very low which improves the
ratings, multi-level inverters are receiving an increasing energetic efficiency of the installation. The proposed
attention in the past few years[1]. topology modeling is performed using an average approach.
The control strategy is designed to produce a nearly
By generating high voltage with low harmonics contents sinusoidal current and to alleviate the harmonic content of
and reducing the switches stress, multilevel converters the output voltage. The filters can thus be smaller or even
permit an effective high power exchange. eliminated.
Traditional multilevel converters like neutral point
II. THE PROPOSED TOPOLOGY
converters NPC proposed by Nabae, Takahashi and Akagi
[2] and flying capacitors converters FCC proposed by A topological optimization of the classic cascaded H-bridge
Meynard and Foch [3] present many drawbacks if the inverters results on a new competitive topology which use
number of voltage levels grows. In fact, the number of small number of passive and active components and avoid
switches, diodes and capacitors grows excessively resulting the use of transformers (figure1).
k,(((
A comparison of seven levels classic converters topologies ⎧ 1 if Ti is ON
and the proposed one is given in table1. The seven levels Si = ⎨ (1)
neutral point converter NPC and the flying capacitors ⎩0 if Ti is OFF
converter FCC one, use a very high number of switches, From figure 4, we can write:
diodes, and capacitors, whereas the classic cascaded H-
bridge inverters topology use only eight switches. The ⎧V Aa1 = −(1 − S1).V 1
⎪
proposed topology, however, uses only six switches. ⎨V a1a 2 = (1 − S 2)(V 1 − V 2) (2)
⎪V
⎩ a2N = (1 − S 3).V 2
TABLE 1
Comparison of seven levels classic topologies and the proposed one We can write also:
NPC FCC Cascaded H- Proposed
⎧i1 = S1.is
⎪
bridge topology ⎨i 2 = S 2.is (3)
Capacitors 6 6 2 2 ⎪i3 = S 3.is
⎩
Clamping 30 0 0 0
diodes
Switches 12 12 8 6
Adding VAa1, Va1a2 and Va2N gives:
VAN =VAa1 +Va1a2 +Va2N = (S2 − S1).V1+ (S3− S2).V2 (4)
Moreover, the proposed topology presents other important
advantage: the switch which must support the highest Applying Kirchhoff’s Current Law (KCL) to the node a1
voltage operates at the lowest switching frequency, and gives:
vice-versa. This reduces the switches stress and improves i1 = i 2 + ic1 + I 1 (5)
the performance of the converter.
Where ic1 and I1 are the C1 capacitor current and the C1
capacitor load current respectively.
dV 1
ic1 = C1. = i1 − i 2 − I 1 (6)
dt
Thus, we can write:
dV 1 (S1 − S 2).is I1
= − (7)
dt C1 C1
By the same, applying Kirchhoff’s Current Law (KCL) to
the node a2 gives:
i 2 = i3 + ic 2 + I 2 (8)
So we can conclude:
dV 2 (S 2 − S 3).is I 2
= − (9)
dt C2 C2
Applying Kirchhoff’s Voltage Law to the converter input
loop gives:
dis
V AN = − R s .is − L s + es (10)
dt
Fig. 1: The classic cascaded H-bridge inverters and the proposed topology
By comparing (4) and (10), we can conclude:
III. MODELING AND CONTROL DESIGN OF THE PROPOSED
TOPOLOGY dis es − R.s is − (S 2 − S1).V 1 − (S 3 − S 2 ).V 2 (11)
=
dt Ls
Ti and Ti′ switches operate complementarily. Let S i be a
switching function of Ti switch where i={1, 2, 3}. S i is Let d1, d2 and d3 be duty cycles of switches T1, T2 and T3
defined by: respectively. Duty cycles are defined by:
k,(((
Fig. 2: Zoom on line current
1 Ts
Ts ∫0
d1 = S1dt Fig. 3: Average model of the proposed topology
From figure 2 we can write: The model of the source-converter-load system can be
written by the following matrix equation:
1 Ts 1 1 ⎛ I −I ⎞
is.dt = (Ts .I1) + ⎜Ts . 2 1 ⎟
Ts ∫0
I= (13) dX
Ts Ts ⎝ 2 ⎠ = F ( X ) + G ( X ).U + C (16)
dt
If we consider the two following areas:
Where:
A1 = Ts .I1 is the blue shaded area ⎡ es ⎤
⎡ − R s x1 ⎤ ⎢L ⎥
I 2 − I1 ⎡ x1⎤ ⎢ L ⎥ ⎢ s ⎥ ⎡u1 ⎤
A2 = Ts . is the red shaded area ⎢ ⎥ ⎢ s ⎥ - I1 ⎥
2 X = ⎢ x 2⎥, F(X) = ⎢ 0 ⎥, C = ⎢ , U = ⎢⎢u 2 ⎥⎥
⎢ C1 ⎥
We can consider that A1>>A2. So we can assume the line ⎢⎣ x3⎥⎦ ⎢ 0 ⎥ ⎢- I ⎥ ⎢⎣u 3 ⎥⎦
current to be constant in a switching period. Thus, we can ⎢ ⎥ ⎢ 2⎥
conclude that: ⎣ ⎦ ⎢⎣ C2 ⎥⎦
Ts Ts
1 is
Ts ∫ S i .i s .dt = Ts ∫ S i .dt = i s .d i (14) ⎡ x2 x3 − x 2 − x3 ⎤
0 0 ⎢L Ls L s ⎥⎥
⎢ s
Let x1, x2 and x3 be the state variables of the source- x − x1
and G(X) = ⎢ 1 0 ⎥
converter-load system defined by: ⎢ C1 C1 ⎥
⎢ x1 − x1 ⎥
⎢ 0 ⎥
x1 = i s , x 2 = V1 and x 3 = V2 ⎢⎣ C2 C 2 ⎥⎦
Then, the system state equation is given by: The determinant of matrix G is null, then G is not invertible.
Noting that state variables x2 and x3 serve to generate x1
⎧ dx1 es − R.s x1 − (d 2 − d1).x2 − (d 3 − d 2).x3 reference, then we can exclude one of them, and with the
⎪ dt = Ls
⎪ following supposition, the problem is solved:
⎪ dx2 (d1 − d 2).x1 I1 (15)
⎨ = -
u1 + u 2 + u 3 = 1.5 (17)
⎪ dt C1 C1
⎪ dx3 = (d 2 − d 3).x1 - I 2
⎪ dt C2 C2 Inputs u1, u2 and u3 vary between 0 and 1, then we have
⎩
chosen to center them in their variation intervals. This
justifies our proposition in equation (17).
k,(((
Applying a PI linear control method to each subsystem IV. SIMULATION RESULTS
gives:
k,(((
Fig. 6. Rectifier input voltage
1
B. Seven level rectifier operation ( k = )
3
The proposed topology presents the possibility of changing
the number of voltage levels from five to seven, or vice-
x3ref
versa, only by acting on the ratio k = . This is obtained
x 2 ref
x 2 ref x 2ref
when decreasing the auxiliary voltage from . to
2 3
The auxiliary voltage reference is now controlled to be the
third of the DC bus voltage. Simulation was made with the
same parameters of section A. Fig. 9: source voltage and line current before and after load change
Fig. 10: Zoom on the sum of duty cycles (condition of equation 17)
k,(((
The proposed topology offers:
k,(((