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Assignment 3: WCET
Note:
Grade 3: only mandatory part must be turned in and passed.
Grade 4 and 5: both mandatory and voluntary part must be turned in and passed.
Introduction
This assignment is focusing on Worst-Case Execution Time (WCET) analysis. Most of the
answers to the given questions can be found in the course reading material and in the lecture
handouts, but some of the answers you have to come up with yourself or find at other places
(such as for example the Wikipedia). Most questions should be possible to answer with a few
sentences, and the total size of the answers should be no more than three A4 pages.
Assignment 1
What are the fundamental methodological differences between a static WCET analysis tool,
such as aiT, Bound-T and SWEET, and a hybrid WCET analysis tool, such as RapiTime?
Assignment 2
In WCET flow analysis terms such as control-flow graphs (CFGs), call-graph (CG), and
infeasible paths are commonly used. Write a small code snippet containing at least two
functions, and draw the corresponding CFGs and CG. One of the functions should also
contain an infeasible path, i.e., a path of nodes from the start node to the end node of the
function's CFG which can never be executed. Moreover, none of the nodes in the infeasible
path should hold dead code, i.e., each node should have some function input values that
forces it to be executed. (Hint: you may need to call the function several times with different
input values).
Assignment 3
Assignment 4
Figure 1 below depicts a control-flow graph (CFG) for a small assembler code snippet (similar
to the code snippet presented in the lecture slides). The CFG consists of four basic blocks: A,
B, C, and D, where A and B hold four instructions each, and C and D hold two instructions
each.
Your task is to derive BCET and WCET estimates (by hand) for the code snippet for some
different cases, allowing you to see how things such as initial cache contents, input values,
code linkage, and interrupts might affect its execution time. For each case you can make the
following assumptions: each instruction always takes 1 clock cycle to execute unless it
experiences an instruction cache miss. When an instruction experience an instruction cache
miss it instead takes 10 clock cycles to execute. In all cases a simple direct-mapped
instruction cache is used, where each cache line (numbered 0,1,2,..,n) can hold exactly 4
instructions.
a) Assume that all instructions in A goes to cache line 0, all instructions in B goes to
cache line 1, and all instructions in C and D goes to cache line 2. Further assume that
the loop condition basic block C always is executed exactly 3 times (which means
that B is executed 2 times). Derive the best-case- and worst-case execution time for
the code snippet under these assumptions. (Hint: you can assume any cache
contents at the start of the execution of the code).
Embedded Systems II – DVA404
b) Now assume that all instructions are mapped to cache lines as in case a), but that the
loop condition basic block C can be executed in between 2 and 4 times (depending
on the initial content of register r1). Given these assumptions, derive the best-case-
and worst-case execution time for the code snippet and compare it to the
corresponding estimates derived in case a).
c) Now assume that some other part of the code in your system is changed somewhat
or maybe recompiled with some other compiler settings, i.e., the analyzed code
snippet itself is unaltered. As a result, the start address of the analyzed code snippet
get changed during the code linking phase (e.g., due to that the other code shrunk or
got larger than before), and correspondingly the mapping of its instructions to diff
erent cache lines is changed. The new mapping looks as follows: the first two
instructions in A goes to cache line 0, the remaining instructions in A and the first two
instructions in B goes to cache line 1, the remaining instructions in B and the
instructions in C goes to cache line 2, and the instructions in D goes to cache line 3.
Further assume that basic block C always is executed exactly 3 times. Based on
these assumptions, derive the WCET for the code snippet and compare it to the
WCET derived in case a).
d) Finally assume that the execution of your code snippet might be interrupted by some
other task or interrupt routine. Further assume that the code executed during the
interrupt might alter the content of the instruction cache significantly (e.g., throwing
out all instructions in the cache belonging to the analyzed code snippet). Assuming
the cache mappings and node execution bound in a), and that the analyzed code
snippet can get interrupted just once, but that the interrupt may occur at any
instruction in the code snippet, derive a new WCET for the code snippet, (which
includes the additional cost for the cache misses occurring due the interrupt).
Compare your derived WCET with the WCET derived in case a). (Hint: some places
for the interrupt to occur are worse than others).