Giao Trinh He Thong Nhung - VDK H8

Chapter 1
Microprocessor Operation
This chapter lets you understand that the microprocessor is built of a

CPU, memory and data input/output ICs, that it operates on a "stored program"
basis, and that it is available in multi-chip/single-chip architectures.
These concepts are not confined to the H8/300H but extend to all other
kinds of microprocessors.
1.1 Microprocessor Configuration
The microprocessor is said to be a "computer built around ICs."

Mainframes, minis, and microprocessors all share the same principles of
operation and vary only in their scale, speed and architecture. The minimum
components required to build a computer are the CPU, memory and I/O
devices as shown in Figure 1.1.
Figure 1.1 Microprocessor configuration
All these components of a microprocessor are fabricated of a single IC.

Such ICs are coupled to build a computer. Three minimum ICs needed to make
up a microprocessor are the CPU, memory, and peripheral IC.
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CPU (Central Processing Unit)
The CPU forms the nucleus of any computer by executing instructions.
Microprocessors are grouped into 4-bit, 8-bit, 16-bit, and 32-bit
microprocessors according to the length of bits they can handle at a time. A 4-
bit microprocessor can handle four binary digits in a single instance of
calculation, but as many as eight digits in two instances and 16 in four
instances.
The microprocessor is also known as a "MPU (microprocessing unit)",
"microprocessor", or simply "processor."
Memory (Memory)
A device on which instructions and data are stored. Without memory,
programs and data cannot be used. In a microprocessor, ROM (read-only
memory) and RAM (random access memory) are used.
Input device (Input)

A data input device. The keyboard and mouse of a PC, for example, are
data input devices. With a built-in controller, switches and sensors are input
devices.
These input devices cannot be directly connected to a CPU, but they
must be attached to the CPU by way of a "peripheral IC," containing
connection circuitry. Depending on the kind of input device to be connected to
the CPU, an appropriate peripheral IC is used.
Output device (Output)

A data output device. The display and printer of a PC, for example, are
data output devices. With a built-in controller, display LEDs, motors, heaters
and so on are output devices. Like input devices, output devices are attached to
a CPU by way of a "peripheral IC." Depending on the kind of output device to
be connected to the CPU, an appropriate peripheral IC is used.
Input devices and output devices are collectively called "peripherals."
1.2 Stored Program Computers
The stored program computer provides a most precise concept of the

operating principles of a computer. It might be safely said that "All modern
computers are stored program computers." The stored program computer was
first conceptualized in 1947 by John von Neumann and is also known as a
"Neumann computer."
In the stored program computer, the CPU reads instructions stored in
memory in sequence, decodes and executes them.
The act of the CPU reading an instruction from memory is called
"fetch." Interpreting the fetched instruction to see what operation it defines is
called "decode." The CPU then proceeds to perform, or "execute," the
operation defined by the instruction. When the CPU has finished executing the
instruction, it fetches the next instruction. After all, the CPU infinitely repeats
the following cycle of operations:
- Instruction fetch
- Instruction decoding
- Instruction execution
Any microprocessor has a program counter in its CPU. The program
counter always holds the "address of the next instruction to be executed."
When the CPU reads an instruction, the program is automatically updated to
indicate the address of the next instruction in sequence. The program counter
thus ensures that instructions stored in memory will be executed in correct
sequence.
Figure 1.2 Operating principles of a stored program computer
1.3 Memory
Memory devices are broadly classified into two categories: ROM (read-
only memory) and RAM (random access memory).
You can only read stored data from ROM but cannot write to it. Stored
data is preserved intact, however, when the microprocessor is switched off. Use
ROM to store valuable data that needs to be protected from erasure in times of
power failures, typically, programs. Instructions are stored in ROM. Each
meaningful collection of instructions is a program. Any microprocessor would
be inoperable unless it comes up with "programs available for ready use" when
switched on. ROM fills this need.
Data can be written to and read from RAM as desired. Stored data
would be lost, however, once the microprocessor is switched off. Even when
the microprocessor is switched on again, previous data is no longer left. Hence,
RAM is used as temporary data storage. Programs may also be placed in RAM,
but will be lost once the microprocessor is switched off. To run programs in
RAM, it is necessary to attach an external storage device, such as a floppy disk
or hard disk drive, and transfer the programs to RAM from external storage to
RAM when the microprocessor is switched on.
Mask ROM (Mask ROM)
When a memory IC is manufactured in the factory, programs are

written to it. A mask is a plate of glass imprinted with patterns of wirings and
transistors used in the IC manufacturing process. Users have a semiconductor
manufacture custom-build a mask to manufacture a memory IC.
Advantages
- Suitable for volume production
- Low cost
Disadvantages
- Long lead-time from ordering to completion
- Not reprogrammable once built
EPROM (Erasable & Programmable ROM)

Stored data can be erased by ultraviolet irradiation. To this end, a
special package with a glass window is used. An EPROM writer is used to
write to EPROM. EPROM is erasable and programmable about 100 times.
Advantage
- Erasable and programmable and thus convenient for testing and debugging
Disadvantage
- Expensive because of the use of a special package
OTPROM (One Time Programmable ROM)

An EPROM chip housed in an inexpensive plastic package. Stored data
cannot be erased by ultraviolet irradiation because no glass window can be
attached to the plastic package. OPTROM can be written only once, but it
comes by far cheaper than EPROM. Programs are debugged in EPPROM and,
when finalized, moved to OTPROM for volume production.
Advantage
- Cheaper than EPROM and suitable for small-batch production
Disadvantage
- Not erasable and programmable
EEPROM (Electrically Erasable & Programmable ROM)

EEPROM can be electrically erased and programmable, and can be
reprogrammed when mounted on a board as a finished product. EEPROM is
reprogrammable about tens of thousand times.
Advantages
- Onboard reprogrammable
- Ready for infinite times of reprogramming
Disadvantage
- Expensive
Flash memory (Flash Memory)

A variation of flash memory, which is cheaper and larger-sized.
Advantage
- Cheaper and larger-sized than EEPROM
Disadvantages
- Unable to write address by address, unlike EEPROM
- Memory IC divided into blocks for erasure and reprogramming block by
block
Static RAM (Static RAM)

RAM with its storage circuit built of flip-flops. Given a supply voltage,
static RAM preserves stored data intact. It dissipates least power when out of
use. Because six transistors are used to build its flip-flops, static RAM offers
less storage capacity than does ROM.
Advantages
- Fast
- Low power consumption and suitable for battery backup
Disadvantages
- Expensive
- Small storage capacity
Dynamic RAM (Dynamic RAM)

Simplified storage circuitry with only one capacitor and one transistor
to provide each bit of memory, and hence larger-sized than static RAM.
Charges on the capacitors, however, drain with time, resulting ultimately in
loss of stored data. Before such loss, all stored data must be read out and
refreshed. Power alone does not allow dynamic RAM to retain stored data but
requires refreshing for that purpose.
Advantage
- Cheap and large-sized
Disadvantage
- Refreshing required
Table 1.1 summarizes features of key ROM and RAM devices.
Table 1.1 Kinds and features of memory devices
Kind Features
Large-sized, cheap, volume production use, custom
Mask ROM
fabrication, not reprogrammable
Programmable and erasable by ultraviolet
EPROM
irradiation. Testing, debugging
Low-volume production use, one-time
ROM OTPROM
programmable
Electrically programmable, onboard
EEPROM
reprogrammable
Electrically erasable and programmable, cheaper
Flash memory
and larger sized than EEPROM
Stored data preserved under voltage input alone,
Static RAM
fast, battery backup use
RAM
Refreshing required to preserve data, large-sized,
Dynamic RAM
cheap
1.4 Single-Chip/Multi-Chip Microprocessors
Putting a CPU, ROM, RAM, and data input/output circuitry into a

single IC will make a single-chip microprocessor. Single-chip microprocessors
come compact and cheap, but do not allow users to choose built-in functions at
their option. Single-chip microprocessors are also known as "microcomputer
units (MCUs)," because they are made of a single IC.
On the other hand, a computer fabricated from a mix of a CPU, memory and
data input/output devices is called a "multi-chip microprocessor." Multi-chip
microprocessors offer users greater freedom in their component choice. Multi-
chip microprocessors will prove more advantageous for larger systems
involving complexities of input/output. See how a single-chip microprocessor
and a multi-chip microprocessor differ in Figure 1.3.
Figure 1.3 Single-chip microprocessor and multi-chip microprocessor
Single-chip microprocessors are used as built-in controllers. When a

single-chip microprocessor is switched on, the control program stored in its
internal ROM launches instantly. Internal RAM is used as temporary storage.
The internal data input/output circuits, too, have been chosen to support the
single-chip microprocessor as s controller.
Kinds of internal ROM

Early single-chip microprocessors included only mask ROM and were
available only for use in mass-produced products.
Subsequently EPROM has made inroads into single-chip
microprocessors as internal ROM. As testing and debugging was carried out in
erasable and programmable packages with windows and inexpensive plastic-
packaged OTPROM used on commercialization, single-chip microprocessors
came to be used in products manufactured in small batches as well.
Now, single-chip microprocessors with internal EEPROM and flash
memory are available for use in various applications. As the IC manufacturing
technology has been advancing from year to year, with continuing increases in
the sizes of internal ROM and RAM, state-of-the-art data input/output
functions have been used in single-chip microprocessors in an expanding of
applications.
Microprocessors and memory

A memory device organized into 8 bits per address is used. Each
sequence of 8 bits is called a "byte," and memory sizes are stated in the unit
byte.
64K bytes of memory could be connected to classical 8-bit
microprocessors as standard. This memory size indicates 8 bits per address in a
memory space of 64K (65536 addresses). Eight bits of memory per address are
also connected to 16- and 32-bit microprocessors, as well as 8-bit
microprocessors.
1. What are the three key ICs needed to make up a microprocessor?

(CPU (MPU ) )
(Memory )
(Peripheral IC)
Mainframes and minis share the same computer architecture.
Microprocessors are characterized by the fact that three components of the
computer - namely, the CPU, memory, and input/output circuit (peripheral IC)
- are each fabricated as an IC.
2. Fill the blanks with appropriate words or phrases.

The (stored program computer) provides a most precise concept of the
operating principles of a computer. This was first conceptualized in 1947 by
(John von Neumann).
The stored program computer materializes the principles of a computer
in which the CPU reads instructions from memory and executes them. This is
also known as a "Neumann computer," because of its conceptualization by
John von Neumann.
3. Mention one advantage and one disadvantage for each of the following
kinds of memory:
Mask ROM Advantage (Inexpensive, large-sized )

Disadvantage (Available only on order, not reprogrammable)
EPROM Advantage (Erasable and programmable)

Disadvantage (Expensive )
Dynamic RAM
Advantage (Inexpensive, large-sized )
Disadvantage (Refreshing required )
Mask ROM is volume-produced at factory at low cost, and features

circuit simplicity, offering large-sized memory. Mask ROM can be
manufactured only by order and is not reprogrammable after it is built.
EPROM allows about 100 times of erasure and reprogramming using a
special writer, but the special package with a glass window adds to its cost.
Using capacitors as storage devices, DRAM is simple in circuitry,
inexpensive, and large-sized, but what is inconvenient, it must be refreshed so
that charges on the capacitors do not drain.
4. Mention one advantage and one disadvantage for the microprocessor.
Advantage (Compact, inexpensive )
Disadvantage (Limited internal functionality )

(Small memory size Not suitable for use in larger systems )
A single-chip microprocessor has all functions assembled on a single
chip and therefore comes compact and more inexpensive than purchasing its
components separately. Its scale of integration is limited and is not suitable for
mounting extra-large-sized memory.
Chapter 2
Knowledge of Binary Numbers Prerequisite to Writing
a Program
There are close links between the computer and binary numbers. This
chapter covers the minimum knowledge of binary numbers prerequisite to
writing a program in an assembler language. The concept of binary numbers is
not restricted to the H8/300H but broadly pertains to computers in general.
Without a correct understanding of the topics covered here, you would not be
able to write correct programs. The key concepts of "Signed binary numbers,"
"Carry," and "Overflow," among other things, would be needed instantly.
Even when you have finished with this chapter, refer back to it from
time to time as needed.
The reason why binary numbers are used in the computer is that the
computer is built of digital circuitry. Digital circuitry concerns only two states -
whether a voltage of interest is higher or lower than a given voltage - and not
any intermediate voltage. A higher-voltage state is designated by H, a lower-
voltage state by L. As the computer is a calculator, the two states of H and L
can be more conveniently expressed in numeric terms as 1 and 0 in binary. All
binary numbers that the computer handles correspond to H and L in digital
circuitry.
The unit bit, or binary digit, is used to count binary numbers. For
example, a reference to 8 bits means 8 digits in binary. A sequence of 8 bits is
called a "byte."
2.1 Kinds of Data Handled by Microprocessors
Before starting to consider how data is represented in binary numbers,

let's see what kinds of data are available. Here, data is broadly grouped into
numeric data and character data as shown in Figure 2.1.
Figure 2.1 Kinds of data
Numeric data is classified into unsigned binary numbers, signed binary
numbers that distinguish between positive and negative, and BCD code used to
express decimal numbers.
Character data is used to print or display characters, or enter characters
from the keyboard. The ASCII code is mainly used in microprocessors.
2.2 Numeric Representation in Unsigned Binary Number
Unsigned binary numbers do not allow for the positive or negative

signs. To promote understanding, unsigned binary number may be
conceptually converted to decimal numbers to express values. Consider an
eight-digit binary number as an example.
Since each digit of a binary number has a weight of 2, the least
significant digit is 20, or 1, the next digit is 21, or 2, and still the next digit is 22,
or 4. Thus, the weight doubles on each carry. In converting an 8-bit binary
number to a decimal number, assuming
we get
Decimal representation =
a7*27 + a6*26 + a5*25 + a4*24 + a3*23 + a2*22 + a1*21+ a0*20
10110010 in binary, for example, is converted to a decimal equivalent as

1*27 + 0*26 + 1*25 + 1*24 + 0*23 + 0*22 + 1*21 + 0*20
= 128 + 32 + 16 + 2
= 178
All-one data "11111111" is the largest number that can be expressed in
an 8-bit format. It corresponds to 255 in decimal. Eight-bit unsigned binary
numbers can represent decimal numbers from 0 to 255.
Generally, N-bit unsigned binary numbers can represent the range of 0
to 2N-1
Table 2.1 lists the lengths of unsigned binary numbers and the ranges
they can represent.
Table 2.1 Ranges of unsigned binary numbers

Binary number length Range that can be represented
4 digits (4 bits) 0 to 15
8 digits (8 bits) 0 to 255
16 digits (16 bits) 0 to 65,535
32 digits (32 bits) 0 to 4,294,967,295
Examples of addition of unsigned binary numbers are given below. To
their right are their decimal equivalents.
01001010 74
+ 00111000 + 56
10000010 130
and,
10001001 173
+ 01111010 + 122
1 00000011 3
This calculation, on the other hand, yields an incorrect result. The

resultant 9-bit value of 255 may appear correct, but the fact is that "calculating
in 8-bit terms within the computer delivers a result in 8-bit terms only." You
can stretch or contract the length of a value as long as you work on its
calculation on paper or in your brains, but not in the computer. You need to
remember the length of arithmetic circuitry in the computer at all times.
The addition of an extra digit to the length of a result is called a "carry."
Figure 2.2 Carry in a binary number
Next, examples of subtraction of unsigned binary numbers are given

below. To their right are their decimal equivalents.
10110101 181
− 10010111 − 151
00011110 30
and,
01001111 79
− 01010000 − 80
11111111 255
This calculation yields an incorrect result due to its failure to subtract a

given value from a smaller value, where a 1 was leased from the ninth bit of
the lower value. This is called a "borrow."
When a carry or borrow occurs in the course of a calculation in the

computer, they are stored in status (in the H8/300H, the condition code). When
writing a program, include a condition test instruction to define what specific
action should be taken if a carry or borrow is encountered in the execution of a
calculation instruction.
Generally, no distinction is made between a carry and a borrow in the
computer, but they are collectively called a "carry."
2.3 Numeric Representation in Signed Binary Number
Signed binary numbers distinguish between positive and negative, but

they cannot be prefixed with a sign, as in +10110001 or -11001110. This is
because the computer operates on the basis of digital circuitry in which only
two voltage states H and L exist, as explained earlier. As H and L are
designated by 1 and 0, the positive and negative states must be designated by a
combination of 1 and 0, as well.
To promote understanding, the most significant bit of data is assumed
to designate a sign. Eight-bit data is expressed as
-(a7*27)+ a6*26 + a5*25 + a4*24 + a3*23 + a2*22 + a1*21+ a0*20
Only the most significant bit is treated as being negative. Accordingly,
00000000 represents +0
--------
Thus, signed binary values having their most significant bit being 0 are treated
positive.
10000000 represents -128

--------
Thus, signed binary values having their most significant bit being 1 are treated
negative.
Generally, N-bit signed binary numbers can represent values in the following
range:
-2N-1 to +2N-1-1
Table 2.2 lists the lengths of signed binary numbers and the ranges they
can represent.
Table 2.2 Ranges of signed binary numbers

Binary number length Range that can be represented
4 digits (4 bits) -8 to -1, +0 to +7
8 digits (8 bits) -128 to -1, +0 to 127
16 digits (16 bits) -32,768 to -1, +0 to 32,767
The most significant bit of a signed binary number is called a "sign bit"
because it denotes a sign.
Figure 2.3 8-bit binary numbers
Examples of addition of signed binary numbers are given below.

00000001 +1
+ 11111111 + −1
1 00000000 +0
The result is correct if only the low-order 8 digits are considered.
10000000 - 128
− 00100000 − + 32
1 01100000 + 96
This calculation, on the other hand, gives an incorrect result, because

the correct result of +144 cannot be represented by an 8-bit signed binary
number. Such a state of a result exceeding a predetermined length is called an
"overflow."
Next, examples of subtraction of signed binary numbers are given below.

01010001 + 81
− 01010010 − + 82
11111111 -1
No overflow has occurred in this calculation.
10000000 - 128
− 00100000 − + 32
00100000 + 96
Subtracting a positive value from a negative value should always
deliver a negative value, but an overflow is seen in this case because the result
is positive. Summing up, the following four conditions
Positive value + Positive value = Negative value
Negative value + Negative value = Positive value
Positive value - Negative value = Negative value
Negative value - Positive value = Positive value
are called "overflows."
It is important to note the length of any signed binary number, because
simply prefixing a signed binary number with 0 could result in an inverted sign
as in the following example:
8-bit 1000 0010 is -126
9-bit 0 1000 0010 is +130
Twos complement notation

Signed binary numbers are also called a "twos complement notation." If
summing up two values produces a carry, with the result of 0, then a twos
complement relation exists between the two values as in the following
example:
10110001
+ 01001111
1 00000000
These two values have the same absolute value but differ only in their
sign. Ones complements, too, exist.
10110001
+ 01001110
11111111
If summing up two values results in a complete sequence of 1s, a ones
complement relation is said to exist between them. These two values have their
0s and 1s inverted.
Changing the sign of a signed binary number can be easily done by
creating its ones complement and then adding 1 to it. This is the same as
calculating a complement. As an example, consider converting +12 to -12. +12
can be expressed in an 8-bit format as:
00001100
First, create the ones complement of 00001100:
11110011
Then, add 1 to it to get:
11110100, or -12
2.4 BCD Code
Short for "Binary Coded Decimal," BCD code means a decimal number
expressed in binary. The BCD code represents each decimal digit with a string
of four binary digits. For example, decimal 156 is expressed as 0001 0101
0110 in BCD code.
The addition of BCD coded characters must deliver a decimal result
like 48 + 24 = 72 as in the example:
01001000 48
+ 00100100 + 24
01110010 72
It involves addition different from the ordinary addition of binary numbers. To
this end, special instructions are needed to perform BCD calculations.
2.5 ASCII Code
The ASCII (American Standard Code for Information Interchange)

code is used to represent alphanumeric characters and symbols. The ASCII
code represents each character with 8 bits. Table 2.3 is an ASCII code table.
For example, A is represented by 01000001 and a by 01100001.
When you type 123 from the keyboard and then press the return key,
the following four characters are entered:
Character code of 1 00110001

Character code of the return 00001101
To handle these characters as unsigned binary 123, they must be
converted to the binary number:
01111011
On the other hand, to display signed binary number
10000000
on the display as -128, it must be converted to the four characters:
Character of the minus sign 00101101
Note that the ASCII code is characters, and 1 through 9 are "digits" and
not "numeric values."
[Audiovisual guidance]
2.6 Numeric Representations
While the computer internally operates on the basis of binary numbers,

binary numbers take more digits than decimal numbers to represent the same
value. For example, decimal 100 can be expressed in three digits, but its
unsigned binary equivalent would end up in a seven-digit sequence of
1100100. Hexadecimal numbers save on extra lengths and make values easier
to read. Memory addresses are expressed in hexadecimal in most situations.
Binary notation also comes an effective way of representation as long
as economizing on lengths is concerned, but it involves a laborious binary
conversion process. Hexadecimal numbers are easy to convert to and from
binary numbers, because each hexadecimal digit simply represents a string of
four binary digits.
Table 2.4 gives the correspondence among binary, hexadecimal, and
decimal numbers.
Table 2.4 Correspondence among binary, hexadecimal and decimal

numbers
Binary Hexadecimal Decimal
0000 0 0
0001 1 1
0010 2 2
0011 3 3
0100 4 4
0101 5 5
0110 6 6
0111 7 7
1000 8 8
1001 9 9
1010 A 10
1011 B 11
1100 C 12
1101 D 13
1110 E 14
1111 F 15
In programs, H 'and B' designate hexadecimal notation and binary

notation, respectively. For example, binary 12 is written as H'12, and binary
01011110 is expressed as B'01011110. 12 or 10, when simply stated, means a
decimal number.
Example:
H'12 H' identifies a hexadecimal number. It is 18 in decimal and
00010010 in binary.
B'01011100 B' identifies a binary number. It is 5C in hexadecimal and 92 in
decimal.
110 Decimal number. It is 6E in hexadecimal and 01101110 in
binary.
1. Fill out the blanks below.
Binary notation Decimal notation Decimal Hexadecimal

(8 bits) (unsigned) notation (signed) notation
01001110 78 78 H'4E
01100100 100 100 H'64
11111101 253 -3 H'FD
10000000 128 -128 H'80
Binary notation 01001110

Decimal notation (signed) 01001110 = 64 + 8 + 4 = 2 = 78
Decimal notation (signed) = positive + 78, because the most significant bit is 0
Hexadecimal notation 0100 = 4 and 1110 = E, hence H'4E
Decimal notation (unsigned) 100

Binary notation 100 = 64 + 32 + 4 = 01100100
Decimal notation (signed) = positive + 100, because the most significant bit is 0
Hexadecimal notation 0110 = 6 and 0100 = 4, hence H'64
Decimal notation (signed) -3

Binary notation -3 = -128 + 64 + 32 + 16+ 8 + 4 + 1 = 11111101
Decimal notation (unsigned) 128 + 64 + 32 + 16+ 8 + 4 + 1 = 253
Hexadecimal notation 1111 = F and 1101 = D, hence H'FD
Hexadecimal notation H'80

Binary notation 10000000 = -128
Decimal notation (unsigned) 10000000 = 128
Decimal notation (signed) = negative -128, because the most significant bit is 1
2. Perform the operations given below and calculate the results to a length
of 8 bits. Answer also whether a carry or borrow has been produced from
the operations and whether an overflow has occurred from the results
when they are viewed as signed binary numbers.
Carry ( Yes )
Overflow ( No )
The result is 9 digits, with a carry.

+72 + (-49) = +23, or positive + negative = positive with no overflow
Borrow ( No )
Overflow ( Yes )
No borrow and no carry.

-116 - (+43) = +65, or negative - positive = positive, with an overflow
Chapter 3
H8/300H Series Overview, and H8/3048
This chapter describes the use of an H8/3048 microcomputer from the

H8/300H family. The H8/3048 is a high-performance microcomputer having
ROM, RAM and peripheral functions.
It will help you understand the functions of this product.
3.1 H8/300H Series Product Map
The H8/300H series is a original high-performance, single-chip

microcomputer having a 16-bit CPU as its core together with peripheral
functions required for system configuration. Figure 3.1 shows the product
lineup of the H8 family.
Figure 3.1: Product Lineup of H8 Family
Figure 3.2 shows the product lineup of the H8/300H series.
Figure 3.2: Product Lineup of H8/300H series
3.2 H8/3048 Overview
In this course, an H8/3048 is used as the sample processor from the

H8/300H family. The H8/3048 includes the following three types: one having a
mask ROM or OTPROM as an internal ROM (simply referred to as the
H8/3048), an H8/3048F having an internal writable flash memory with two
power supplies (5V and 12V) and an H8/3048F-ONE having an internal
writable flash memory with a single power supply (5V). The only difference
among them is the type of internal ROM, the rest are almost the same.
Although this chapter describes the overview of the H8/3048F-ONE, the
descriptions in this and following chapters are common to all types. Note,
however, that the training board has been developed based on the H8/3048F-
ONE.
Figure 3.3 shows the H8/3048F-ONE internal block.
Figure 3.3: H8/3048F-ONE Internal Block
Features of CPU
- 16-bit CPU which serves as a general-purpose register machine.
Equipped with 16-bit × 16 general-purpose registers.
(Also available in 8-bit × 16 + 16-bit × 8 or 32-bit × 8 form.)
- High-speed CPU.
The maximum operating frequency of the H8/3048F-ONE is
25MHz and addition/subtraction can be executed in 80ns and
multiplication/division in 560ns.
The CPU is operated based on clock signals and the higher the
clock signal frequency, the faster the operation. The time of one
25MHz clock signal pulse is 0.04 microsecond (40ns), which is called
"1 state". Addition/subtraction are completed in two states and
multiplication/division in 14 states.
- Equipped with a maximum 16M bytes of address space.

(CPU, instructions and programs are described in Chapters 4, 5 and 6.)
Available both as single-chip and multi-chip microcomputer

It can be used as a single-chip microcomputer thanks to the internal
ROM, RAM and data I/O functions in addition to the CPU.
It can also be used as a multi-chip microcomputer when an external
memory is added due to insufficient ROM or RAM capacity. When used as a
multi-chip microcomputer, it has 24 address pins and up to 16M bytes of
memory can be added. Addresses consume 16M, 8 bits per address. Since there
are 16 data pins, 16 bits can be read or written simultaneously.
Internal ROM
It has a 128k byte, writable flash memory with a single 5V power
supply. This enables onboard writing.
For writing to the flash memory, a boot mode using a serial interface is
supported. Writing with a user-defined program is also available.
Internal RAM
It has an internal, 4k byte RAM.
I/O ports: 70 I/O pins and 8 input-only pins

The I/O ports can be used to input switch on/off statuses or signals from
various sensors. When used as output ports, they can control blinking of a
display lamp or turn a motor or heater on and off. The I/O ports are widely
used as general-purpose I/O functions.
On the training board, they are used to read switch statuses and control
LED displays.
Internal SCI (serial communication interface) × 2 channels

Channel 0 is available for a smart card interface.
For start-stop synchronization, it is used for RS-232C and other
communication functions. It is connected to a PC to enable data exchange.
On the training board, it is connected to a PC via RS-232C to send a
created program from a PC to the board or input a command for debugging.
Internal ITU (integrated timer unit) composed of 16-bit timer × 5 channels

Pulse outputs from up to 12 pins and up to 10 types of pulse inputs can
be processed.
It has a wide variety of uses such as measurement of time, speed and
frequency as well as control of pulse motors.
On the training board, a piezoelectric buzzer is provided so that pulses
can be heard as sounds.
Internal TPC (programmable timing pattern controller)

capable of outputting up to 16-bit pulses using the ITU as a time base
In combination with the ITU, a large number of pulse outputs are
available.
Internal watch-dog timer

Program runaway can be detected. Since control using a microcomputer
is based on programs, an extremely dangerous situation may occur if a program
should run away. This function is indispensable for creating a highly reliable
system.
Internal A/D converter with 10-bit resolution × 8 channels

The A/D converter is designed to input analog voltages instead of
digital voltages. For example, signals from a temperature sensor are input not
by high/low digital voltages but analog voltages. These signals are read after
being converted into 10-bit binary numbers.
On the training board, 0 to 5V analog voltages can be input with added
volume.
Internal 8-bit D/A converter × 2 channels

Unlike the A/D converter, the D/A converter is designed to output
analog voltages. It is also used to output desired waveforms or adjust volume
or hue of a TV.
On the training board, LEDs can be driven with D/A-converted output
voltages to control brightness.
Internal DMA controller × 4 channels (max.)

Used for high-speed data transfer. It enables data to be transferred faster
than with the CPU. It is generally used with a timer and other communication
functions.
Internal refresh controller

Refreshing is required to retain the data in the dynamic RAM. This
microprocessor has an internal controller for this purpose.
The H8/3048F-ONE can be used as a single-chip microcomputer. In

this form, no external memory can be added and only the internal one is
available. The operating mode when it is used as a single-chip microcomputer
is referred to as "single-chip mode". Figure 3.4 shows the memory map in
single-chip mode. In this mode, the memory addresses are expressed with 20
bits (5 digits in hexadecimal notation).
Figure 3.4: Memory Map in Single-chip Mode
• For the vector area, refer to "Exception Handling".
• For the memory indirect branch addresses, refer to "Addressing Modes
of Instructions".
• The internal I/O registers are used for peripheral functions such as the
SCI and timer.
Memory indirect
Addressing for branching by storing the destination address in the
memory and specifying it.
This is written in the following format:
@@ address
Memory indirect is available only for the JSR and JMP instructions. An
even-numbered address between H’000000 and H’0000FC can be specified for
an instruction. Not all addresses can be used freely, however, since other
exception handling functions also use the same range.
Sample: JMP @@H'10

Branches to the address stored in the H'10 address.
Although the destination is written with 32 bits in the memory, only the
lower 24 bits are used. An even address must be specified by an instruction.
The address of the memory storing the destination can also be specified using a
symbol. The assembler converts a written symbol into an address, which is
assumed to be the destination.
Sample: JMP @@WORK

Branches to the address written in the WORK address.
The H8/3048F-ONE can also be used as a multi-chip microcomputer.
The operating mode in this case is referred to as "external extension mode". In
external extension mode, a memory or peripheral IC can be connected
externally. Figure 3.5 shows the memory map in external extension mode.
Since there are 24 address buses, up to 16M bytes of external memory can be
added. Addresses are expressed with 6-digit, hexadecimal numbers.
The addresses of the internal ROM, RAM and internal I/O register, however,
are fixed and cannot be changed. If the address of the memory to be added is
the same as that of the internal ROM, RAM or internal I/O register, the internal
function has priority, disabling reading/writing from/to the external memory.
Figure 3.5: Memory Map in External Extension Mode
• For areas 0 to 7, refer to "Connecting CPU to Memory". When creating

a program, you need not take areas 0 to 7 into account.
Although this chapter has described the overview of the H8/3048F-ONE,

table 3.1 shows the differences between the H8/3048, H8/3048F and
H8/3048F-ONE as well as their features for summary.
Table 3.1: Differences Between the H8/3048, H8/3048F and H8/3048F-ONE

and Their Features
H8/3048 H8F/3048 H8/3048F-ONE
CPU 16-bit CPU, general-purpose register machine
Maximum operating
18MHz 16MHz 25MHz
frequency
Address space 16Mbyte max
Flash memory Flash memory
Mask ROM/
(writable with 2 power (writable with single 5V power
Internal ROM OTPROM
supplies, 5V and 12V) supply)
128Kbyte
Internal RAM 4Kbyte
Operating mode Available both as single- and multi-chip microcomputer
Power supply voltage 5V operation: -0.3 to +7.0 (V)
-0.3 to +7.0 (V) -0.3 to +7.0 (V)
Vcc operation: -0.3 to +4.6 (V)
- 78 I/O ports in all: 70 I/O pins and 8 input-only pins
Peripheral functions - SCI x 2 channels
- ITU composed of 16-bit timer x 5 channels
- TPC capable of outputting up to 16-bit pulses
- Watch-dog timer for detecting program runaway
- A/D converter with 10-bit resolution x 8 channels
- 8-bit D/A converter x 2 channels
- DMA controller x 4 channels (max.)
- Refresh controller
1. Enter an appropriate word in parentheses.

The H8/3048 has an internal ( 16 )-bit CPU and up to ( 16M ) bytes of
memory can be connected.
The H8/3048 belongs to the H8/300H series and employs a 16-bit CPU.
It has up to 24 address pins and the memory addresses are expressed in 24-bit
binary numbers. This means that 16M (mega) bytes of memory, or 16,777,216
addresses can be connected.

( SCI ) has a variety of internal I/O functions and can be connected to a
PC.( ITU ) is used to control pulse motors.
SCI is an acronym for Serial Communication Interface used for
communication.
ITU is an acronym for Integrated Timer pulse Unit which serves as a
timer with a pulse I/O function. Its typical application is to control pulse
motors.
Chapter 4
Writing a Simple Program in an Assembly Language
This chapter gives an overview of a program developed in an assembly

language used by the H8/300H. Only basic instructions are introduced here to
help you understand how a program proceeds and how the contents of the
registers and memory change as it progresses.
To understand these subjects, you need a knowledge of binary numbers
described in Chapter 2. Learn how a program is configured and proceeds
before going on to the next chapter which explains instructions in detail.
The assembly language is the most basic programming language and

corresponds to machine instructions one-to-one, making it the most suitable
language for understanding microcomputer operation. Although C-language is
also becoming popular in the microcomputer field, studying programs written
in the assembly language will be very helpful for developing a program with
C-language afterward. The CPU can execute machine instructions only. No
matter in which language a program is written, it must be converted into
machine instructions in the end. Since machine instructions are collections of
0s and 1s, it is difficult to develop a program directly with machine language.
For this reason, assembly language is used since it enables machine language
to be expressed in easily understandable alphabets. For example, a machine
instruction to add the R0L and R1L as an arithmetic register is expressed as
follows in 16 bits:
0000 1000 1000 1001
In assembly language, it is expressed as follows:
ADD.B R0L,R1L
A program written in assembly language is referred to as a source
program.
4.1 CPU Internal Registers
Before developing a program with assembly language, you need to

know what kinds of registers and functions the CPU has. Figure 4.1 shows the
CPU internal registers of the H8/300H.
Figure 4.1: CPU Internal Registers
The internal registers are classified into general-purpose and control

registers.
The general-purpose registers are used to calculate data and store
addresses.
The control register is further classified into the PC (program counter)
to control program progress and the CCR (condition code register) to test
conditions.
How to use general-purpose registers

The CPU has 8 general-purpose registers, each capable of storing 32-
digit binary numbers.In addition to 32-bit data, they can also store 16- or 8-bit
data.
When 32-bit data is stored, they are described as follows in an instruction,

using 8 registers in all:
ER0, ER1, ER2, ER3, ER4, ER5, ER6, ER7
When 16-bit data is stored, they are described as follows in an instruction,

using registers as 16 units in all:
E0, E1, E2, E3, E4, E5, E6, E7, R0, R1, R2, R3, R4, R5, R6, R7
When 8-bit data is stored, they are described as follows in an instruction, using
registers as 16 units in all:
R0H, R0L, R1H, R1L, R2H, R2L, R3H, R3L, R4H, R4L, R5H, R5L, R6H,
R6L, R7H, R7L
This is illustrated in Figure 4.2.
Figure 4.2: General-purpose Register
Example of calculation by general-purpose registers

In this example, an add instruction is used to show how general-purpose
registers are actually used.
ADD.B R0L,R1H is an instruction for 8-bit addition. ADD represents
"ADDition" and B represents "Byte" (8 bits). The contents of the R1H and R0L
are added and the results are stored in the R1H.
This will not influence the E1 or R1L. Only 8-bit results are obtained.
Any 8-bit register is available for this calculation. For example, you can
specify the same register like "ADD.B R1L,R1L". In this case, the R1L is
doubled.
ADD.W R0,E1 is an instruction for 16-bit addition. ADD represents

"ADDition" and W represents "Word" (16 bits). The contents of the E1 and R0
are added and the results are stored in the E1.
This will not influence the R1.Only 16-bit results are obtained.
ADD.L ER0,ER1 is an instruction for 32-bit addition.ADD represents

"ADDition" and L represents "Long word" (32 bits). The contents of the ER1
and ER0 are added and the results are stored in the ER1.
The 32-bit results are stored in the ER1.
SP (stack pointer)
A special function has been added to the ER7 as a stack pointer. The
ER7 is usually not used for calculation but as a stack pointer. The stack pointer
function is described in detail in "Subroutines" and "Interrupt Operations".
PC (program counter)
n the program counter, the "address of the instruction to be executed
next" is always stored and the data is automatically updated every time the
CPU reads instructions. Since the addresses are 24 bits, the PC also has 24-bit
configuration. Programmers need not pay special attention to how the PC is
configured. Every time an instruction is read, the address of the next instruction
is automatically stored.
In the case of the H8/300H, an instruction is always read from an even-
numbered address first. This means that an even-numbered address is always
stored in the PC (see "Data in the memory").
CCR (condition code register)

This is used to control interrupts or test conditions. Although it is an 8-
bit register, every bit has a different meaning. Interrupt control is described in
detail in "Exception Handling".
This section describes the part used for conditional test. Every time an
instruction is executed, the N, Z, V and C bits change to reflect the results.
Conditions are tested based on their changes. An instruction to be tested exists
separately. The N, Z, V and C bits are called "flags".
N (Negative) flag: When the execution results are regarded to be a signed

binary number, set to 1 if it is negative, or 0 if positive.
Z (Zero) flag: Set to 1 if the execution results are zero, otherwise, 0.
V (oVerflow) flag: When the execution results are regarded to be a signed
binary number, set to 1 if it overflows, otherwise, 0.
C (Carry) flag: Set to 1 if execution results in a carry or borrow, otherwise, 0.
Conditional test in a program is performed by these four flags. Any
condition can be tested using them.
Conditional test using the CCR

As for two numeric values, X and Y, let's consider how to test their
collating sequence.To test the collating sequence, subtraction is used. By
subtracting Y from X, the sequence can be tested based on how N, Z, V and C
in the CCR change.
Let's assume that C becomes 1 after subtracting Y from X. This means
that a borrow occurred after subtraction. A borrow occurs when X is less than
Y. If a borrow does not occur, you can judge that X is equal to or greater than
Y.
If Z is 1, X is equal to Y since the subtraction results are zero.If Z is 0, you can
judge that X is not equal to Y.
As described above, the collating sequence can be tested based on C
and Z obtained after subtraction. In this case, however, X and Y are assumed to
be unsigned binary numbers. If they are signed binary numbers, the N or V
flag, instead of C, is used for conditional test.
Data in the memory

The following describes how to store 8-, 16- and 32-bit data into the
memory.
Not only the H8/300H but all 16-bit microcomputers use 8 bits of the memory
per address. So, one 8-bit data block exactly occupies one address.
One 16-bit data block occupies two addresses. The upper 8 bits are stored in a
smaller address and the lower 8 bits in a larger one. The smaller one must be an
even-numbered address. Although each data block is stored separately in two
addresses, the smaller one is regarded to be the address storing the data. For
example, "16-bit data in the H'1000 address" means that the upper 8 bits are
stored in the H'1000 address and the lower in the H'1001 address.
In an instruction to read or write 16-bit data, you should specify an
even-numbered address (smaller address). If you attempt to read or write 16-bit
data by specifying an odd-numbered address, reading/writing will fail. For the
reason why this restriction applies, refer to "Connecting CPU to Memory (16-
bit Data Bus)".
In the case of the H8/300H, an instruction is always read in 16-bit
units. This means that an instruction must be stored in an even-numbered
address. H8/300H machine instructions are composed in 16-bit integral
multiples. If the first instruction falls in an even-numbered address, the
subsequent instructions also fall in even-numbered addresses.
One 32-bit data block occupies four addresses of the memory. Since the
H8/300H cannot read or write 32-bit data at a time, data are divided into 16-bit
units for reading/writing. In this case, the first data must also fall in an even-
numbered address. Likewise, the most significant 8 bits are stored in the
smallest address and the least significant 8 bits in the largest one.
[Explanation with motion pictures and sound]
1. ( T ) There are eight 32-bit general-purpose registers in all.
There are eight general-purpose registers, from ER0 to ER7.
2. ( T ) The ER7 is a stack pointer.
Among the general-purpose registers, only the ER7 has a special stack
pointer function.
3. ( F ) The CCR is a 16-bit register.
The CCR (Condition Code Register) is a control registers with 8-bit
configuration.
4. ( F ) The PC stores the instruction currently being executed.
The PC (Program Counter) does not store instructions but the
"address" of the instruction to be executed next.
5. ( F ) Although the ER0 can perform addition, the ER6 cannot.
All general purpose registers from ER0 to ER7 can handle the same
instructions.(The ER7, however, has a special stack pointer function)
6. ( T ) The least significant 8 bits of the ER0 is the R0L.
The upper 16 bits of the ER0 are the E0 and the lower 16 bits are the
R0.And the upper 8 bits of the R0 are the R0H and the lower 8 bits are the R0L.
7. ( F ) The upper 16 bits of the ER0 is the R0.
The upper 16 bits of the ER0 are the E0 and the lower 16 bits are the
R0.
8. ( F ) The Z flag in the CCR is set to zero when calculation results in
zero.
Since this flag is named "Zero", it is set to 1 when calculation results in
zero.
9. ( T ) The N flag in the CCR is set to zero when the calculation results are
positive.
Since this flag is named "Negative", it is set to 1 when the calculation
results are negative. Zero when positive.
10. ( F )The C flag in the CCR is set to zero when calculation results in a
carry.
Since this flag is named "Carry", it is set to 1 when calculation results
in a carry. Otherwise, zero.
11. ( T )One address of the memory is 8 bits.
Except for special microcomputers such as 4-bit types, 8 bits (1 byte) of
the memory are used per address.
12. ( T )8-bit data can be stored in both even- and odd-numbered
addresses.
Since 8-bit data exactly occupies one address of the memory, it can be
stored in either an even- or odd-numbered address.
13. ( T )16-bit data must be stored in an even-numbered address.
Since the H8/3048 reads and writes 16 bits of data at a time, the upper
8 bits must be stored in an even-numbered address and the lower 8 bits in the
next address. If 16-bit data is stored in an odd-numbered address and the next
even-numbered address, reading/writing will fail.
4.2 Instruction Configuration
This section describes some basic instructions used in assembly

language. And the subsequent sections explain how to develop a program using
them.
MOV instruction
The MOV (MOVe data) instruction is used for data transfer. Although
"transfer" may sound like moving the original data, the function of this
instruction is similar to copying and the original data remains.
It is available from the memory to a general-purpose register, from a general-
purpose register to the memory, between general-purpose registers and from
data to a general-purpose register. This instruction is most frequently used in a
program.
Samples
MOV.B R0L,R1L Transfers 8-bit data from the R0L to the R1L.
MOV.B @H'1000,R0L Transfers the 8 bits in the H'1000 address to the R0L.
MOV.B R1L,@H'2000 Transfers the R1L to the 8 bits in the H'2000 address.
MOV.B #1,R0L Inputs (transfers) data "1" in the R0L.
ADD instruction
The ADD (ADD binary) instruction is used for addition. The results are
stored in the general-purpose register written on the right.
Samples
ADD.B R0L,R1L Adds the R1L and R0L and stores the results in the R1L.
ADD.B #H'12,R0L Adds the R0L and H'12 (18 in decimal notation) and stores
the results in the R0L.
SUB instruction
The SUB instruction (SUBtract binary) is used for subtraction. It
subtracts the contents of the general-purpose register written on the left from
those on the right and stores the results in the register written on the right.
Sample
SUB.B R0L,R1L Subtracts the R0L from the R1L and stores the results in
the R1L.
CMP instruction
The CMP (CoMPare) instruction is used for comparison. It performs
subtraction not to obtain the results but simply for comparison. What matters
most is not what the answer is but how N, Z, V and C in the CCR change after
subtraction. In other words, the CMP instruction simply performs subtraction
and changes N, Z, V and C in the CCR.
A CMP instruction must be followed by a conditional branch
instruction. This is because comparison is meaningless without conditional test.
Samples
CMP.B R0L,R1L Subtracts the R0L from the R1L, changing the CCR.
Conditional branch instruction
CMP.B #H'12,R0L Subtracts H'12 (18 in decimal notation) from the R0L,
changing the CCR.
Conditional branch instruction
BRA instruction
The BRA (BRanch Always) instruction is called "unconditional branch
instruction". Executing this instruction results in branching to the specified
address. Branching is similar to "jumping". It causes jumping forward or
backward, skipping some instructions.
The destination address is specified by giving it a name ("symbol")
Sample
BRA ABC Unconditionally branches to the symbol ABC.
Instruction
ABC: Instruction
BGT instruction
The BGT (Branch Greater Than) instruction is one type of conditional
branch instruction. It compares data as a "signed binary number" and branches
to the specified instruction if it is greater. Otherwise, it does nothing and the
next instruction is executed.
Sample
CMP.B R0L,R1L Compares the R1L with the R0L.
BGT ABC If the R1L is greater, branches to the symbol ABC.
Instruction Otherwise, the next instruction is executed.
Instruction
ABC: Instruction
BHI instruction
The BHI (Branch HIgh) instruction is another type of conditional
branch instruction. It compares data as an "unsigned binary number" and
branches to the specified instruction if it is greater. Otherwise, it does nothing
and the next instruction is executed.
Sample
CMP.B R0L,R1L Compares the R1L with the R0L.
BHI ABC If the R1L is greater, branches to the symbol ABC.
Instruction Otherwise, the next instruction is executed.
Instruction
ABC: Instruction
4.3 Adder Program
4.3.1 How to Develop a Source Program
This section describes how to develop a source program to add 8-bit

data with assembly language.
It is assumed that 8-bit unsigned binary numbers are stored in the
H'2000 and H'2001 addresses of the memory. Here, you will create a program
to add these two data blocks and write the results in the H'2002 address. Up to
8 bits of results are obtained even if addition results in a carry, generating 9
bits.
Since addition is performed, the following instruction is used:
ADD.B R0L,R1L
Any 8-bit register can be used as general-purpose registers other than

the R0L or R1L.
To perform addition using this instruction, you must input data to be added in
the R0L and R1L beforehand. To input data from the H'2000 address of the
memory to the R0L general-purpose register, use the following instruction:
MOV.B @H'2000,R0L
To input data from the H'2001 address to the R1L general-purpose register, use
the following instruction:
MOV.B @H'2001,R1L
H'2000 represents an address in hexadecimal notation. Memory addresses are
generally expressed in this notation. "@" is a mandatory prefix to indicate a
memory address.
The above instructions should be arranged as follows for addition:
MOV.B @H'2000,R0L
MOV.B @H'2001,R1L
ADD.B R0L,R1L
This, however, simply stores the addition results in the R1L and they
are not written in the H'2002 address of the memory.
MOV.B R1L, @H'2002
Use the above instruction to write the addition results in the H'2002
address of the memory.
MOV.B @H'2000,R1L
MOV.B @H'2001,R1L
ADD.B R0L,R1L
MOV.B R1L,@H'2002
Consequently, addition is completed with the above four instructions.

Simply arranging these four instructions, however, will not make a complete
program.
After reading one instruction, the CPU automatically stores the address
of the next instruction in the PC and reads the next instruction after execution
is completed. Since the CPU does not understand whether the next address has
an instruction or not, it assumes that there must be an instruction in the next
address and executes it even after executing the above four instructions. This
results in a runaway since the CPU executes non-existing instructions. To
prevent this, use the BRA instruction as follows:
MOV.B @H'2000,R1L
MOV.B @H'2001,R1L
ADD.B R0L,R1L
MOV.B R1L,@H'2002
ABC: BRA ABC
The above instruction leads to unlimited execution of the BRA

instruction. This prevents the program from proceeding and running away.
The program, however, is still incomplete.
This program does not indicate at which address of the memory the
program itself should be located. It is indicated using an assembler control
instruction. The assembler control instruction is not executed by the CPU but
used to instruct an assembler, which is machine language conversion software.
.SECTION PROG,CODE,LOCATE=H'1000
Use the control instruction shown above. Every assembler control

instruction is prefixed with "." (period). With it, you can easily distinguish
between assembler control instructions and those executed by the CPU
(execution instructions).
.SECTION indicates the section control instruction, PROG represents
the section name (section can be named originally based on certain rules),
CODE refers to the instruction code, and LOCATE=H'1000 specifies that
instructions should be located starting from the H'1000 address of the memory.
The .CPU control instruction to specify the CPU type is also required
since the assembler for the H8/300H is compatible with several CPU types. In
addition, the .END control instruction must be written on the last line.
Finally, a complete program is written as shown in List 4.1.
List 4.1: Simplest Program
This source program is converted into machine instructions by the
assembler as follows:
Address Machine instruction Instruction
.CPU 300HA
.SECTION PROG,CODE,LOCATE=H'1000
H'001000 6A082000 MOV.B @H'2000,R0L
H'001004 6A092001 MOV.B @H'2001,R1L
H'001008 0889 ADD.B R0L,R1L
H'00100A 6A892002 MOV.B R1L,@H'2002
H'00100E 40FE ABC: BRA ABC
.END
The machine instruction is expressed in hexadecimal notation. Since

one address of the memory is 8 bits, it is expressed with a 2-digit, hexadecimal
number. Since the machine instruction "MOV.B @H'2000,R0L" is eight digits,
four addresses of the memory are used to store it (called "4-byte instruction").
In the case of the H8/300H, the shortest instruction is 2 bytes and the longest is
10 bytes.
The first MOV instruction is stored in the four addresses starting from
H'1000 (H'001000) and the next MOV instruction in the four addresses from
H'1004. The ADD instruction is stored from H'1008, the next MOV instruction
from H'100A and the last BRA instruction from H'100E. Since .CPU,
.SECTION and .END are control instructions, they do not correspond to
machine instructions.
Let's consider how the contents of general-purpose registers and the

memory change when a program is executed. It is assumed that H'4C
(B'01001100) is stored in the H'2000 address and H'40 (B'01000000) in the
H'2001 address. Also, the contents of the R0L general-purpose register is
assumed to be H'00 and those of the R1L to be H'00.
[Simulation]
4.3.2 Rules on Source Programs
There are some rules when developing source programs in assembly

language. If they are not followed, an error will occur on assembly. This
section describes the rules relating to source programs.
Configuration of an instruction
An instruction is configured as follows:
Sample instruction ADD.B R0L,R1L
ADD is the operation portion of the instruction representing "ADDition".

.B is the size specification portion indicating that the instruction's operation is in 8 bit
units.
(.W represents 16 bits and L represents 32 bits.)
The R0L and R1L are collectively called "operand", which is an operation target.
The R0L (on the left) is specifically called the source operand.
And the R1L (on the right) is specifically called the destination operand.
The results and answers to calculations are stored in the destination operand.
Note that some instructions have only one operand (destination operand) or
none at all.
Sample instruction with one operand INC.B R0L

Sample instruction with no operand RTS
How to write one line (without a symbol)

Rules: One or more spaces or tabs must be placed at the beginning.
Instructions and operands must be separated by one or more spaces or tabs.
An instruction may be written in both upper and lower cases.
A line must end with a return.
Samples:
MOV.B R0L,R1L Good sample
mov.b r0l,r1l Good sample
Mov.b @h'1000,R1h Good sample
MOV.B R0L,R1L Bad sample (no space or tab at the beginning)
MOV.BR0L,R1L Bad sample (instruction and operand are not
separated by one or more spaces or tabs)
How to write one line (with a symbol)

Rules: Write a symbol first. Suffix the symbol with ":" (colon).
The rest are the same for a line without a symbol.
Rules on symbols: Available characters are A to Z, a to z, 0 to 9, _ and $

Upper and lower cases are handled as different characters
The first character must not be a numeric value
The same name as a CPU internal register must not be used
Samples:
LOOP: MOV.B R0L,R1L Good sample
R1: MOV.B R0L,R1L Bad sample (the same name as an internal
register is used as a symbol)
Samples available as symbols:

Loop Upper and lower cases may be mixed
End_of_Loop "_" is available as a character
DATA1 A numeric value can be used except at the beginning
Samples not available as symbols:

1second Starts with a numeric value
Second/100 "/" is used
Total.Data "." is used
CCR The same name as an internal register
Lines with symbols only

Only symbols may be written on lines. In this case, they are treated like
those written for the following instruction. So, the two samples below represent
exactly the same program:
Samples:
LOOP: MOV.B R0L,R1L Sample with symbol and instruction
written on the same line
LOOP: Sample with symbol and instruction
MOV.B R0L,R1L written on different lines
4.3.3 Inserting Comments
Comments are inserted to make programs readily understood. They serve as

memos and have no influence on program operation. Comments can be
inserted in two ways. One is to place ";" (semicolon) at the beginning of a line,
which causes the entire line to be treated as a comment. All characters such as
alphabets, numeric values and special symbols can be used.
Sample:
;********************************
;* H8/300H Sample program *
;* 2002.9.1 *
;********************************
Another is to insert a comment by suffixing an instruction with ";".This

way, you can add a comment to each instruction.
Program operation is easy to understand when each instruction has a comment.
In List 4.2, comments have been added to the adder program described earlier.
List 4.2: Program with Comments
4.3.4 How to Use .EQU Control Instruction
If a memory address is written in hexadecimal notation in a program, it

is difficult to determine what kind of data is included. So, it is helpful if an
address including data can be expressed by a symbol, rather than in
hexadecimal notation. The .EQU control instruction is the simplest way to
express an address with a symbol.
DATA1: .EQU H'2000
DATA2: .EQU H'2001
ANSWER: .EQU H'2002
The above instructions make DATA1 equal to H'2000.For example, in

the following instruction:
MOV.B @DATA1,R0L
DATA1 is converted into H'2000 by the assembler and it becomes

equal to:
MOV.B @H'2000,R0L
This method is useful when numeric values and addresses are fixed and
will not be changed. List 4.3 shows a program rewritten with this method.
List 4.3: Program Using .EQU
4.3.5 How to Use .RES Control Instruction
The .RES control instruction is used to reserve an area for writing in the
RAM.A RAM address is generally specified not by the .EQU control
instruction but by a combination of .RES and .SECTION control instructions.
This is because the .RES control instruction has the following benefits:
The beginning address can be freely changed using .SECTION
Data areas can be easily inserted or deleted
The .RES control instruction is used as follows:

Samples:
.SECTION WORK,DATA,LOCATE=H'2000
AB: .RES.L 1 ; Reserves one 32-bit area using the symbol AB.
CD: .RES.B 1 ; Reserves one 8-bit area using the symbol CD.
.RES.B 1 ; Simply reserves one 8-bit area. This is used to correct the
16- or 32-bit area to be reserved next to an even-numbered address.
EF: .RES.W 2 ; Reserves two 16-bit areas using the symbol EF.
XYZ: .RES.B 6 ; Reserves six 8-bit areas using the symbol XYZ.
A symbol attached to a reserved area represents the address.

In the example below, since the WORK section is located at the H'2000
address, DATA1, DATA2 and ANSWER represent the H'2000, H'2004 and
H'2006 addresses respectively.
DATA1: .RES.L 1
DATA2: .RES.W 1
ANSWER: .RES.B 1
If the RAM starts from the H'2000 address as with the program
described earlier, write as follows to reserve an area for writing there:
DATA1: .RES.B 1
DATA2: .RES.B 1
ANSWER: .RES.B 1
In the above, DATA1, DATA2 and ANSWER represent the H'2000,

H'2001 and H'2002 addresses respectively.
List 4.4 shows a program rewritten using .RES control instructions.

You can see that the ROM starts from the H'1000 address, in which a
program is stored, and the RAM starts from the H'2000 address, which is used
as a work area.
List 4.4: Program Using .RES
4.3.6 How to Use .DATA Control Instruction
The programs described so far require that values to be added be

written at the DATA1 and DATA2 addresses by some means before they are
executed. This is because DATA1 and DATA2 are stored in the RAM. Since
the contents of the RAM are cleared when it is turned off, it is unpredictable
what are stored there after it is turned on again. In other words, you cannot
determine what must be included in the RAM data area. In the RAM, you can
only reserve an area for writing data temporarily.
On the contrary, the .DATA control instruction is used to set a certain

value in the ROM. Although the use is similar to .RES, it differs in that the
control instruction is followed by "the value to be set in an area", not by "the
count of areas".
Samples:
AB: .DATA.B 10 ; Reserves an 8-bit area including a value "10" using the
symbol AB.
CD: .DATA.B H'A6 ; Reserves an 8-bit area including a value "H'A6" using the
symbol CD.
EF: .DATA.W H'12AB; Reserves a 16-bit area including a value "H'12AB" using
the symbol EF.
XYZ: .DATA.L 40000 ; Reserves a 32-bit area including a value "40000" using
the symbol XYZ.
In the case of the .DATA control instruction, a symbol attached to a

reserved area also represents the address.
DATA1: .DATA.L 10000
DATA2: .DATA.W 1000
ANSWER: .DATA.B 10
In the above example, since the WORK section is located at the H'1100
address, DATA1, DATA2 and ANSWER represent the H'1100, H'1104 and
H'1106 addresses respectively.
If the ROM is also located at the H'1100 address, and if "10" and "100"
to be added should be provided separately, write as follows to prepare a
separate section for storing the addition results in:
.SECTION ROM_DATA,DATA,LOCATE=H'1100
DATA1: .DATA.B 10
DATA2: .DATA.B 100
.SECTION RAM_DATA,DATA,LOCATE=H'2000
ANSWER: .RES.B 1
The above makes DATA1 represent the H'1100 address including "10"
("H'0A" in hexadecimal notation), DATA2 represent the H'1101 address
including "100" ("H'64" in hexadecimal notation) and ANSWER represent the
H'2000 address.
List 4.5 shows a program rewritten using .DATA control instructions.

You can see that the program starts from the H'1000 address, "10" and "100"
are stored in the H'1100 and H'1101 addresses respectively as data in the ROM,
and the H'2000 address is used as a work area in the RAM.
List 4.5: Program Using .DATA
4.4 Collating Sequence Test Program
This section describes a program to test the collating sequence. Let's

assume that two 8-bit data blocks (both unsigned) are stored in the RAM and
you create a program to sort them in descending order. The program should
also store larger data in the DATA1 (H'2000) address and smaller in the
DATA2 (H'2001).
As instructions to test conditions, the BHI (Branch HIgh) and BGT
(Branch Greater Than) instructions have already been described. The BHI tests
the collating sequence assuming data to be unsigned and the BGT assuming
data to be signed. In combination with the CMP instruction, they are used as
follows:
CMP.B R1L,R0L ; Compares the contents of the R1L and R0L
BHI ABC ; Branches to ABC if the contents of the R1L are greater
Instruction ; Otherwise, the next instruction is executed
Instruction
ABC: Instruction
The BHI is an instruction to perform branching if data is greater. "If

data is greater" means "if the data on the right is greater than that on the left
based on comparison" by the CMP instruction. Attach a symbol to the
instruction you want to branch. If the condition is satisfied, branching forward
or backward occurs, skipping some instructions. Otherwise, the next instruction
is executed.
The BHI instruction performs branching when both Z and C flags in the
CCR are 0. The CMP instruction subtracts the R1L from the R0L. If Z is 0 as a
result of subtraction, two data blocks are not equal. If C is 0, no borrow has
occurred. These two conditions are satisfied simultaneously when:
R0L > R1L
The BHI instruction performs branching when the data on the right
(R0L) is greater than that on the left (R1L) based on comparison by the CMP
instruction.
The flowchart of this program is shown in Figure 4.3.
List 4.6 shows the source program.
Figure 4.3: Flowchart to Test Collating Sequence
List 4.6: Program to Test Collating Sequence
1. After an ADD instruction is executed, each flag in the CCR (N, Z, V and
C) changes to reflect the results.
Answer how N, Z, V and C change after the following addition assuming
that R0L = H'80 and R1L = H'80 before the instruction is executed.
And what are the contents of the R0L? Use hexadecimal notation for them
and 0 or 1 for N, Z, V and C.
ADD.B R1L,R0L R0L = , N = , Z = , V = , C =
Answer
R0L = H'00, N = 0, Z = 1, V = 1, C = 1
The results are R0L = H'00 (Z = 1)
A carry occurs (C = 1)
The most significant bit of the R0L is 0 and positive (N = 0)
Since Negative + Negative = Positive, an overflow occurs (V = 1)
Answer how N, Z, V and C change after the following addition assuming

ADD.B R1L,R0L R0L = , N = , Z = , V = , C =
Answer
R0L = H'81, N = 1, Z = 0, V = 1, C = 0
The results are R0L = H'81, not zero (Z = 0)
No carry occurs (C = 0)
The most significant bit of the R0L is 1 and negative (N = 1)
Since Positive + Positive = Negative, an overflow occurs (V = 1)
2. After a SUB instruction is executed, each flag in the CCR (N, Z, V and
C) changes to reflect the results.
Answer how N, Z, V and C change after the following subtraction
assuming that R0L = H'70 and R1L = H'80 before the instruction is
executed.
SUB.B R1L,R0L R0L = , N = , Z = , V = , C =
Answer
R0L = H'F0, N = 1, Z = 0, V = 1, C = 1
The results are R0L = H'F0 and not zero (Z = 0)
A carry occurs (C = 1)
The most significant bit of the R0L is negative (N = 1)
Since Negative - Positive = Negative, an overflow occurs (V = 1)
Answer how N, Z, V and C change after the following subtraction assuming

SUB.B R1L,R0L R0L = , N = , Z = , V = , C =
Answer
R0L = H'5F, N = 0, Z = 0, V = 0, C = 0
The results are R0L = H'5F, not zero (Z = 0)
No carry occurs (C = 0)
The most significant bit of the R0L is 0 and positive (N = 0)
Since Positive - Positive = Positive, no overflow occurs (V = 0)
Chapter 5
H8/300H Instructions and Addressing Mode
Although programs were developed using simple instructions in

Chapter 4, many other instructions are available for the H8/300H. In this
chapter, all instructions for the H8/300H are listed in easy-to-understand tables.
Some instructions frequently appear in programs while others are hardly used.
At this stage, how to use each instruction is not described in detail. It does not
matter if you do not understand some points. Detailed explanations are given in
the next chapter, where sample programs are introduced.
Since developing programs require frequent reference to the
"instruction table", you should learn how to read the table at this stage.
5.1 Instructions
Instruction types
This section lists instructions provided in the H8/300H CPU. Not only
instructions but all descriptions in this chapter are common to the entire
H8/300H series including the H8/3048.
Data transfer instructions Arithmetic instructions Logical instructions

Conditional branch
Unconditional branch instructions Bit handling instructions
instructions
Shift/Rotate instructions Block transfer instructions System control instructions
- Data transfer instructions

Instruction Meaning Description Sample program
MOV MOVe data Data transfer
PUSH PUSH data Stores data in the stack -
POP POP data Restores data from the stack -
- Arithmetic instructions
ADD ADD binary Binary addition
SUB SUBtract binary Binary subtraction -
ADDX ADD with eXtend carry Binary addition with a carry -
SUBX SUBtract with eXtend carry Binary subtraction with a carry -
INC INCrement Increment
DEC DECrement Decrement
ADDS ADD with Sign extension Binary address data addition
SUBS SUBtract with Sign extension Binary address data subtraction -
DAA Decimal Adjust Add Decimal adjustment (addition) -
DAS Decimal Adjust Subtract Decimal adjustment (subtraction) -
MULXU MULtiply eXtend as Unsigned Unsigned multiplication
MULXS MULtiply eXtend as Signed Signed multiplication
DIVXU DIVide eXtend as Unsigned Unsigned division
DIVXS DIVide eXtend as Signed Signed division
CMP CoMPare Comparison
NEG NEGate Sign change -
EXTS EXTend as Signed Signed extension -
EXTU EXTend as Unsigned Unsigned extension
- Logical instructions
AND AND logical Logical product
OR inclusive OR logical Logical sum
XOR eXclusive OR logical Exclusive logical sum
NOT NOT (logical complement) Logical negation -
- Conditional branch instructions

Instruction Meaning Description Sample
program
BHI Branch HIgh Branches if larger (unsigned) -
BLS Branch Low or Same Branches if smaller or the same (unsigned) -
BCC Branch Carry Clear
Branches if no carry occurs (unsigned)
(BHS) Branch High or Same
BCS Branch Carry Set
Branches if a carry occurs (unsigned) -
(BLO) Branch LOw
BNE Branch Not Equal Branches if not equal
BEQ Branch EQual Branches if equal -
BVC Branch oVerflow Clear Branches if no overflow occurs -
BVS Branch oVerflow Set Branches if an overflow occurs -
BPL Branch PLus Branches if positive -
BMI Branch MInus Branches if negative -
BGE Branch Greater or Equal Branches if larger or the same (signed) -
BLT Branch Less Than Branches if smaller (signed) -
BGT Branch Greater Than Branches if larger (signed) -
BLE Branch Less or Equal Branches if smaller or the same (signed) -
- Unconditional branch instructions

JMP JuMP Unconditional jump -
JSR Jump to SubRoutine Jumps to a subroutine
BRA BRanch Always Unconditional branch
BSR Branch to SubRoutine Branches to a subroutine -
RTS ReTurn from Subroutine Returns from a
subroutine
- Bit handling instructions

BSET Bit SET Sets one bit
BCLR Bit CLeaR Clears one bit
BNOT Bit NOT Inverts one bit
BTST Bit TeST 1-bit test
BAND Bit AND 1-bit logical product -
BIAND Bit Invert AND 1-bit inversion and logical product -
BOR Bit inclusive OR 1-bit logical sum -
BIOR Bit Invert OR 1-bit inversion and logical sum -
BXOR Bit eXclusive OR Exclusive logical sum with one bit -
BIXOR Bit Invert eXclusive OR 1-bit inversion and exclusive logical sum -
BLD Bit LoaD Loads one bit (to a carry) -
BILD Bit Invert LoaD Inverts and loads one bit (to a carry) -
BST Bit STore Stores one bit (from a carry) -
BIST Bit Invert STore Inverts and stores one bit (from a carry) -
- Shift/Rotate instructions
SHAL SHift Arithmetic Left Arithmetic left shift -
SHAR SHift Arithmetic Right Arithmetic right shift -
SHLL SHift Logical Left Logical left shift -
SHLR SHift Logical Right Logical right shift -
ROTL ROTate Left Left rotation -
ROTR ROTate Right Right rotation -
ROTXL ROTate with eXtend carry Left Left rotation with a carry -
ROTXR ROTate with eXtend carry Right Right rotation with a carry -
- Block transfer instructions

EEPMOV MOVe data to EEPROM Data block transfer -
* Serves as a data block transfer instruction since no EEPROM is provided
with the H8/300H series.
- System control instructions

TRAPA TRAP Always Generates a trap -
RTE ReTurn from Exception Returns from an exception -
handling routine
SLEEP SLEEP Sets the CPU in sleep state -
LDC LoaD to Control register Loads data to the CCR -
STC STore from Control register Stores data from the CCR -
ANDC AND Control register Logical product with the CCR -
ORC inclusive OR Control register Logical sum with the CCR -
XORC eXclusive OR Control register Exclusive logical sum with the -
CCR
NOP No OPeration No operation -
5.2 Addressing Modes
As described in Chapter 4, most instructions consist of mnemonics and

operands (targets for calculation or operation). Addressing modes represent
how to specify targets for calculation or operation, in other words, how to write
operands. There are nine addressing modes in all, each of which is selected
according to whether the target is a general-purpose register or memory, and
other factors.
Some addressing modes are available only for specific instructions.
Table 5.1: Addressing Mode Types

Sample
Addressing mode Symbol Description
program
Rn, En, ERn Addressing for handling the contents of
Register direct
RnL, RnH a general-purpose register.
Addressing for handling numeric
Immediate #xx
values directly.
Addressing for handling the contents of
the memory.
Absolute address @aa
A memory address is directly written in
an instruction.
the memory.
Register indirect @ERn A memory address is represented by
the contents of a general-purpose
register.
the memory.
Register indirect with A memory address is represented by
@(disp,ERn)
displacement the contents of a general-purpose
register with displacement (distance)
added.
Post-increment the memory.
@ERn+
register indirect Although the contents of a general-
purpose register is used as a memory
address, the contents are incremented
after instruction execution.
the memory.
Predecrement Although the contents of a general-
@-ERn
register indirect purpose register is used as a memory
address, the contents are decremented
before instruction execution.
Addressing for branching by storing the
Memory indirect @@aa destination address in the memory and —
specifying it.
Program counter Addressing for specifying a branch
Symbol
relative destination address.
* n: General register number xx: Numeric value
aa: Address disp: Displacement
5.3 Assembler Control Instructions
The assembler control instructions are used to specify operation of the

assembler when it converts a source program into an object program.
Specifically, they instruct the assembler where a program starts and ends, how
to reserve data or areas, and how to define symbols (no machine code is
generated except for some data generation instructions).
More than 30 assembler control instructions are available for the H8/300H
series assembler. Among them, basic instructions are described in this section.
For the assembler control instructions used in the sample programs in

Chapter 6, check the specifications in the table below:
Table 5.2: Assembler Control Instruction List

Control
Type Functions
instruction
Aligns an address to an even-numbered address or a 256-byte
boundary.
Put a boundary alignment number (2n) in the operand.
Samples
.ALIGN 2 ------------- (1)
.ALIGN
.DATA.W 1000
1.Section/ .ALIGN 256 ------------- (2)
location .DATA.W 2000
(1) Aligns an address to an even-numbered one.
(2) Aligns an address to a 256-byte boundary.
Specifies start and resume of a section and declares the attribute.
You can specify the name, attribute and start address of a section in
.SECTION
the operand.
Section attribute
CODE --- Code section
DATA --- Data section
Samples
.SECTION SCT1,CODE,LOCATE=H'1000 --- (1)
MOV.W R0,R1
MOV.W R2,R3
RTS
.SECTION SCT2,DATA,LOCATE=H'2000 --- (2)
ABC: .RES.W 1
(1) SCT1 specifies a code section and H'1000 as the start
address.
(2) SCT2 specifies a data section and H'2000 as the start
address.
Sets an address.
Samples
.SECTION SCT1,DATA,LOCATE=H'0000
DATA1: .DATA.W H'1234
.ORG H'0020 ------------- (1)
DATA2: .DATA.W H'5678
.ORG
.ORG H'0040 ------------- (2)
DATA3: .DATA.W H'ABCD
(1) Sets an address to H'0020.
DATA2 is allocated to the H'0020 address.
(2) Sets an address to H'0040.
DATA3 is allocated to the H'0040 address.
2.Setting of
.EQU Sets a value for a symbol.
symbol value
Reserves integer data based on the specified size.
Following ".", B (Byte), W (Word) or L (Long word) can be
specified as the size of the data to be set. Unless specified, "W" is
.DATA assumed.
Put integer data to be set in the operand. You can specify multiple
3.Setting of
integer data blocks using "," as a separator.
data
The symbol represents the start address of the reserved data.
Reserves string data.
Specify the string to be reserved in the operand. Characters must be
.SDATA
enclosed with "". You can specify up to 255 characters.
The symbol represents the start address of the reserved string data.
Reserves an integer data area based on the specified size.
Following ".", B (Byte), W (Word) or L (Long word) can be
4.Reservation
specified as the size of the area to be reserved. Unless specified,
of .RES
"W" is assumed.
data area
Put the count of areas to be reserved in the operand.
The symbol represents the start address of the reserved area.
5.Specification Specifies the target CPU for the source program to be assembled.
.CPU
of CPU The H8/300H CPU types are as follows:
300HA:20 ------ Operates in a 1Mbyte memory space
300HA:24 ------ Operates in a 16Mbyte memory space
(":24" may be omitted)
Indicates the end of a source program.
Put this instruction in the end of a source program. If part of a
6. Other .END
source program continues following this instruction, it is ignored
and not assembled.
5.4 How to Read the Instruction Table
This section describes how to read the instruction table detailing each
instruction.
The instructions described in 5.1 have specific data size and addressing
mode they can execute, and how each flag in the CCR changes after execution
differs. These detailed instruction specifications are described in the instruction
table.
The following shows how to read it.
Execution state count

"Execution state count" is synonymous with "execution clock count".
For example, if the system clock executes the following at 10MHz (1 clock =
0.1 microsecond):
MOV.B #xx,Rd (execution state count = 2)
Execution takes 0.2 microsecond.
Example for referring to the execution state count

Next, when execution states are referred to is described using an example.
Example: There are three ways to clear a general-purpose register to zero:
(1) MOV.B #0,R0L Transfers zero
(2) SUB.B R0L,R0L Subtracts itself
(3) XOR.B R0L,R0L Executes the exclusive logical sum with itself
If the data size is byte as shown above, the execution state count is 2 for
all of the three. This means that there is no difference in speed. If the data size
is long word (32 bit), however, the counts change as follows:
Execution state count
(1) MOV.L #0,ER0 6
(2) SUB.L ER0,ER0 2
(3) XOR.L ER0,ER0 4
From the above, you can see that SUB.L ER0,ER0 has the shortest
execution time.
When the same process can be achieved with several methods as shown
above, you should check their execution state counts (and instruction lengths)
to select the one with the smallest count.
1. Point out the errors in the following instructions. (Some instructions,

however, may not include errors.)
(1) MOV.B #H'FF,@RESULT
(2) MOV.B #H'FF,@ER0+
(3) MOV.B @-ER0,R1L
(4) CMP.B R0L,#0
(5) MOV.B R0,R1
(6) MOV.B #200,R0L
(7) MOV.B #500,R0L
(8) ADD.B @DATA,R0L
Answers
(1) The MOV instruction cannot transfer immediate data directly to the
memory.
(2) Post-increment register indirect can only be specified for the source
operand.
(3) Predecrement register indirect can only be specified for the destination
operand.
(4) Immediate data can only be specified for the source operand.
(5) The specified data size is wrong. Since the R0 and R1 are 16-bit general-
purpose registers, the data size must be "W".
(6) Correct.
(7) A decimal number of "500" cannot be handled when the size is byte (8
bits).
(8) The ADD instruction cannot directly calculate data in the memory.
2. After the following instruction is executed, by how many will the value
of the ER0 be decremented from that before execution.
MOV.B R1H,@-ER0
Answer: 1
One is subtracted when the size of the data to be transferred is byte.
3. All of the following instructions clear the ER0 to zero. Which has the
shortest length?
(1) MOV.L #0,ER0
(2) SUB.L ER0,ER0
(3) XOR.L ER0,ER0
Answer: (2)
(1) is 6-byte long. (2) is 2-byte long. (3) is 4-byte long.
So, (2) SUB.L ER0,ER0 is the shortest.
4. List advantage and disadvantage of single-chip microcomputers, one for

each.
Advantage (Small, inexpensive)
Disadvantage (Limited internal functions)
(Small memory capacity,
unsuitable for large-scale systems)
Since single-chip microcomputers have all functions on one chip, they
are small and less expensive than buying components separately. Circuit
integration, however, is limited and thus cannot accommodate relatively large
memory.
Chapter 6
Sample Programming in an Assembly Language
This chapter introduces some sample programs so that you can actually
develop programs using various instructions.
Programs can be developed in several ways and there is no single right
answer. During development, you will have many questions such as "Can the
same be achieved by another method?" and "What will happen by doing this?".
Rather than just worrying, go on and develop the program in mind and execute
it using the simulator. If the results are the same as those obtained by the
sample program, your program is also the right one. Developing a different
program by modifying a sample program is another effective way of learning.
This chapter will help you understand how various instructions and
addressing modes described in Chapter 5 work for program development.
6.1 Conditional Test Programs
This section introduces conditional test programs.
To branch a process based on the collating sequence of values, the

CMP (compare) instruction is used in combination with the conditional branch
instruction. You will use different branch instructions depending on whether
the values to be compared are signed or not.
The table below shows how to select branch instructions:
Table 6.1: Conditional Branch Instruction
Next, check the CMP instruction specifications in the instruction table.
The CMP instruction can compare 8-, 16- and 32-bit data. The comparison
targets, however, must be general-purpose registers, or immediate and a
general-purpose register. Before executing the CMP instruction, store data in a
general-purpose register.
The conditional branch instruction can also be used independent of the
CMP instruction. To branch using the conditional branch instruction only, the
status of each flag in the CCR changed by the previous instruction determines
whether to branch or not.
The table below shows the conditions for the conditional branch instruction:
Table 6.2: Conditions for Conditional Branch Instruction
6.2 Programs Containing a Loop
Repetitive (looping) processing in assembly language is achieved using
the conditional branch instruction. This section introduces programs containing
loops.
After each repetitive processing, the value stored in a general-purpose

register is incremented or decremented. This value is generally called "loop
counter". The value of the loop counter is judged by the conditional branch
instruction at the end of each processing to determine whether to repeat it or
not.
It is usually recommended that the loop counter be decremented for
repetitive processing. This is because if the loop counter is incremented as
shown in sample program 1, the CMP instruction is required to judge whether
to repeat the processing or not.
On the other hand, if the counter is decremented, the CMP instruction is
not required since the end of repetition can be determined based on whether the
counter is zero or not. This is because Z in the CCR becomes 1 for this type of
instruction when the loop counter becomes 0 (otherwise, Z is 0).
This enables an instruction "to repeat processing if Z in the CCR is 0".
In this case, you can use the BNE instruction to branch if Z in the CCR is 0.
You can also stop looping by judging that the address of the memory
has reached a specific value.
6.3 Subroutines
If the same collection (function) of instructions is executed several
times in a program, writing the function every time makes the program difficult
to understand. In addition, it makes the program larger since it also increases
the instruction count.
To prevent this, programs should be developed by separating repeated

functions from the main flow.
These separated functions are called "subroutines". (By contrast, the

main program flow is called "main routine".)
Moving execution to a separated function is referred to as "calling a
subroutine (subroutine call)" and subroutine call instructions (BSR and JSR
instructions) are used for this purpose. They are written as follows:
BSR Subroutine name (Called with program counter relative addressing)

JSR @Subroutine name (Called with absolute address addressing)
* Subroutine name: Symbol prefixed to a subroutine
In the called subroutine, instructions are executed in ordinary order and

control is returned to the source after execution is completed.
The RTS instruction is used to return execution to the source. This
means that all subroutines end with the RTS instruction. This instruction is
written as follows:
RTS (The RTS instruction has no operand)
After the RTS instruction is executed, processing resumes from the
instruction next to the one which has called the subroutine.
Let's consider how the RTS instruction returns execution to the source.
If one subroutine is called from different places, execution is returned to
the respective places by the RTS instruction.
Before introducing the principle of subroutine operation, introduction of
the stack is indispensable.
What is the stack?

1. It refers to RAM space which is extended from larger to
smaller addresses as necessary to input information while the
direction is reversed from smaller to larger for outputting
stored information.
2. In a RAM prepared as the stack, up to which addresses have
been used and which will be used next are automatically managed by the stack pointer
(SP). Once the stack area address has been set in the SP, programmers need not be
concerned about where the current SP is.
All programmers need to do before using the stack for calling a subroutine or other purpose is
to set a value for "the last address of the area to be used as the stack + 1 (even number)" in the
SP (the ER7 in case of the H8/300H series).
In the stack, you can store even-number-sized information only. Although any RAM is
available for the stack area, the internal RAM space is generally used.
3. When using the stack area in a program, programmers must take the stack capacity
(how many bytes are required in all) into account. Calculate the capacity used in the
developed program and be sure to secure sufficient free RAM space.
Subroutines are called using the above stack function.
Subroutine call instructions (JSR and BSR instructions)

The CPU always maintains the address of the next instruction in the program counter.
The subroutine call instruction first stores the address of the instruction written next to itself in
the stack (this becomes the address returned from the subroutine). After this operation,
execution moves to the subroutine.
Instruction to return from subroutine (RTS instruction)
The RTS instruction at the end of a subroutine writes the address stored in the stack by the
subroutine call instruction to the PC. This enables the instruction next to the subroutine call
instruction to be executed next to the RTS instruction. In other words, processing is returned to
the source of the subroutine.
1. You want to branch if R0 is less than R1 after the following instruction.
Which branch instruction do you use? It is assumed, however, that
unsigned data are stored in R0 and R1.
CMP.W R0,R1
Answer: BHI
The destination operand plays the main role in comparison using the CMP
instruction.
In this question, R1 is used as the destination operand.
Assuming that R1 is greater than R0, you should use BHI.
2. After the following instruction is executed, is Z in the CCR "0" or "1"?

CMP.W R0,R1
Answer: 1
Since 0 is stored in the ER0 register as a result of subtraction, Z in the CCR is
1.
3. The following program is designed to obtain the minimum value from

10 blocks of byte data at the ROM_DT address using a subroutine and
store it in the RESULT address. Enter appropriate information in
parentheses. It is assumed, however, that signed data are stored in the
ROM_DT address.
Answers are written in red below
BNE LOOP
In the R1L register, "9" is entered as the counter to repeat the loop nine times.
The counter is decremented by 1 per processing, which is repeated until the
counter becomes zero. The BNE (branch if not zero) instruction is used to loop
unless zero.
MOV.B R0L,@RESULT
Since the minimum data is stored in the R0L register after being compared 9
times, it is written to the RESULT address.
MIN: CMP.B R0H,R0L

In the first instruction of a subroutine, specify its name.
MIN is the name of the subroutine and:
JSR @MIN
is used to jump to it.
BLE RETURN
This subroutine compares the contents of the R0H and R0L registers assuming
them to be signed and puts the smaller in the R0L register.
If the contents of R0L are equal to or smaller than as a result of comparison,
processing is returned from the subroutine without any operation. As a
conditional test instruction, use the one assuming data to be signed.
RTS
Instruction to return from a subroutine.
DATA.B 99,0,-5,39,-2,68,-16,5,20
Defines 8-bit data. DATA.B is mainly used to represent data in the ROM.
6.4 Register Indirect with Displacement
Register indirect with displacement addressing (described in Chapter 5)

is used to retrieve specific data from consecutive data in the memory such as
arrays.
6.5 Post-increment Register Indirect/Predecrement Register
Indirect
This section introduces sample programs using post-increment register

indirect and predecrement register indirect (described in Chapter 5).
Post-increment register indirect

Post-increment register indirect is used to refer to consecutive values in
the memory.
To be more specific, it stores the address of the memory to be referred
to in a general-purpose register, refers to the contents and increments the value
(address) stored in the register by the byte count of the handled data.
Predecrement register indirect
Predecrement register indirect is used to store values sequentially in
consecutive areas in the memory.
To be more specific, it stores "the last address of the target memory + 1" in a
general-purpose register, decrements the value in the register by the byte count
of the data to be handled and writes information to the address.
6.6 Multiplication and Division Programs
The H8/300H is provided with multiplication and division instructions.

This section introduces programs using these instructions.
Multiplication instructions
There are two types of multiplication instructions: one for unsigned
values (MULXU instruction) and the other for signed values (MULXS
instruction).
Division instructions
There are also two types of division instructions: one for unsigned
values (DIVXU instruction) and the other for signed values (DIVXS
instruction).
For the division instructions, the results are not guaranteed in the following
cases:
When the quotient exceeds 1 byte for byte-size division (overflow)
When the quotient exceeds 2 bytes for word-size division (overflow)
When divided by zero
6.7 Logical Operation
The H8/300H is provided with an instruction for logical operation per

data bit. This section introduces programs using logical operation.
Logical operation is used to retrieve the statuses of multiple bits in data,

set multiple bits to 0 or 1, or invert the current statuses.
The table below shows the logical operation results of 2 data blocks:
Table 6.3: Logical Operation Table
Based on these results, logical operation is used in the following cases:
6.8 Bit Handling
The H8/300H is provided with a bit handling instruction for handling a

specific 1 bit only. This section introduces a sample program using this
instruction.
Although a specific 1 bit among data can also be handled using the
logical instruction described earlier, its target is general-purpose registers only.
On the contrary, the bit handling instruction can handle not only data stored in
a general-purpose register but also directly handle the contents of the memory
between H'FFFF00 and H'FFFFFF addresses using absolute address
addressing.
Bits in 1-byte data are numbered as follows:
1. Point out the errors in the following instructions. (Some instructions,
however, may not include errors.)
Instruction
(1) DIVXU.B #H'15,R0
(2) MOV.B @(#H'10,R0L),R0H
(3) BSET #1,@H'FFFFF0
(4) BSET #1,@H'200000
(5) BTST #7,R0L
(6) BTST #8,R0L
(7) BTST.W #3,R0
Answers
(1) Only a general-purpose register can be specified for the DIVXU
instruction operand.
(2) Register indirect with displacement can specify 32-bit general-
purpose registers only.
(3) Correct.
(4) Although the bit handling instruction can specify H'FFFF00 to
H'FFFFFF using an absolute address, other addresses must be specified by
register indirect.
(5) Correct.
(6) Available bit numbers are between 0 and 7.
(7) The bit handling instruction can handle byte data only.
2. Answer the following questions.

(1) How can you rewrite only the least significant 2 bits in 1-byte data to 0?
Answer:
Execute AND with #B'11111100
AND operation is used to set specific bits to 0 since it results in 0 if either of
the two is 0.
Use the BCLR instruction to set only one bit to 0.
(2) How can you rewrite only the least significant 2 bits in 1-byte data to 1?
Answer:
Execute OR with #B'00000011
OR operation is used to set specific bits to 1 since it results in 1 if either of the
two is 1.
Use the BSET instruction to set only one bit to 1.
(3) How can you invert only the least significant 2 bits in 1-byte data?
Answer:
Execute XOR with #B'00000011
EOR with 0 results in no change but with 1 in inversion. Utilizing this function,
you can use EOR operation with 1 to invert specific bits. Use the BNOT
instruction to invert one bit only.
(4) How can you check the statuses of the least significant 2 bits in 1-byte
data and ignore the rest?
Answer:
Execute AND with #B'00000011
After setting untargeted bits to 0 using AND operation, you can judge whether
the target bits are zero or not, or compare them with specific bit patterns using
the CMP instruction.
(5) How can you check the status of only the least significant bit in R0L
and ignore the rest?
Answer:
BTST #0,R0L
When the target is one bit only, the BNE or BEQ instruction is used following
the BTST instruction to judge whether it is zero or not.
3. In the following process, what is stored in COUNT?

MOV.B @T_DATA,R4L
MOV.B #0,R0L
MOV.B #7,R0H
LOOP: BTST R0H,R4L
BEQ NOCNT
INC.B R0L
NOCNT: DEC.B R0H
BNE LOOP
MOV.B R0L,@COUNT
Answer
The count of bits set to 1 in 1-byte data at the T_DATA address
The key instruction is:
BTST R0H,R4L
on the fourth line. It tests 1 bit in R4L using R0H as the bit number. It changes
R0H from 7 to 0 and checks whether 8 bits in R4L are 1 or 0 sequentially from
the most to least significant bits. Since R0L is incremented by 1 per bit having
a value of "1", the count of 1s in the T_DATA address is stored in R0L.
Chapter 7
Exception Handling
Exception handling is classified into reset and interrupts and the

interrupt function is indispensable for control using programs. It is almost
always used when a timer is used and is also required for effective data
input/output. To write the program you have made to the ROM for execution,
you also need to understand how reset works. The concepts of reset and
interrupts, however, are difficult to understand for beginners.
Since practical uses are not mentioned in this chapter, you may not get
a clear idea of them. The effects of interrupts are described in chapters relating
to timers and serial interface. Here, you should fully understand the following
key items: interrupt mask bit in the CCR, vector addresses and storage of the
PC and CCR values.
Note:
Some IC signal names have bars over them to indicate negative logic.
In the contents of the CD-ROM, however, no bar can be placed on them since
they are written in HTML format. Still, bars are added to negative logic signals
in figures included as images.
The following are negative logic signals:
7.1 What Is Exception Handling?
The CPU sometimes shows special operation called "exception

handling". Exception handling refers to the operation that moves execution not
to the next instruction but to another program after the current instruction is
completely executed if any exception handling source is generated while the
CPU is executing the main routine. The program to which execution is moved
by exception handling is referred to as an "exception handling routine".
Figure 7.1: Exception Handling Operation Overview
The H8/3048 has 42 types of exception handling sources, which are

classified into one reset and 41 interrupts. Reset is mainly designed to start
execution from a particular program after turning the microcomputer on.
Interrupts are designed to move operation to an exception handling routine
when an interrupt source is generated during program execution and return
operation to the original program after the exception handling routine has been
executed completely.
Figure 7.2: Types of Exception Handling Sources
Although what generates an exception handling source depends on the

type, all types of exception handling routines employ the vector method. This
method is designed to notify the CPU of the start address of an exception
handling routine. The details are described in the following sections.
7.2 Reset
7.2.1 Reset Sources and Operation
Reset is generated for two purposes. One is to start execution from a
particular program after turning the microcomputer on. This program is called
the "main routine". The other is to stop any program being executed by the
CPU and resume processing from the same state when the power is turned on
again. Figure 7.3 shows reset sources:
Figure 7.3: Reset Sources
The CPU shows the operation described in Figure 7.4 after reset is generated.
Figure 7.4: Reset Operation
After reset is generated, the CPU stops any program being executed,
loads the reset vector to the PC and fetches an instruction from this address to
execute it. In other words, reset generation always causes the main routine
stored in the address indicated by the reset vector to be executed. After reset is
generated to start main routine execution, processing cannot be returned to the
original program to continue. Reset generation means that the microcomputer
starts processing from the initial state.
When the microcomputer starts operation, users are required to set the
program to be executed first, namely the start address of the main routine, as
the reset vector in the lower three addresses of the four-address area starting
from address 0. This area is referred to as the "reset vector address".
7.2.2 Power-on Reset
Although you can generate reset any time, there is one time that you
must generate it. That is, when the microcomputer is turned on.
Simply turning it on will not set all registers in the CPU to specific values and
even the value in the PC cannot be determined. This means that the CPU
cannot determine from which address the program should be executed when
the microcomputer is turned on.
Therefore, reset must be generated prior to any other processing after
power-on. This is called "power-on reset".
Figure 7.5: Overview of Reset Pin External Circuit and Voltage Waveform
For reset to be generated properly at power-on, the electrical

characteristics of the H8/3048 specify that the low-level voltage be kept at least
20ms before the high-level voltage applied to the reset pin. This allows the
internal clock oscillating circuit to stabilize after power-on.
On the contrary, to prevent reset generation in the microcomputer, you
must externally apply the high-level voltage to the reset pin beforehand. Note
that reset may be generated by a low-level noise only.
To satisfy these two conditions, it is recommended that a circuit using a
commercially available reset IC be designed around the reset pin.
Precautions on storing the reset vector
For a program to operate properly after power-on reset, the reset vector
must be stored in the reset vector addresses before the microcomputer is turned
on. This means that the reset vector addresses must be in the ROM whose
contents remain even after power-off. You must store the reset vector in this
ROM.
As shown in Figure 7.6, use the DATA.L assembler control instruction
to store the reset vector. In this example, the main routine (symbol MAIN) is
placed starting from the H'001000 address and the value of H'001000 indicated
by the MAIN symbol is stored as the reset vector in the 4-address area between
the H'000000 and H'000003 addresses.
Figure 7.6: Description to Store the Reset Vector
7.3 Interrupts
7.3.1 Interrupt Overview
The H8/3048 has 41 types of interrupts, which are exception handling

routines with a variety of types.
Any microcomputer-applied system must timely respond to processing
requests which may be generated at any time such as signal inputs from many
sensors and outputs to specific equipment. Although it is possible for one
program to sequentially search for and respond to all processing requests, this
results in long search time and slow response speed. To solve this problem, a
mechanism is needed to allow a response program (interrupt handling routine)
to be executed only when a processing request is issued. The CPU is provided
with interrupts for this function.
Interrupts are designed to respond to a processing request with a higher
priority than the current program and move execution to it.
Figure 7.7: Interrupt Operation
Let's take a microcomputer used in a beverage vending machine as an

example. The microcomputer is generally required simply to execute a
program to keep the product temperature at a certain level. Only when coins
are dropped in, should interrupt operation be started to execute programs as
interrupt handling routines to judge how many coins have been dropped in or
which button has been pressed. After execution is completed, the
microcomputer can return to the original temperature control program.
7.3.2 Interrupt Types
Two conditions must be satisfied to allow an interrupt to be generated:

one is that an interrupt request has been generated and the other is that an
interrupt is enabled.
Although the judgement of whether an interrupt request is generated or
not depends on the interrupt type, event occurrence in the microcomputer
hardware is generally regarded to be generation of an interrupt request.
Interrupts are roughly classified into 41 types, which are further divided
into external and internal interrupts based on the sources. For internal
interrupts, requests are generated by the internal peripheral functions, which
are described in the following chapters. In other words, interrupt requests are
generated when something happens on the internal peripheral function
hardware. Since internal interrupts are described in the following chapters,
external interrupts only are explained here.
Operation, however, is the same for both external and internal
interrupts, which you should fully understand here.
Figure 7.8: External Interrupt Request Input Pins
The H8/3048 has seven pins to input external interrupt requests in all
and six of them are named "IRQ0" to "IRQ5". The remaining pin is named
"NMI".
In the case of external interrupts, a request is regarded to be generated
when the low-level voltage is applied to one of these interrupt request input
pins. To prevent an external interrupt request from being generated, apply the
high-level voltage to these pins.
For example, if the low-level voltage is applied to the IRQ3 input pin,
an external interrupt request of the "IRQ3" type is regarded to be generated. If
the interrupt is enabled at this time, the interrupt is generated to move
execution to the IRQ3 interrupt handling routine.
Accordingly, you can execute a program to handle requests only when
required by creating an external circuit to apply the low-level voltage to a
corresponding interrupt request input pin when a sensor has prepared data to be
read by the microcomputer.
Disabling/Enabling Interrupts
As indicated by the above description saying "If the interrupt is enabled
at this time", interrupt requests, irrespective of whether they are external or
internal, are not necessarily accepted by the microcomputer. The following
describes the interrupt mask bit in the CCR, which controls whether to accept
interrupt requests or not.
Figure 7.9: Interrupt Mask Bit
Whether to enable or disable interrupts is controlled by the most
significant bit in the CCR (I bit), or the interrupt mask bit. This I bit can be set
to 1 or 0 using an LDC instruction or others.
When the I bit is 1, interrupts are masked, or disabled, and interrupt operation
is not performed even if an interrupt request is generated. When the I bit is 0,
interrupts are enabled and interrupt operation is performed if an interrupt
request is generated.
This I bit collectively disables or enables all external and internal
interrupts excluding the NMI. The NMI is an acronym for non-maskable
interrupt, an interrupt which cannot be disabled even if the I bit is set to 1.
In addition, interrupts other than the NMI can be individually enabled
or disabled by the respective bits. They are described in the next section.
7.3.3 IRQs
(1) Electrical characteristics of IRQs
Since external interrupts generate requests by externally inputting

electrical signals to the interrupt request input pins, they must satisfy certain
characteristics. This section describes the electrical characteristics of external
interrupts specified for the H8/3048.
In the case of the H8/3048, all operations are based on digital circuits
synchronous with the system clock named "φ (phi)". Whether the high or low
voltage is applied to the seven interrupt request input pins is judged based on
the timing of the trailing edge of the system clock φ (phi). Accordingly, the
setup time and hold time, which are inevitably specified for all clock
synchronous digital IC input pins, are also specified for the H8/3048.
Figure 7.10: Electrical Characteristics of External Interrupts
(2) Internal I/O registers of IRQs
Next, you will learn about internal I/O registers of IRQs. Internal I/O
registers collectively refer to registers for using various internal peripheral
functions. Each register is placed at a specific address in the memory and given
a specific name.
This lesson contains many descriptions of various internal I/O registers.
In the microcomputer, external interrupt operation is controlled by the internal
peripheral function named "interrupt controller". Two internal I/O registers for
using this interrupt controller are described below. First, the IRQ enable
register (IER) is described, together with how to interpret the explanatory
diagram.
Figure 7.12: IRQ Enable Register (IER)
Using bits 5 to 0 of the IRQ enable register (IER), you can enable or
disable six IRQ interrupts individually. To enable the IRQ0 interrupt, for
example, you should set the least significant IRQ0 enable bit (IRQ0E) to 1. As
a matter of course, you should set the I bit in the CCR to 0 as well.
Since all bits of this register are set to 0 by default, all IRQ interrupts
are disabled without modification after resetting. To allow a specific IRQ
interrupt, set the relevant bit of the IER to 1 using an instruction.
Figure 7.13: IRQ Sense Control Register (ISCR)
The other register relating to IRQ interrupts is the IRQ sense control
register (ISCR). Using bits 5 to 0 of this register, you can set the sense level to
low or the trailing edge for six IRQ interrupts individually.
These two differ as follows. When it is set to the low level, the system
assumes that interrupt requests are continuously generated while the low-level
voltage is applied to an IRQ interrupt request input pin. When it is set to the
trailing edge, on the other hand, the system assumes that an interrupt request is
generated only when the low-level voltage is first applied to an IRQ interrupt
request input pin and does not assume continuous generation even if the low-
level voltage continues to be applied. Select a setting appropriate for your
system.
7.3.4 Interrupt Operations

(1) Shift to an interrupt handling routine
Figure 7.14 shows three operations performed by the CPU when an

interrupt is generated:
Figure 7.14: Interrupt Operations
Figure 7.15: Storage of the PC and CCR Values in the Stack
During stacking, the first operation after interrupt generation, the 8-bit
CCR value is stored in the address obtained by decrementing the stack pointer
by 4 and the 24-bit PC value in the following three addresses. This operation is
almost the same as for subroutine call instructions (JSR and BSR instructions)
and stores the PC value at interrupt generation as the return address in the
stack.
It differs from the subroutine call instructions in that the CCR value at
interrupt generation is also stored in the stack. The reason is as follows: since
the I bit in the CCR is set to 1 (interrupt disabled) after interrupt generation, the
I bit that has been 0 during original program execution is stored in the stack to
restore the CCR from the stack when returning to the original program and
resetting the I bit to 0 (interrupt enabled).
Figure 7.16: Loading the Interrupt Vector to the PC
During loading the vector to the PC, the second operation after interrupt
generation, the vector method is employed as with reset operation.
In the case of interrupts, the start address of each interrupt handling routine is
also referred to as the interrupt vector and this 24-bit interrupt vector is stored
in the lower three addresses of the four interrupt vector addresses in the
memory, which are determined by the interrupt type.
For example, the NMI interrupt vector addresses are the four starting
from H'00001C and the IRQ0 interrupt vector addresses are from H'000030.
This mechanism enables execution to be moved to different interrupt handling
routines according to the type of interrupt generated. For the vector address of
each interrupt, refer to Table 7.1 in the following section.
As the last operation after interrupt generation, the CCR sets the I bit in
the CCR to 1 to disable (mask) interrupts. This means that after an interrupt is
generated to move execution to an interrupt handling routine, any other
generated interrupt will be accepted. Another interrupt is accepted only after
the current interrupt routine is completed and the RTE instruction, the last
instruction in an interrupt routine, is executed.
The NMI interrupt, however, is always accepted irrespective of the I bit in the
CCR.
(2) Return from an interrupt handling routine
Figure 7.17: Restoration of the CCR and PC Values from the Stack
You must specify the RTE instruction at the end of every interrupt
handling routine and its execution enables processing to return to the original
program to continue. The RTE instruction works almost the same as the RTS
instruction, an instruction to return from a subroutine. The difference is that the
RTE also restores the CCR value stored in the stack.
Although the RTE and RTS instructions have similar names and operations,
they are completely different and misuse of them will cause a program to
malfunction. Remember to put the RTE instruction at the end of an interrupt
handling routine and the RTS instruction at the end of a subroutine.
Also note that if an interrupt handling routine arbitrarily uses a general-
purpose register, the value in the register changes when execution is returned to
the original program, causing the normal process to fail. To prevent this from
happening, develop a program so as to start processing in an interrupt handling
routine after storing the general-purpose register to be used in the stack and
restore the register from the stack before returning to the original program
using the RTE instruction. The PUSH instruction is used to store a general-
purpose register in the stack and the POP instruction to restore it. Use these
instructions properly to store and restore general-purpose registers.
7.4 Vector List
As described earlier, all exception handling routines employ the vector

method to notify the CPU of the start address of the program to which
execution is moved. Table 7.1 shows the list of exception handling vector
addresses:
The vector addresses are located in the area between H'000000 (start
address of the memory space) and H'0000F3. This address area is called the
"vector area". In this area, only data called "vectors" that represent the start
address of each interrupt handling routine can be placed and no other data or
program is allowed. The addresses marked "system reservation" in the table
refer to free areas, which have no definite vectors to be placed.
As described earlier, be sure to generate reset when turning the
microcomputer on. Reset loads the reset vector stored in the reset vector
addresses (between H'000000 and H'000003) within the vector area to the PC.
In the reset vector addresses, the defined reset vector must have been stored
before power-on. This means that the reset vector addresses must be in the
ROM in which the reset vector is written.
Whether to set other exception handling vector addresses in the ROM
or RAM depends on the system. When using the microcomputer as an internal
controller, however, other exception handling vector addresses are generally
located in the same ROM as the reset vector addresses.
7.5 Sample Interrupt Programs
Let's take a look at some sample programs to perform IRQ0 interrupt

handling after the H8/3048 is turned on and reset. Programs to generate
exception handling routines require that the vectors be stored in the memory
beforehand and that interrupts be enabled.
What all the programs shown below do is to increment the contents of
the COUNTER address in the memory by 1 every time the IRQ0 interrupt is
generated. You can determine how many IRQ0 interrupts have been generated
by referring to the contents of the COUNTER address afterward.
Table 7.1: H8/3048 Exception Handling Sources
C Language sample
#include <machine.h>; /* include embedded function */
/* Internal I/O register address define */
#define IER (*(volatile unsigned char *)0xFFFFF4)
#define ISCR (*(volatile unsigned char *)0xFFFFF5)
/* define variavle */
unsigned long counter ;
/* stack area size */
#pragma stacksize 0x100
/* Power ON Reset function */
__entry(vect=0) void main(void)
{
counter= 0 ; /* clear counter */
ISCR |= 0x01 ; /* select interrupt signal falling edge */
IER |= 0x01 ; /* enable IRQ0 terminal */
set_ccr(0) ; /* clear interrupt mask */
while(1) ; /* endless loop */
}
/* IRQ0 function */
// vector 12 IRQ0
__interrupt(vect=12) void INT_IRQ0(void)
{
counter++ ;
}
1. What happens if an enabled interrupt request is generated while the
CPU is executing a program?
(A) The current instruction is interrupted for exception handling.
(B) Exception handling is performed after the current instruction is
completed.
(C) Exception handling is performed after the program is completed.
Answer: (B)
(A) disables the original program to properly continue even after execution is
returned from the interrupt handling routine to the next instruction of the
original program.
(C) refers to the situation where interrupts are disabled. If (C) is true, no
interrupt can be generated for a program containing a loop since it is never
completed.
2. Which describes the correct type of exception handling sources in the

H8/3048?
(A) Reset only
(B) Interrupts only
(C) Reset and interrupts
Answer: (C)
The H8/3048 has both reset and interrupt exception handling routines.
3. What is common to all exception handling routines?

(A) Employs the vector method.
(B) Sets the I bit in the CCR to 0.
(C) Initializes the internal I/O registers.
Answer: (A)
(B) Exception handling sets the I bit to 1.
(C) Interrupts do not initialize the internal I/O registers.
4. What is the vector address?

(A) Addresses between H'000000 and H'000003 in the memory space.
(B) Start address of an exception handling routine.
(C) Specific address area for storing the start address of an exception
handling routine.
(D) Specific address area for storing the return address at exception
handling generation.
Answer: (C)
(A) refers to the vector address for reset only.
(B) refers to the vector.
(D) refers to the stack.
5. What do you do first after turning the microcomputer on to start

execution from a particular program?
(A) Generate the NMI interrupt.
(B) Generate reset.
(C) Initialize the SP (ER7).
Answer: (B)
You must generate reset to input the start address of a particular program in
the PC.
(A) does not determine to which address execution is returned by the RTE
instruction at the end of the NMI interrupt handling routine.
As for (C), a program to initialize the SP cannot be started without generating
reset.
6. Why is a circuit using a reset IC configured around the reset pin?

(A) To prevent overcurrent from entering the reset pin.
(B) To apply the high-level voltage to the reset pin even when the power is
turned off.
(C) To apply the low-level voltage to the reset pin after the power is turned
on.
Answer: (C)
The reset IC is used to apply the low-level voltage to the reset pin for a certain
period of time after power-on.
7. You developed an IRQ1 interrupt handling routine. From which

address do you store it?
(A) Any address excluding the vector area as long as the memory exists.
(B) H'000000.
(C) H'000034.
(D) Any address in the vector area.
Answer: (A)
(B) refers to the vector address for reset and (C) to that for IRQ1.
As for (D), no data or programs except vectors should be stored in the vector
area.
8. By how many does the value in the SP (ER7) change immediately before
and after an interrupt is generated?
(A) +2
(B) +4
(C) -2
(D) -4

Answer: (D)
The SP is decremented by 4 and the PC and CCR are stored in a 4-address
area in the stack.
<Interrupts>
Write a program to use an external interrupt as you have learned in
Chapter 7 and run it on the training board. Work out through the following
steps:
• Complete the exercise source program by filling out its blanks.
• Make sure that the program runs successfully on the training board.
• If the program will not run as specified in the exercise, consult the
sample answer and make necessary changes to it before rerunning it.
Turning on jumper J6 on the training board will connect SW28 and the
CPU IRQ5 pin to each other. Press SW28 to input a low-level voltage to the
IRQ5 pin; release it to input a high-level voltage to the IRQ5 pin.
Eight LEDs are connected by way of the 74LV574 placed at address
H'FFFF12. The following correspondence exists between the value written to
each bit of address H'FFFF12 and the resulting on/off status of the LED:
0 ... LED on
1 ... LED off
All eight LEDs come initially off. Each time you press SW28, the eight LEDs
increment as an eight-digit binary incremental counter. Once all the eight have
lit up, they go out to continue incrementing further again.
• Configure the program to raise one IRQ5 interrupt each time you press
SW28. To this end, IRQ5 must be configured so it will be sensed at the
trailing edge. Remember also to enable the IRQ5 interrupt.
• The IRQ5 interrupt handler increments the value at the COUNT address
in internal RAM by one.
• Allowing for the correspondence between the value of 0 or 1 written to
address H'FFFF12 and the resulting on/off status of the LED, it is
necessary to create the one's complement of the value that is
incremented by one and write it to address H'FFFF12.

Chapter 8
Parallel Data Input/Output
Although the programs described in Chapter 6 use the memory and

CPU registers only, this chapter explains how to input and output parallel data.
Among various data input and output, those of parallel data are the simplest
and have a wide variety of uses. They are used for general purposes such as
inputting signals from various sensors and turning lamps or heaters on/off.
8.1 Parallel Data Input/Output
In a microcomputer-applied system, you may want to know the on/off

statuses of some switches or display the current statuses using LEDs or others.
Such simultaneous input/output of several-bit data is referred to as parallel data
input/output and the peripheral functions for parallel data input/output are
called "I/O ports", which have registers and pins as shown in Figure 8.1.
Figure 8.1: Parallel Data Input/Output
Parallel data input/output using I/O ports are performed through

registers as shown in Figure 8.2.

Figure 8.2: Parallel Data Input/Output Method
Input function
"1" can be read from I/O port registers when the "High" voltage is
applied to I/O port pins or "0" when "Low". Based on the values read from I/O
port registers, the on/off statuses of the switches connected to pins or the
high/low status of the comparator output can be determined.
Output function
The "Low" voltage is output from I/O port pins when the values written
in I/O port registers are "0" or "High" when "1". Based on the values written in
I/O port registers, the LEDs connected to pins or relays can be turned on and
off.
8.2 Port Configuration
The H8/3048 has ports 1 to B as I/O ports available for parallel data
input/output. Port 7 is for input only.
These ports have data direction registers (DDRs) and data registers
(DRs) as shown in Table 8.1.
The H8/3048 employs the memory-mapped I/O method for data
input/output. This method has no dedicated data input/output instructions such
as "data input instructions" or "data output instructions" and instructions for
writing/reading to/from the memory are also used for data input/output. For
data input/output functions (various registers), addresses are allocated as with
the memory. In the case of the H8/3048, the H'FFFF10 to H'FFFFFF addresses
are used for data input/output functions (various registers).
Accordingly, the MOV and bit handling instructions can be used as
they are and reading/writing from/to addresses between H'FFFF10 and
H'FFFFFF are regarded as being data input/output. In I/O ports, data are output
from pins by writing them in the DR of each port and the statuses of pins can
be input by reading data from the DR.

Table 8.1: I/O Port Register Map
Figure 8.3 shows the I/O port block diagram.
Figure 8.3: I/O Port Block Diagram
Depending on the DDR setting, the I/O port pins can be used for either
input or output. Write "1" in the DDR of the target bit to use the corresponding
pin for output or "0" for input.
Since the DDR is a write-only register, the setting cannot be read even
if the MOV instruction is used. If an instruction for reading is executed by
mistake, "1" is always read irrespective of the setting.

In the DR, a flip-flop function is provided for the output only. Output data once
written is kept (output) until the next data is written. During data input, on the
contrary, the voltage signal being input to a pin is read as it is, not the data
written in the DR output flip-flop.
Precautions on connecting external equipment to I/O ports

The DDR of each port is set to "0" (input) without modification after
resetting and the pin is in "High-Z" (high impedance) state. Since the DR is
also set to "0" by default, setting the DDR to "1" without modifying the DR
changes the pin to "Low". For circuits like the TTL, the "High-Z" state of the
input is the same as the "High" input.
If a TTL is connected to a port and equipment operating when output
from the port is "High" is externally connected, some operation will be
performed between the time immediately after resetting and until the port is
changed to output.
To prevent this abnormal operation, develop a circuit so as to operate
when output from a port is "Low" and set the DR to "1" before setting the DDR
to output. Since this setting changes the pin from "High-Z" to "High", no
abnormal operation occurs after resetting, keeping external equipment stopped.
8.3 How to Use Ports

8.3.1 Sample Port Output
Figure 8.4 shows an example to set port A to output to control LEDs on/off.
Figure 8.4: Control of LEDs On/Off
In a pin set to output by the DDR, the voltage varies with the contents
of the DR. When LEDs are turned on using port A as shown in Figure 8.4,
write "1" in the corresponding bit of the PADDR to set the corresponding pin
of port A to output. To turn the LEDs on, write "0" in the corresponding bit of

the PADR, or "1" to turn them off. To turn only LED1 on, write B'00000010
(H'02) in the PADR.
For the bits set to input (bits to which no LED is connected), writing
data in the DR will not output voltage to the pin. If you attempt to read data
from the DR, the pin voltage, not the written value, is read. As a result, writing
is invalid, not affecting the pin.
LEDs are turned on when a current (IF) of about 10mA is circulated
forward of the diodes. At this time, a forward voltage (VF) of about 2V is
required. Since the port A pin of the H8/3048 will not supply enough current to
drive the LEDs directly, the HD74AC series' CMOS circuit is connected to
drive them. The HD74AC family is capable of supplying a 24mA current with
either "High" or "Low" output. In addition, 4V can be reserved from the
"High" voltage (VOH) at this time to drive the LEDs. Resistance is inserted to
prevent a current of over 10mA from flowing into the LEDs. The resistance to
be inserted is obtained as follows:
Resistance [Ohm] ³ (4V - 2V)/10mA
Port A for turning LEDs on and off using this circuit is initialized as follows:
PADDR: .EQU H'FFFFD1 ; Defines the PADDR address
PADR: .EQU H'FFFFD3 ; Defines the PADR address
MOV.B #B'00000011,R0L ; Prepares a setting in R0L
MOV.B R0L,@PADR ; Sets the PA1 and PA0 default output values (off)
in PADR
MOV.B R0L,@PADDR ; Writes "1" in lower 2 bits of PADDR and sets
PA1 and PA0 to output pins
Write "1" in the lower 2 bits of the PADR and then set the lower 2 pins
of port A to output. This turns both LED1 and LED2 off by default.
To turn only LED1 on/off, use the following instructions:
BCLR #0,@PADR ; Turns only LED1 on

BSET #0,@PADR ; Turns only LED1 off
BNOT #0,@PADR ; Inverts the on/off status of LED1 only
To control a specific LED only, use the bit handling instruction as

shown above. To control several LEDs simultaneously, on the other hand, it is
better to use the MOV instruction for bulk change than using the bit handling
instruction to change the on/off status for each LED. This is because the bit
handling instruction changes the statuses one by one, taking a long time to
change all the LEDs.
MOV.B #B'00000000,R0L ; Sets LED1 and LED2 On data in R0L

MOV.B R0L,@PADR ; Turns LED1 and LED2 on simultaneously
MOV.B #B'00000011,R0L ; Sets LED1 and LED2 Off data in R0L
MOV.B R0L,@PADR ; Turns LED1 and LED2 off simultaneously

MOV.B @PADR,R0L ; Loads the current output value (On data) to R0L
XOR.B #B'00000011,R0L ;Sets LED1 and LED2 On/Off inversion data in R0L
MOV.B R0L,@PADR ; Inverts LED1 and LED2 on/off simultaneously
Precautions on initializing I/O ports

When initializing I/O ports to output or input (described in the next
section), be sure to use the MOV instruction to write data in the DDR. Unlike
the DR, the bit handling instruction is not available because the BSET or
BCLR instruction is executed in three operations of read, modify and write. As
a result, executing the following instruction for the PADDR to set only PA0 to
output also sets the PA7 to PA1 I/O pins to output.
BSET #0,@PADDR ; Sets only the PA0 pin to output

; Wrong. The PA7 to PA1 pins are also set to output.
After the BSET instruction is executed, the PADDR value is read in 8-

bit units. Since the PADDR is a write-only register, 8 bits are all read to be "1"
at this time no matter whether "0" or "1" is actually set. After this, bit 0
specified by the instruction is changed to "1" (although it is "1" in the first
place) and written in 8 bit units. As a results, all pins are set to output.
BSET #0,@PADDR ; (1) Read: Reads B'11111111 from PADDR

; (2) Modify: Changes bit 0 of the read value to "1"
; (3) Write: Writes B'11111111 to PADDR
; As a result, all pins are set to output
The DDR is a write-only register and incapable of reading. If any bit

handling instruction to cause reading is used for it, a bit not targeted for
handling may be set to an unexpected value. Remember that the bit handling
instruction must not be used for the I/O port DDR.
C Language Sample
PADDR: .EQU H'FFFFD1 ; Defines the PADDR address
PADR: .EQU H'FFFFD3 ; Defines the PADR address
MOV.B R0L,@PADR ; Sets the PA1 and PA0 default output values (off) in PADR
MOV.B R0L,@PADDR ; Writes "1" in lower 2 bits of PADDR and
sets PA1 and PA0 to output pins
#define PADDR (*(volatile unsigned char *)0xffffd1)

#define PADR (*(volatile unsigned char *)0xffffd3)
PADR = 0x03 ;
PADDR = 0x03 ;

Write "1" in the lower 2 bits of the PADR and then set the lower 2 pins
of port A to output. This turns both LED1 and LED2 off by default.
To turn only LED1 on/off, use the following instructions:
BCLR #0,@PADR ; Turns only LED1 on
PADR &= 0xfe ;
BSET #0,@PADR ; Turns only LED1 off
PADR |= 0x01 ;
BNOT #0,@PADR ; Inverts the on/off status of LED1 only
PADR ^= 0x01 ;
8.3.2 Sample Port Input
Figure 8.5 shows an example for setting port B to input to judge the
switch on/off status.
Figure 8.5: Judgement of Switch On/Off Status
As for the pins set to input by the DDR and port 7, the statuses can be
read by reading the DR. To read the status of the switch connected to port B as
shown in Figure 8.5, write "0" in the corresponding bit of the PBDDR and set
the corresponding pin of port B to input to read the PBDR. At this time, "0" is
read from the PBDR if the switch is turned on, or "1" if turned off. If nothing is
done after resetting, the DDR is set to "0", or input, by default. The switch
status can be checked only by reading the DR.
Port B for judging the switch on/off status using this circuit is
initialized as follows: In the following example, unused pins and all 8 pins of
port B are set to input.
PBDDR: .EQU H'FFFFD4 ; Defines the PBDDR address

PBDR: .EQU H'FFFFD6 ; Defines the PBDR address
MOV.B R0L,@PBDDR ;Handles PBDDR to set PB3 and PB2 to input pins
;The above 2 instructions are not required after resetting

To check the SW1 status after initializing port B and call the INPUT
subroutine after it is turned on, use the following instructions (the contents of
the INPUT subroutine is not shown below):
WAIT1: BTST #2,@PBDR ; Judges the SW1 status

BNE WAIT1 : Branches to WAIT1 if not on
JSR @INPUT ; Calls INPUT subroutine
To check both SW1 and SW2 statuses and call the OUTPUT subroutine
after they are turned on, use the following instructions (the contents of the
OUTPUT subroutine is not shown below):
WAIT12: MOV.B @PBDR,R0L ; Reads all 8 bits of port B to R0L

AND.B #B'00001100,R0L ; Judges the SW1 and SW2 statuses only
BNE WAIT12 : Branches to WAIT12 unless both are on
JSR @OUTPUT ; Calls OUTPUT subroutine
As with the sample output for port A, it is recommended that the bit
handling instruction be used to judge a single switch status or a combination of
MOV and logical instructions to judge several switches simultaneously.
1. Which of the following can be achieved using I/O ports?

(A) To simultaneously output 8-bit data using one pin.
(B) To simultaneously input 4-bit data using four pins.
(C) To generate an interrupt when the "Low"-level voltage is applied.
Answer: (B)
(A) Data of several bits cannot simultaneously be input or output using one
signal line.
(C) This is the function of an interrupt input pin.
2. Where is the DR of an I/O port located?

(A) In the CPU, with the name of "Pn data register" (PnDR).
(B) Located at any address in the memory by a user.
(C) Located at a specific address in the memory.
Answer: (C)
Since the H8/3048 employs the memory-mapped I/O method, the DR of an I/O
port is located at a specific address in the memory.
3. How is an I/O port pin set to input when viewed externally?

(A) In "High-Z" state
(B) Outputs the "High"-level voltage.
(C) Outputs the "High"- or "Low"-level voltage depending on whether the
DR value is "1" or "0".
Answer: (A)
(B) and (C) are observed when a pin is set to output. An input pin is in High-Z
state.
4. At which address is the P3DR located?
Answer: H'FFFFC6
Refer to "Table 8.1: I/O Port Register Map" in 8-2. Although you need not
remember the address, remember which table you should refer to.
5. At which address is the PADDR located?
Answer: H'FFFFD1
Refer to "Table 8.1: I/O Port Register Map" in 8-2. Although you need not
remember the address, remember which table you should refer to.
6. To use an I/O port pin as output, what do you do with the

corresponding bit of its DDR?
Answer: Write "1"

Write I/O in the DDR bit to set the corresponding port pin to output/input.
<Parallel data input/output>
Write a program to use parallel data input/output as you have learned

in Chapter 8 and run it on the training board. Work out through the following
steps:
Take a close look at the circuit of SW12 in the training board block
diagram. To determine whether SW12 has turned on or off, output a low-level
voltage from PA6 and leave PA3, PA4, and PA5 in the input state. By so
doing, you can determine the correspondence between the value read from P70
and the resulting on/off status of SW12, as follows:
0 ... SW12 on
1 ... SW12 off

Eight LEDs are connected by way of the 74LV574 placed at address
H'FFFF12. The following correspondence exists between the value written to
each bit of address H'FFFF12 and the resulting on/off status of the LED:
0 ... LED on
1 ... LED off
All eight LEDs come initially off. Each time you press SW12, a software timer
causes the eight LEDs to increment as an eight-digit binary incremental
counter at regular intervals of time. Once all the eight have lit up, they go out
to continue incrementing further again.
• Because processing does not advance further until you press SW12
once, allow the program to continue looping as long as SW12 is tested
off, and let it exit the loop when SW12 is tested on.
• Program the software timer as a subroutine to gain time. Write a
program that loads a general-purpose register with a given value at the
start of the subroutine and then loops to decrement that value by one
until the result of decrementing equals 0, when the program should exit
the loop and leave the subroutine. The loop count determines how
much time the subroutine gains. Too short time gained would make
changes in the display status of the LEDs look faster beyond visual
recognition.
• As the main routine loops, the value at the COUNT address in internal
RAM is incremented by one after each interval of time allowed by the
software timer.
• Allowing for the correspondence between the value of 0 or 1 written to
address H'FFFF12 and the resulting on/off status of the LED, it is
necessary to create the one's complement of the value that is
incremented by one and write it to address H'FFFF12.

Chapter 9
Analog Voltage Input
Although parallel data described in the previous chapter are used for
inputting and outputting digital voltages, this chapter explains the A/D
converter used for inputting analog voltages. A/D conversion is used for
inputting from temperature sensors.
In this chapter, you should fully understand the methods for checking
and clearing the status flag (ADF) when A/D conversion has been completed or
in other cases since they are frequently used.
Note: The following is a negative logic signal:
9.1 A/D Converter Configuration
In a microcomputer-applied system, processing may require handling of

information input as analog voltages by an analog sensor (sensor which
generates analog voltages according to physical values such as temperature and
pressure). Since the microcomputer, however, is composed of digital circuits, it
is incapable of handling analog voltages as they are.
Analog voltages, therefore, must be converted into numeric data of several bits
before processing. This conversion from analog to digital is accomplished by
the A/D converter, which is a peripheral function designed to convert analog
voltages externally input into digital numeric data.
The H8/3048 A/D converter employs the successive comparison

method and has the following characteristics:
Input voltage range 0V to 5V (range of analog input voltages which can be converted into digital
numeric data.)
You can use desired voltages between 0V as the minimum and 0V to 5V as the
maximum.
You can obtain high-precision A/D conversion results, however, by setting the
maximum voltage as high as possible.
Resolution 10 bits (refers to how many bits of digital numeric data voltages are to be
converted into.)
10-bit resolution means that you can obtain conversion results in two to the
tenth power (1024) steps.
If you do not need so many steps, use the required bit count from the most
significant bit from the 10 bits. For example, you can obtain conversion results

in two to the eighth power (256) by using the upper 8 bits or to the fifth power
(32) by using the upper 5 bits.
Conversion time 266 or 134 states (time required for conversion.)
For 134-state conversion (shorter conversion time), one conversion takes 6.7
microseconds in the case of 20MHz operation. In this case, the sampling
measurement of signals having a period of
6.7 microseconds x 2 = 13.4 microseconds or longer (frequency of 75kHz or
lower)
is possible based on the sampling theorem.
Since the A/D converter is a circuit for handling analog electrical

signals, noise appears as conversion errors. If you want to suppress conversion
errors, take sufficient measures against them.
Figure 9.1: A/D Converter Block Diagram
The following explains the A/D converter configuration in the H8/3048.

It has 12 external input pins. AN0 to AN7 are designed to input analog
voltages to be A/D converted. These 8 input pins are switched to perform A/D
conversion one by one. AVcc is a power supply pin and AVss is a ground pin.
Since they are separated from other power supply or ground pins, the A/D

converter will not function unless power is supplied to them. If you want to
suppress conversion errors, sufficient measures are also required in this case,
too. VREF is a reference voltage pin for converting voltages between AVss and
VREF into 10 bits (1024 steps). A/D conversion is started after the trailing edge
has externally been input to the ADTRG pin. A/D conversion can also be
started by an instruction.
The analog voltage input in the selected analog input pin is converted
into 10-bit binary data using the successive comparison method and stored in
the AD data registers (ADDRA to ADDRD). There are four 16-bit A/D data
registers from A to D and conversion results are stored in one of them
depending on which analog input pin has been selected. The A/D conversion
results are read using the MOV instruction. The A/D converter has two more
registers for controlling other settings such as the operating mode, which are
described in the following section.
9.2 A/D Converter Registers
Table 9.1 shows the A/D converter register configuration.

Table 9.1: A/D Converter Register Configuration
Each register is described below.
(1) A/D control status register (ADCSR)

Figure 9.2 shows the A/D control status register (ADCSR), which
selects the channel to be A/D converted, instructs the start of A/D conversion
and judges its end.

Figure 9.2: A/D Control Status Register (ADCSR)
Although all 8 bits of this register are capable of reading, indicated by

"R" under each bit, certain conditions apply to one of them regarding writing,
indicated by "W" in parentheses with "*" attached. The bit marked "W" in
parentheses with "*" attached is generally called the "status flag", which
requires some precautions. The status flag bit also exists in other internal I/O
registers, to which common precautions apply. As for this flag, press the link
button shown above ("How to use the status flag") to completely master the use
before proceeding.
(2) A/D control register (ADCR)

Figure 9.3 shows the A/D control register (ADCR), which has only one
significant bit (bit 7). If this trigger enable bit (TRGE) is not changed from its
default value of 0, A/D conversion will not be started even if the trailing edge
is input to the ADTRG pin. In this case, conversion can be started by
instruction only (setting the ADST of the ADCSR to 1).
If the TRGE is set to 1, on the other hand, A/D conversion can be
started by inputting the trailing edge to the ADTRG pin. In this case, however,
A/D conversion can also be started by instruction.

Figure 9.3: A/D Control Register (ADCR)
Note: Do not set bit 0 of the ADCR to 1.
(3) A/D data registers A to D (ADDRA to ADDRD)

The 16-bit A/D data registers are designed to store A/D conversion
results and located at two consecutive addresses in the memory. Figure 9.4
shows the A/D data register A (ADDRA) as an example. Although the A/D
data registers B (ADDRB) to D (ADDRD) have different analog input pins and
addresses, the use is completely the same.
Although the ADDRA to ADDRD are 16-bit registers, conversion
results are stored in the upper 10 bits. To use only the upper 8 bits of the
conversion results, read them in byte-size units. To use all 10 bits of the
conversion results, read them in word-size units and handle them by shifting
them to the right by 6 bits or by other means.
Figure 9.4: A/D Data Register A (ADDRA)
9.3 Sample Use of A/D Converter
This section shows a program using an A/D converter, which is

assumed to operate under the following conditions:
• The AN0 analog voltage is A/D converted in single mode (results are
stored in the ADDRA).
• The conversion time is 134 states.
• The ADTRG pin is not used.
• The A/D conversion complete interrupt is not used.
• The main routine obtains A/D conversion results in 8-bit units to store
them in R1H and calls the OUTPUT subroutine.
Then, the above operation is repeated (the contents of the OUTPUT subroutine
are not shown).

C Language Sample
#include "iodefine.h" /* include I/O address define
header file */
/* define variavle */
unsigned char data ;
{
AD.CSR.BYTE = 0x08 ; /* single mode , 134 clock , not use
interrupt */
while(1) { /* endless loop */
AD.CSR.BIT.ADST = 1 ; /* start A/D convert */
while(AD.CSR.BIT.ADF == 0) ; /* wait A/D convert end */
AD.CSR.BIT.ADF = 0 ; /* clear ADF */
data = AD.DRA >> 8 ; /* data <- ADDRA */
}
}
1. You want to convert the voltage externally input into 9-bit (512-step)
digital numeric values using the A/D converter. What do you do?
(A) Since the resolution of the A/D converter is fixed at 10 bits, 9-bit
conversion results cannot be obtained.
(B) Use the ADCSR to change the resolution setting from the default of 10
bits to 9 bits.
(C) Use the upper 9 bits from the 10-bit A/D conversion results.

Answer: (C)
When you need a resolution lower than 10 bits, you can simply use the
required bit count from the most significant bit from the conversion results.
(B) This setting is not available in the H8/3048.
2. How many methods can you use to start conversion by the A/D
converter?
(A) Only one method to externally input a signal.
(B) Only one method to use an instruction.
(C) Two methods to externally input a signal and use an instruction.
Answer: (C)
The H8/3048 is capable of starting conversion with two methods.
3. Where are the A/D conversion results of analog voltages input to the
AN3 pin stored?
Answer: ADDRD
Refer to "Figure 9.1: A/D Converter Block Diagram" in 9.1 to understand the
relationship between the analog input pin and the ADDR.
4. How is the ADF changed after the first A/D conversion regarding the
selected input channel is completed?
Answer: The ADF is changed to 1

The ADF flag is designed to indicate that the first A/D conversion has been
completed.
5. You want to obtain A/D conversion results regarding four input

channels from AN0 to AN3 in scan mode. How do you set the lower 3 bits
of the ADCSR?
Answer: B'011
Understand how the ADCSR is used by referring to "Figure 9.2: A/D Control
Status Register (ADCSR)" in 9.2.
<A/D converters>
Write a program to use an A/D converter as you have learned in
Chapter 9 and run it on the training board. Work out through the following
steps:

A trimmer is connected to the AN4 pin of the training board. Fully turn
the trimmer clockwise to input the VREF voltage to the AN4 pin, or fully turn
it counterclockwise to input the AVss voltage to the AN4 pin.
Further, eight LEDs are connected by way of the 74LV574 placed at
address H'FFFF12. The following correspondence exists between the value
written to each bit of address H'FFFF12 and the resulting on/off status of the
LED:
0 ... LED on
1 ... LED off
SW28 is connected to the ADTRG pin. Press SW28 to input a low-
level voltage to the ADTRG pin; release it to input a high-level voltage to the
ADTRG pin.
Convert the analog voltage input to the AN4 pin from analog to digital at a
134-state conversion speed in scan mode and display the conversion result as
an 8-bit binary value on the eight LEDs. As you turn the trimmer to vary the
analog input voltage, the LED display should vary accordingly.
If you have successfully written a program that meets the requirements

defined above, modify it this time so it will carry out a single run A/D
conversion each time SW28 is pressed and display the conversion result as an
8-bit binary value on the eight LEDs. Even when you turn the trimmer, the
LED display will not change unless you press SW28.
• Configure the A/D converter for scan mode, 134-state, and AN4
selection before starting the conversion process.
• The program should loop by waiting until each run of A/D conversion
completes, or ADF equals 1, and reading the conversion result for
output on the LEDs.
• Write the display data resulting from the conversion process to address
H'FFFF12. Allowing for the correspondence between the value of 0 or
1 written to address H'FFFF12 and the resulting on/off status of the
LED, it is necessary to invert the conversion result and write it to
address H'FFFF12.

Chapter 10
Analog Voltage Output
Unlike A/D conversion, D/A conversion is designed to output analog

voltages. This conversion is easy to understand since it is simpler to use than
A/D conversion.
10.1 D/A Converter Configuration
In a microcomputer-applied system, an analog actuator (actuator which

controls physical values such as rotation speed and amount of generated heat
using analog voltages) may have to be controlled using analog voltages. Since
the microcomputer, however, is composed of digital circuits, it is incapable of
outputting analog voltages as they are.
Analog voltages, therefore, must be output after being converted from
several bits of digital numeric data. This conversion from digital to analog is
accomplished by the D/A converter, which is a peripheral function designed to
convert digital numeric data into analog voltages.
The H8/3048 D/A converter has the following characteristics:

Output voltage range 0V to 5V (max.)(range of analog voltages which can be output.)
Resolution 8 bits (refers to how many bits of digital numeric data voltages
are to be converted into.)
8-bit resolution means that voltages can be output in two to the
eighth power (256) steps within the output range.
Conversion time 10 microseconds (time required for conversion.)
An actuator capable of receiving analog voltages which change at
a time interval of 10 microseconds or longer can be controlled.

Figure 10.1: D/A Converter Block Diagram
The following explains the D/A converter configuration in the H8/3048.

It has 5 external pins. DA0 and DA1 are designed to output D/A converted
analog voltages. AVcc is a power supply pin and AVss is a ground pin. Since
they are separated from other power supply or ground pins, the D/A converter
will not function unless power is supplied to them. If you want to suppress
conversion errors, sufficient measures are also required in this case, too. VREF is
a reference voltage input pin for outputting voltages between AVSS and VREF
with 8-bit (256-step) resolution.
There are two 8-bit D/A data registers (DADR0 and DADR1). When
analog output is enabled, data in the D/A data register are D/A converted for
output from the analog output pin.
10.2 D/A Converter Registers
Table 10.1 shows the D/A converter register configuration.

Table 10.1: D/A Converter Register Configuration
Each register is described below.

(1) D/A data registers 0 and 1 (DADR0 and DADR1)
The D/A data registers 0 and 1 (DADR0 and DADR1) are 8-bit,
read/write registers designed to store data to be D/A converted. Figure 10.2
shows the DADR0 as an example. The conversion results of data in the
DADR0 are output from the DA0 pin. Although the DADR1 has different
analog output pins and addresses, the use and meanings are completely the
same.
When analog output is enabled, the values in the DADR are always
D/A converted for output to the analog output pin.
Figure 10.2: D/A Data Register 0 (DADR0)
(2) D/A control register (DACR)

Figure 10.3 shows the D/A control register (DACR), which is operated
for D/A conversion. When the DACR is operated to enable analog output, data
in the DADR are D/A converted and analog voltages are always output from
the analog output pin. Output continues unless analog output is disabled. If the
values in the DADR are changed during output, the corresponding voltages are
output immediately after the conversion time has elapsed. Although the
maximum conversion time is 10 microseconds, it may take some time until the
output voltage reaches a certain level if the external circuit load is large.
Figure 10.3: D/A Control Register (DACR)

(3) D/A standby control register (DASTCR)
Figure 10.4 shows the D/A standby control register (DASTCR), which
is designed to enable or disable D/A output in software standby mode. The
details are not described here. Use it in default state.
Figure 10.4: D/A Standby Control Register (DASTCR)
1. You want to convert 10-bit digital numeric values into voltages in 1024
steps using the D/A converter. What do you do?
(A) Since the resolution of the D/A converter is fixed at 8 bits, they cannot
be converted into voltages in 1024 steps.
(B) Use the ADCR to change the resolution setting from the default of 8
bits to 10 bits.
(C) Multiply the 8-bit D/A conversion results by 1.25 (10/8).
Answer: (A)
(B) This is not available in the H8/3048.
(C) The D/A conversion results remain in 8-bit units (256 steps) even after this
multiplication.
2. How many methods can you use to start conversion by the D/A
converter?
(A) Only one method to externally input a signal.
(B) Only one method to use an instruction.
(C) Two methods to externally input a signal and use an instruction.
Answer: (B)
In the case of the H8/3048, conversion can only be started using an instruction.
3. From which pin are the voltages obtained by D/A converting numeric
data in the DADR1 output?

Answer: DA1 pin
Read "(1) D/A data registers 0 and 1 (DADR0 and DADR1)" in 10.2 to
understand the relationship between the DADR and the analog output pin.
4. You want to D/A convert both channels 0 and 1. How do you set the
upper 3 bits of the DACR?
Answer: Write B'011, B'010 or B'11-.

Understand how the DACR is used by referring to "Figure 10.3: D/A Control
Register (DACR)" in 10.2.
5. How is the DACR changed after the first D/A conversion of the specified
channel is completed?
Answer: There is no change

The H8/3048 has no flag to indicate that D/A conversion has been completed.
The DACR register is designed to enable or disable D/A conversion.
<D/A converters>
Write a program to use a D/A converter as you have learned in Chapter
10 and run it on the training board. Work out through the following steps:
The training board houses a circuit in which an operational amplifier
connected to the DA0 pin turns on an LED, so that the D/A converter output
voltage can control the brightness of the LED.
The higher the output voltage, the brighter the LED glows; the lower
the output voltage, the dimmer the LED becomes. A voltage of approximately
2 V is required to turn on the LED. The LED will stay out under an output
voltage of 0 to 2 V. Changes in the LED brightness would be more easily
identifiable visually by changing the output voltage from 1 V to 5 V.

Output a voltage of 1.2 V to 5 V from the DA0 pin to check that the LED
changes in brightness accordingly.
Set DADR0 to H'40 to output 1.2 V or to H'FF to output 5 V. A software timer
allows a voltage of 1.2 V to 1.5 V to be output iteratively at regular intervals of
time.
• DACR is loaded with B'01000000 on initialization, with b0 of

DASTCR being set to 1.
• A software timer (already created) is used to provide timing at regular
intervals of time.
• Load DADR0 with H'40 to H'FF in sequence, then back to H'40.
Repeat this sequence infinitely.

Chapter 11
Serial Interface (SCI)
The serial interface is a communication function having two types:

start-stop synchronization and clock synchronization. This chapter describes
the start-stop synchronization type, which has a wider range of applications.
Although a multiprocessor function is added to the H8/3048 serial interface,
this function is not explained here since it is specific to the series and not
provided for other processors.
The serial interface has more registers than peripheral functions
described earlier and the operation may seem more complex. You need to
completely understand the meaning of the settings regarding the contents of
each register.
Since the training board is connected to your PC through the serial
interface, you can use the PC as I/O equipment by developing a program to
send and receive characters using ASCII codes.
Note
The following register has negative logic bit names:
11.1 Serial Data Input/Output and Its Method
In a microcomputer-applied system, several bits of digital data are

sometimes input or output through time-division using one pin. These time-
divided bits of digital data are called "serial data" and the function for
inputting/outputting serial data is called the "serial port". Although the serial
port has a different name on some products, it is referred to as the "serial
communication interface" (hereinafter referred to as the "SCI") in the H8/3048.
Although data input/output using the serial port takes longer time than
that using the I/O port you learned about in Chapter 8, it uses fewer signal lines
for exchanging data with other parties (such as microcomputers, equipment and
devices).

Figure 11.1: Serial Data Input/Output
As such, the serial port is mostly used for input/output with more
distant parties, for which connection using a large number of signal lines is
unsuitable. Data input/output using the serial port is often referred to as
"communication", with input being referred to as "reception" and output
"transmission".
Serial data communication is conducted via the RS-232C and USB
(Universal Serial Bus) ports, used to connect PCs and peripherals, as well as
data communication using Ethernet or telephone lines.
Figure 11.2: Serial Data Formats

Start-stop synchronization communicates 7- or 8-bit data per operation
and the transmit pin outputs the high-level voltage while data are not
transmitted. When transmission is started, the start bit, one bit of the low-level
voltage, is output to notify the other party of the start of data transmission and
7- or 8-bit data are output. After that, the parity bit is output if an error is
detected. At the end of transmission, the stop bit, a high-level voltage, is
output, which consumes one or two bits.
As shown above, start-stop synchronization has several data formats.
There are two requirements to communicate through start-stop
synchronization: one is for the sender and receiver to use the same data format
and the other is for them to use the same transmission speed (also called "baud
rate", which refers to how many bits are communicated per second; the unit is
bit per second, or bps). Communication will fail unless these two are
predetermined between sender and receiver.
11.2 SCI Operation Overview
The H8/3048 has two SCI channels which can be set to either start-stop
synchronization or clock synchronization. Although the figure below shows a
block diagram of only one SCI channel, both have the same configuration and
use.
Figure 11.3: SCI Block Diagram
For transmission, the CPU writes the data to be transmitted in the

transmit data register (TDR). After that, the SCI moves the data from the TDR
to the transmit shift register (TSR), which outputs them from the transmit pin

(TxD) bit by bit in the set data format through some modification such as
adding the start or stop bit.
For reception, the data input in the receive pin (RxD) are stored in the
receive shift register (RSR) bit by bit through some modification such as
removing the start or stop bit. After that, the SCI moves the data from the RSR
to the received data register (RDR) when the stop bit arrives and the CPU reads
them using the MOV instruction.
In communication using the SCI, the data to be transmitted are written

in the TDR and the received data are read from the RDR. Although the TSR
and RSR exist inside the SCI, they are not assigned an address in the memory
since users need not operate them. The SCI has four more registers for
controlling other settings such as communication operation, which are
described in the following section.
11.3 SCI Registers
Table 11.1 shows the SCI register configuration. The following

explains how to transmit and receive serial data using the SCI in sequence
together with introduction of each register.
Table 11.1: SCI Register Configuration (for 2 Channels)
11.3.1 Communication Mode and Data Format Setting

The SCI is equipped with a serial mode register (SMR), which is
designed to set the communication mode and data format.
Figure 11.4: Serial Mode Register (SMR)

C/A The communication mode bit is designed to set use of start-stop or clock synchronization.
Bits 6 to 2 are effective only when this bit is set to 0.
CHR The character length bit is designed to set the data bit length.
PE The parity enable bit is designed to set use of parity bit or not.
O/E The parity mode bit is designed to set even or odd parity when the parity bit is set to be
used. If it is set not to be used, the setting of this bit is ineffective.
STOP The stop bit length bit is designed to set the stop bit length.
MP The description of the multiprocessor mode bit is omitted in this lesson.
CKS The lower 2 clock select bits are designed to select the clock to be used to generate the
baud rate among four using a combination of 1 and 0. The SCI communication speed is
determined by three factors, one of which is the clock select bits. How it is determined is
described in detail in the next section.
11.3.2 Setting of Communication Speed

Figure 11.5 shows the bit rate register (BRR), which is used to
determine the communication speed.
Figure 11.5: Bit Rate Register (BRR)
The SCI communication speed is determined by the following three

factors:
1. Clock select bits in the SMR (CKS1 and CKS0)
2. Value written in the BRR
3. Microcomputer operating frequency (same as the oscillating frequency
of the crystal oscillator externally connected to the microcomputer)
Table 11.2 shows how the communication speed is determined by these three
factors.
For example, to set the communication speed to 9600 bauds (the same unit as
bps) when the microcomputer operating frequency is 20MHz (same as when
the crystal XTAL is 20MHz), read the values of N and n from this table. N
refers to the value to be set in the BRR and n to the one to be set in the clock
select bits in the SMR. Since N = 64 and n = 0 at 9600 bauds, the clock select
bits (CKS1 and CKS0) are both 0. A communication speed of 9600 bauds can
be achieved by writing these values in each register.
Table 11.2: Sample Settings of BRR for Baud Rates (Start-stop

Synchronization)

11.3.3 Communication Procedure
Figure 11.6 shows the serial status register (SSR), which is an
important register for transmitting or receiving data.
Figure 11.6: Serial Status Register (SSR)
All of the upper 5 bits of this register serve as the status flag. If you are
not sure about the use, review how to use each flag. The lower 3 bits are not
described here since they are not used so often.
TDRE The transmit data register empty (TDRE) flag is used for transmitting data. Refer to
Figure 11.7 for the transmission procedure.
Before writing the data to be transmitted in the transmit data register (TDR), make sure
that the TDRE is set to 1. If it is still set to 0, you should not write data in the TDR yet.
If the TDRE is set to 1, write the data to be transmitted in the TDR, then be sure to clear
the TDRE to 0 using the BCLR instruction or by other means.
When the TDRE is cleared to 0, the SCI starts transmission. It automatically sets the
TDRE to 1 after completely moving the data from the TDR to the TSR. This is why you
should write data in the TDR after the TDRE has been set to 1.

RDRF The received data register full (RDRF) flag is used for receiving data. For the reception
procedure, also refer to Figure 11.7.
The SCI automatically sets the RDRF to 1 after completely moving the received data
from the RSR to the received data register (RDR). So, make sure that the RDRF is set to
1 before reading the received data from the RDR. If it is still set to 0, you should not read
the data yet.
If the RDRF is set to 1, read the received data from the RDR, then be sure to clear the
RDRF to 0 using the BCLR instruction or by other means.
After the RDRF is cleared to 0, the SCI is allowed to move the data received next from
the RSR to the RDR. If the next data is received before the RDRF is cleared to 0, the SCI
cannot move the received data from the RSR to the RDR, resulting in an overrun error
(described later). Accordingly, be sure to clear the RDRF to 0 after reading the received
data from the RDR.
Figure 11.7 shows the transmission and reception procedures described above
in the form of flowcharts.
Figure 11.7: Data Transmission/Reception Flowcharts
Receive error
The SSR has three error flags. Although no transmission errors occur
since data are unilaterally sent, errors sometimes occur during reception since
the receiver may fail to receive what the sender has transmitted. The three
types of errors all occur during reception.

Figure 11.8: Receive Error
11.3.4 Enabling/Disabling Communication or Interrupts

Figure 11.9 shows the serial control register (SCR), which is designed
to enable or disable transmission/reception or interrupts. The lower 4 bits are
not described here.
Figure 11.9: Serial Control Register (SCR)

TIE The transmit interrupt enable bit is designed to enable or disable the transmitted data empty
interrupt (TXI). When this bit is set to 1, the TXI interrupt is generated when the TDRE in the
SSR is set to 1 (when the system is ready to write the data to be transmitted to the TDR).
RIE The receive interrupt enable bit is designed to enable or disable the received data full interrupt
(RXI) and receive error interrupt (ERI). Although there are two types of reception-related
interrupts, RXI and ERI, you cannot enable or disable them separately. This bit is used to
collectively enable or disable both interrupts.
When this bit is set to 1, the RXI interrupt is generated when the RDRF in the SSR is set to 1
(when the system is ready to read the received data from the RDR).
The ERI interrupt is generated whenever any of the three flags in the SSR, namely, overrun
error (ORER), framing error (FER) and parity error (PER), is set to 1 (whenever a certain
receive error occurs).

TE The transmit enable (TE) and receive enable bits are designed to enable or disable SCI
and transmission and reception, respectively. Unless these bits are set to 1, no transmission or
RE reception is conducted. To initialize or change SCI settings such as communication mode, data
format and communication speed, on the other hand, they must be set to 0.
Now that descriptions of the SCI registers are completed, let's proceed to some
sample uses of the SCI.
11.4 Sample SCI Uses
This section introduces programs to transmit and receive one-character

data (8-bit data) written in ASCII code through start-stop synchronization using
the SCI0. The following specifications are assumed here, and hardware design
and register value settings are conducted accordingly.
• Data transfer mode and level Start-stop synchronization (RS-232C level)

• Data transfer speed 9600 bauds
• Data transfer format 8-bit data, 1 stop bit, and no parity bit
• Multiprocessor function Not used
• SCI clock Internal (the H8/3048 operates at 20MHz)
• Interrupts during data transfer Interrupts are used for reception
As for the hardware, the H8/3048 signal level (5V, 0V) must be
changed to the RS-232C level (±12V). For this purpose, an RS-232C line
driver/receiver IC as shown in Figure 11.10 is used.
Although an RS-232C device also has modem control signals in
addition to TxD and RxD pins, it is assumed that these signals be not used
since they are not supported by the H8/3048.
Figure 11.10: Hardware for Start-stop Synchronization Data Transfer

Using SCI0

11.4.1 SCI Initialization Program
Since programs using the SCI tend to be complicated, let's start by
taking a look at a program to conduct SCI initialization only. Each register of
the SCI0 to be used is set as follows by default:
Figure 11.11: SCI0 Register Default Settings
Now that the register default values are determined, the following
explains a sample program to initialize the registers.
This program is designed as a subroutine to be called from the main
routine. Since reception will fail if the reception-related status flags have been
set before each register is initialized or reception is started, clear the flags after
dummy-reading the SSR. They are not cleared unless zero is written after
reading. Dummy read refers to reading conducted only for satisfying this
condition even though flag values need not be checked.
If B'00000000 is written at this time, the TDRE is also cleared,
mistakenly transmitting data stored in the TDR, if any. To prevent this, write

B'10000000 so that the TDRE is not cleared (nothing happens by writing 1 in
the TDRE). The SSR need not be initialized if nothing is done after resetting.
C Language Sample
#include "iodefine.h"
void initSCI(void) ;
void initSCI(void)
{
int i ;
SCI0.SCR.BYTE = 0 ; /* stip SCI0 , use internal clock */

SCI0.SMR.BYTE = 0 ; /* asynchronouse mode,8 bit
data,1stop,no-parity,1/1 clock*/
SCI0.BRR = 64 ; /* 20MHz / 9600 / 32 -1 = 64 */
for(i=0;i<350;i--) ; /* wait 1bit time */
SCI0.SCR.BYTE = 0x30 ; /* transmit and receive are enable
*/
SCI0.SSR.BYTE &= 0x80 ; /* clear all receive flags */
}

After the SCI communication speed is set or changed, operation should
not be started immediately. You must wait for the time required for at least 1
bit to be communicated at the set speed. This is the time required for the SCI to
be initialized, hence the need to wait for the time required for 1 or more bits to
be communicated.
In the above program, this time is calculated from the execution state
counts for looping. Based on this calculation, 350 is input in the R0 general-
purpose register and decrementation by 1 is looped until it becomes 0. These
instructions have the following execution state counts:
MOV.W #350,R0 ; 4 states

WAIT_1BIT: DEC.W #1,R0 ; 2 states
BNE WAIT_1BIT ; 4 states
The execution state counts of the repetitive DEC.W and BNE

instructions are two and four states, respectively, amounting to 6 states. Since
the operating frequency is 20MHz, one state time is 50ns and 6 states required
for one loop is 300ns. Since the communication speed is set to 9600 bauds,
about 104 microseconds are required for communicating 1 bit. To calculate
how many loops take 104 microseconds, divide 104 microseconds by 300ns to
obtain 346.6. With some allowance, we use a value of 350 here.
As described above, wait for the time required for 1 bit to be
communicated at the set speed using looping or by other means after setting or
changing the SCI communication speed, rather than immediately starting
operation.
11.4.2 SCI Transmit/Receive Program

Interrupts are hardly used for transmission since it is mostly conducted
when the CPU is ready to send the data it has prepared. As for reception,
however, the receiver cannot tell when data is transmitted by the sender.
Testing the RDRF using an instruction and waiting until it is set to 1 wastes
time and prevents the CPU from executing other processing. To prevent this,
reception generally involves interrupts. Before using an interrupt, you must
store the vector in the corresponding vector address. There are two reception-
related interrupts as follows:
SCI0 receive error interrupt (ERI0) Vector address: H'0000D0 - H'0000D3

SCI0 received data full interrupt (RXI0) Vector address: H'0000D4 - H'0000D7
In addition, reception-related interrupts must be enabled beforehand.

The sample program shown below assumes that an LED is connected to
the least significant bit of port A (PA0) and is designed to invert the LED
on/off status per proper reception by the SCI0 but not invert it if an error
occurs on reception.
When reception is conducted properly, the data received through the
RXI interrupt routine (IN_1CHR) are sent back to the other party through the

send subroutine (OUT_1CHR) as they are (this is called "echo back"). If an
error occurs on reception, the error status flags are cleared though the ERI
receive interrupt routine (ERR_IN) and no echo back is conducted.
C Language Sample
#include <machine.h>
header file */
void initSCI(void) ;
{
initSCI() ;
PA.DDR = 0x01 ; /* PA0 output */
set_ccr(0) ; /* enable interrupt */
}
void initSCI(void)
{
int i ;
SCI0.SCR.BYTE = 0 ; /* stop SCI0,use internal clock */
SCI0.SMR.BYTE = 0 ; /* asynchronouse mode,8 bit
data,1stop,no-parity,1/1clock */
SCI0.BRR = 64 ; /**/
for(i=0;i<350;i++) ;
SCI0.SSR.BYTE &= 0x80 ; /* clear receive flags */
SCI0.SCR.BYTE = 0x70 ; /* enable receive
interrupt,transmit and receive enable */
}
// vector 52 ERI0
__interrupt(vect=52) void INT_ERI0(void)
{
SCI0.SSR.BYTE &= 0xc0 ; /* clear receive error flags */
}
// vector 53 RXI0
__interrupt(vect=53) void INT_RXI0(void)
{
SCI0.SSR.BIT.RDRF = 0 ; /* clear RDRF , stop interrupt
request */
PA.DR.BIT.B0 = ~PA.DR.BIT.B0 ; /* invert PA0 terminal */
}

1. What are the characteristics of serial data input/output compared with
that of parallel data?
Enter an appropriate word in parentheses.
Answer
It takes (longer) time for inputting/outputting the same bit count of data.
It uses (fewer) signal lines.
Refer to the comparison between the serial and I/O ports described in 11.1
2. What are the requirements for communication through start-stop

synchronization?
Answer
The sender and receiver must use the same (data format) and (communication
speed).
Otherwise, an error occurs on reception and communication fails.
3. The following describes the transmission procedure using the SCI.

Answer
Check that the (TDRE) flag in the (SSR) is set to 1, and if not, wait until it
becomes 1. If it is set to 1, write the data to be transmitted in the (TDR) and
then set the (TDRE) flag to (0).
Refer to "Figure 11.7: Data Transmission/Reception Flowcharts" in 11.3.3.
4. The following describes how an overrun error occurs.

Answer
It occurs when the next data is received with the (RDRF) flag in the (SSR) set
to (1).
Listen to the explanation provided in "Figure 11.8: Receive Error" in 11.3.3.
5. What are the three factors which determine the SCI communication
speed?
Answer
(CKS1 and CKS0 (clock select bits) in the SMR)
(Value in the BRR)
(Crystal oscillating frequency )
Refer to 11.3.2.

< SCI >
Write a program to use SCI converter as you have learned in Chapter

11 and run it on the training board. Work out through the following steps:
When the training board is used, SCI channel 1 is connected to a PC by
an RS-232C interface as shown below to carry out debugging using a monitor
program and HTERM software. In this setup, characters (ASCII code) can be
transferred between the PC and SCI channel 1.
Type one digit between 1 and 9 on the PC and A through Z will be

printed as many lines as specified by the input digit. For example, if 3 is typed,
three lines of A through Z will be printed. The execution result will appear as
shown below.
3
ABCDEFGHIJKLMNOPQRSTUVWXYZ
Execute this sequence repeatedly.

It is assumed that SCI channel 1 is initialized for 8-bit data, one stop
bit, no parity, no interrupt, and a transfer speed of 9600 bps. No error check is
made on received data.
As a character is received, it is sent back, or echoed back, to the PC.
Without echo-back, nothing would appear on the screen if you type any
character on the keyboard.
When an ASCII code is received, it is converted to a binary number
with its higher-order four bits being zeroed, for use as a counter. A CR
(Carriage Return) code and a LF (Line Feed) code are transmitted to effect a
line feed after each line of data has printed. The CR and LF are represented by
H'0D and H'0A, respectively. When a CR is transmitted, the cursor moves to
the leftmost end of the current line; when an LF is transmitted, the cursor

moves down one line. Accordingly, if a CR and an LF are transmitted in
succession, the cursor moves to the beginning of the next line.
Write a subroutine that prints A through Z.

Write a subroutine that receives one character at a time. The subroutine makes
no error check on received characters. As a character code is received, it is
stored in ROL and returned.
• Since ASCII code "A" is represented by H'41, "B" by H'42, and "C" by
H'5A, transmit from H'41 to H'5A in sequence to print characters A
through Z.

Chapter 12
Timers
Timers are always used for microcomputer-based control. Since the

interrupt function is almost always used as well, review exception handling
described in Chapter 7.
Although the H8/3048 timers have many channels and various uses
are enabled by combining them, this chapter focuses on simple applications
only.
12.1 General Timer Overview
Most microcomputer-applied systems require time management.

Timers are used in the following cases:
To execute a program after a certain period of time or at a certain
interval.
To make an external pin output pulses after a certain period of time or
at a certain interval to control operation of externally connected equipment.
To measure the high- and low-level periods of pulses input from externally
connected equipment to a pin to check and control the equipment status.
Although timer functions differ between products and most single-chip
microcomputers have several types of timers incorporated in one
microcomputer, timers generally have the following structure and functions:
Timer basic structure and interrupt request generation by compare match

The central component of the timer is a counter called a "timer
counter". Although the bit count of the counters differs between products, 8- or
16-bit counters are the mainstream. The counter is designed to count
microcomputer internal clocks or clocks input from an external input pin. By
counting clocks having known periods, you can determine the elapsed time
based on the count. The timer also has a register often called a "compare
register", which has the same bit count as the timer counter. In this register,
you can write any numeric data using an instruction. The value in the compare
register is always compared with the timer count by a comparator, and an event
in which both values match is referred to as a "compare match". By using this
function, you can generate a compare match when the time obtained by
multiplying the clock period counted by the timer counter by the value in the
compare register has elapsed. In every timer, a compare match generates an
interrupt request. You can manage the time of processing as necessary by

writing a desired value in the compare register to generate an interrupt after the
set time has elapsed.
Figure 12.1: Sample Configuration of Timer Having Output Compare and

Input Capture Functions
Interval timer
Specific interrupt handling can be triggered at a certain interval. A
timer used in this way is specifically referred to as an "interval timer".
Output compare function

Some timers are capable of outputting the high- or low-level voltage
according to the setting from a dedicated output pin when a compare match
occurs. This function is called the "output compare function" or "pulse output
function" of the timer. By using a timer with this function, you can output
pulses having a desired high- or low-level period.
Input capture function

Some timers also have a register often called an "input capture
register", which has the same bit count as the timer counter. This register is
designed to capture the timer counter value when the leading or trailing edge is
input to a dedicated input pin. This is called the "input capture function" of the
timer. By using a timer with this function, you can measure the high- or low-
level period of input pulses.
Some timers also have more complicated functions. As described

above, timers have various functions and which are provided depends on each

timer. Except for special dedicated ones, most timers have a function to
generate interrupt requests using compare matches.
12.2 ITU Configuration
Of the several types of timers incorporated into the H8/3048, this

section examines the ITU (Integrated Timer Unit).
The ITU has five channels from 0 to 4. Each channel can be used as an
independent timer since it is equipped with registers, pulse output/input pins
and external clock input pins corresponding to the timer counter, compare
register and input capture register. You can also interlock multiple channels.
Each channel has almost the same configuration. Figure 12.2 shows the
channel 0 block diagram.
Figure 12.2: ITU Channel 0 Block Diagram
Since each channel has almost the same structure and use, let's take
channel 0 as an example. Table 12.1 shows registers relating to channel 0. The
"0" suffix represents registers dedicated for channel 0 and other channels also
have the same types of registers. The timer counter 0 (TCNT0) is a 16-bit, up
counter. There are two general registers 0, A and B (GRA0 and GRB0), which
are available as either a compare or input capture register. Since these three 16-
bit registers are located at even-numbered addresses in the memory, they are
read and written in word-size units.
Table 12.1: ITU Channel 0 Register Configuration

Registers not described here are described in the following sections.
Table 12.2 shows the external pins relating to ITU channel 0. There are two
TIOC0 pins, A and B, which are used as either pulse output or input pins
according to the setting for the uses of the GRA0 and GRB0, either a compare
or input capture register.
Table 12.2: ITU Channel 0 Pin Configuration
12.3 ITU Registers
This section examines ITU channel 0-related registers not described in

the previous section. Figure 12.3 shows the timer start register (TSTR), which
is not dedicated for channel 0 but commonly used by all channels. This register
is designed to start or stop counting by the timer counter of each channel.
Figure 12.3: Timer Start Register (TSTR)
For channel 0, bit 0 or counter start 0 (STR0) is used and counting is

stopped when the STR0 is set at 0 or started when 1. While counting is
stopped, no compare match is generated since the TCNT0 is not counted up, no
interrupt is generated even if it is enabled, and no pulse is output even if pulse
output is enabled.

12.3.1 Timer Control Register 0 (TCR0)
Figure 12.4 shows the timer control register 0 (TCR0), which is
designed to set the counting mode for the TCNT0.
Figure 12.4: Timer Control Register (TCR0)
The timer prescaler bits (TPSC2 to TPSC0) are used to select the clock
to be counted. The internal clock can be selected from the system clock φ and
the clocks having periods that are twice, four times and eight times as long, and
the external clock from four external clock input pins from TCLKA to
TCLKD.
The clock edge bits (CKEG1 and CKEG0) are used to select the clock
edge for counting up when an external clock is selected. If you set to count a
clock at both edges, the count is incremented by 2 per clock input.
The counter clear bits (CCLR1 and CCLR0) are used to set the timing
for clearing the TCNT0 count value. If they are set at 00, the TCNT0 is not
cleared but continues counting up permanently. When the count value reaches
H'FFFF, however, it automatically returns to H'0000. If they are set at 01 or 10,
the TCNT0 is cleared when a compare match or input capture is generated by
the GRA0 or GRB0. This setting is convenient for generating compare matches
at a certain interval, in other words, for enabling the interval timer, since a
value once input to the GRA0 or GRB0 need not be rewritten every time a
compare match is generated.
Note the following precaution if you set to clear the TCNT0 when a
compare match is generated. The TCNT0 count value is not cleared
immediately after it reaches the GRA0 or GRB0 value. Instead, it is cleared
when the next clock is input or when the counter is counted up next after both
values match. Setting of "11" represents synchronous clearing. This lesson,
however, omits descriptions of complicated functions such as interlocking of
multiple ITU channels.
12.3.2 Timer I/O Control Register 0 (TIOR0)

Figure 12.5 shows the timer I/O control register 0 (TIOR0), which is
designed to set the uses of the GRA0 and GRB0 as well as those of the
corresponding TIOCA0 and TIOCB0 external pins.

Figure 12.5: Timer I/O Control Register 0 (TIOR0)
The I/O control bits A2 to A0 (IOA2 to IOA0) are used to set the uses
of the GRA0 and TIOCA0 pins, and the I/O control bits B2 to B0 (IOB2 to
IOB0) to set the uses of the GRB0 and TIOCB0 pins. Since they are set in the
same way, the following explains how to set the lower 3 bits only.
If they are set at 000, the GRA0 is used as an output compare register,
which, however, does not output pulses. This setting is used for the interval
timer. If they are set at 001, the low-level voltage is output by the TIOCA0 pin
when a compare match occurs. If they are set at 010, the high-level voltage is
output. If they are set at 011, toggle is output by the TIOCA0 pin when a
compare match occurs. Toggle output refers to outputting by inverting the
current high/low level.
If they are set at 100, the GRA0 is used as an input capture register and
input is captured when the leading edge is input to the TIOCA0 pin. If they are
set at 101, input is captured when the trailing edge is input to the TIOCA0 pin.
Settings 110 and 111 are the same and input is captured at both leading and
trailing edges.
12.3.3 Timer Status Register 0 (TSR0)

Figure 12.6 shows the timer status register (TSR0), which is designed
to collect status flags for notifying compare match or input capture generation.
Figure 12.6: Timer Status Register 0 (TSR0)
The input capture/compare match flag A (IMFA) is set at 1 when an

input capture or compare match occurs in the GRA0.
The input capture/compare match flag B (IMFB) is set at 1 when an
input capture or compare match occurs in the GRB0. The overflow flag (OVF)
is set at 1 when the TCNT0 value is changed from H'FFFF to H'0000.
12.3.4 Timer Interrupt Enable Register 0 (TIER0)

Figure 12.7 shows the timer interrupt enable register 0 (TIER0), which
disables or enables interrupt requests corresponding to each status flag of the
TSR0.

Figure 12.7: Timer Interrupt Enable Register 0 (TIER0)
This register is designed to enable or disable requests for three types of

interrupts which can be generated from ITU channel 0, namely, IMIA0, IMIB0
and OVI0 interrupts.
For example, if you want to trigger an IMIA0 interrupt request when
the IMFA flag of the TSR0 is set at 1, set bit 0 of this register (input
capture/compare match interrupt enable A, or IMIEA) at 1. Likewise, the input
capture/compare match interrupt enable B (IMIEB) and overflow interrupt
enable (OVIE) correspond to the IMFB and OVF of the TSR0 and are designed
to enable or disable IMIB0 or OVI0 interrupts, respectively.
12.4 Sample Use as Interval Timer
Let's consider an example to turn an LED on at a 25ms interval using

ITU channel 0. Here, we write 0 to unused bits of each register.
The H8/3048 is assumed to operate at 20MHz.
- TCR0 setting
For ITU operation, the internal clock φ (phi)/8 is used to set the GRA0
to 25ms and the TCNT0 is used for counting. A compare match occurs every
25ms to clear the TCNT0 and start next counting operation.
To enable this, the TCR0 is set as follows. Setting the φ/8 clock enables 25ms
setting using 16 bits of the GRA.
- GRA0 setting
If the φ/8 clock source is selected when the CPU clock is set at 20MHz,
one count is equal to 0.5 microsecond. Since 25ms (25000 microseconds) are
equal to 62500 counts, set GRA0 to 62499 (62500 - 1).
The reason why one is subtracted is that it takes one-clock time after a
compare match occurs until the TCNT0 is cleared.
- TIOR0 setting
Since output pins are not used, the TIOR0 is set as follows:
- TIER0 setting
As for interrupts, only the IMIA0 is used.
- TSTR setting
Start channel 0 after all settings are completed.
C Language Sample
#include <machine.h>
header file */
void initITU(void) ;
{
initITU() ;
PA.DDR = 0x01 ; /* PA0 output */
set_ccr(0) ; /* enable interrupt */
}
void initITU(void)
{
ITU0.TCR.BYTE = 0x23 ; /* counter clear GRA,1/8 clock */
ITU0.TIER.BIT.IMIEA = 1 ; /* enable IMIA interrupt */
ITU0.GRA = 62500-1 ; /* 20MHz/40Hz(25ms)/8 = 62500 */
ITU.TSTR.BIT.STR0 = 1 ; /* start ITU0 */
}
// vector 24 IMIA0
__interrupt(vect=24) void INT_IMIA0(void)
{
ITU0.TSR.BIT.IMFA = 0 ; /* clear IMFA , stop interrupt
request */
PA.DR.BIT.B0 = ~PA.DR.BIT.B0 ; /* inverse PA0 terminal */
}

This concludes the description of a sample program using timers.

1. What are the following functions provided for the ITU called? Enter an
appropriate word in parentheses.
Answer
To trigger specific interrupt handling at a certain interval. ¼(Interval timer)
function
To output the high/low-level voltage from an external pin after a certain period
of time.¼(Output compare) function
To capture the timer counter value when the leading/trailing edge is input in an
external pin to another register. ¼(Input capture) function
Refer to 12.1 to understand the general timer overview.
2. The following describes the compare match function of the ITU. Enter
an appropriate word in parentheses.
Answer
In ITU channel 0, a compare match is generated by the GRA0 when the time
obtained by multiplying the (period) of pulses counted by the (TCNT0) by the
value in the GRA0 has elapsed.
Refer to 12.1 and 12.2 to understand how a compare match is generated.
3. The following describes the functions available when a compare match

is generated by the GRB0 of ITU channel 0. Enter an appropriate word in
parentheses.
Answer
The (IMIB0) interrupt can be generated.
The (high/low-level voltage) can be output from the (TIOCB0) external pin.
Listen to the explanation provided in "Figure 12.2: ITU Channel 0 Block
Diagram" in 12.2 to understand how channel 0 generates two compare
matches, A and B.
4. You want to generate an interrupt using the GRA0 of ITU channel 0 but
without outputting pulses when a compare match occurs. How do you set
the TIOR0 and TIER0?
Answer
Write (000) to the 3 bits from (I/O control bits A2 to A0 (bit 2 to bit 0)) of the
TIOR0.
Write (1) to the (IMIEA) bit of the TIER0.
Refer to 12.3.2 and 12.3.4 to understand how the TIOR0 and TIER0 are used.
5. What happens if a compare match occurs using the GRB0 of ITU

channel 0?
Answer
The (IMFB) in the (TSR0) is set at 1.
Refer to 12.3.3 to understand how the TSR0 is used.
6. What happens if the TSTR of the ITU is set to stop counting by the
timer counter? Select the one you think is appropriate in parentheses.
Answer
A compare match (does not occur) when the set time has elapsed.
An interrupt is (not generated) when the set time has elapsed (even) if enabled.
Pulses are (not output) when the set time has elapsed (even) if enabled.
Refer to 12.3 to understand what happens when counting by the timer counter
is stopped.
<Timer 1>
Write a program to use ITU as you have learned in Chapter 12 and run
it on the training board. Work out through the following steps:
Use timer channel 0 to create a time interval of 1 second and let the 8-bit
LEDs at address H'FFFF12 increment at 1-second intervals.
Timer channel 0 must be a 20 ms interval timer.
• Use the internal clock divided by eight as a timer counter clock. (The
CPU clock is 20 MHz.)
• A compare match with GRA0 clears the timer counter.
• Use an interrupt that is raised by a compare match with GRA0.
• The LEDs increment each time a 20 ms interrupt routine has run 50
times.
Write an initialization subroutine.

Fill out the blanks in the interrupt routine.
(Initialization)
• TCR0: Configure to clear the timer counter on compare match with
GRA0 and to use the internal clock divided by eight.

• TIOR0: Configure to inhibit pulse output on compare match with
GRA0.
• TIER0: Request an interrupt on compare match with GRA0.
• GRA0: Set (20 ms/0.4 µs) - 1.
(Interrupt routine)
Create an interrupt routine that reads and increments work area
LED_DATA each time it has run 50 times, and then that inverts and outputs
the data to the LEDs.
The purpose of this inversion is to turn off the LEDs upon '1' output
and turn them on upon '0' output.
Reset R0L to 50 when it has decremented to equal 0.

<Timer 2>
Write a program to use ITU as you have learned in Chapter 12 and run
it on the training board. Work out through the following steps:
A piezoelectric buzzer is connected to the TIOCA0 pin of the board.
Configure the program to beep by generating 500 Hz pulses while SW28 is
pressed.
• 500 Hz pulses are a signal in which a low and a high toggle at 1 ms
intervals.
• SW28 is connected to PB7 (port B bit 7). Press it to input a low-level
voltage to PB7; release it to input a high-level voltage to PB7.
• Timer channel 0 generates a compare match with GRA0 at 1 ms
intervals, with resultant pulse output from the TIOCA0 pin through
toggle action.
Write an initialization subroutine.
• No interrupt is used.

• Load GRA0 with a value needed to create a time interval of 1 second.
• A compare match with GRA0 clears the timer counter.
• Configure the subroutine to provide toggle output from GRA0.
• The timer is not started in the course of initialization.

Chapter 13
Expanding Memory and I/O
Since the H8/3048 has a 128kbyte internal ROM and an 8kbyte

internal RAM, it can accommodate a relatively large program without
externally expanding the memory. If the internal memory is insufficient,
however, you can externally expand it, which is essential for hardware design
engineers to know. Although software engineers can still develop programs
without this knowledge, they are also expected to understand some of the basic
techniques.
Although the H8/3048 can accommodate a dynamic RAM, this
chapter focuses on the basic functions and describes the ROM and static RAM.
In this chapter, you learn about which signals are required for expanding the
memory, how they change at reading/writing and how to calculate if the CPU
and memory speed match. This chapter also helps you understand memory
signals and timings.
Note: The following are negative logic signals:
Although the H8/3048 has an internal ROM and RAM, external memory
expansion may be required due to insufficient capacity. The following
describes how to connect the memory and CPU and match their speeds using
EPROM and SRAM as examples.
13.1 H8/3048 Operating Mode
When expanding the H8/3048 memory, you can determine how much
memory capacity to be added and how to use the data bus. The mode set pins
(MD0, MD1 and MD2) are used to select one of seven operating modes, which
determine the uses of the address bus, data bus and read/write signals.
Table 13.1 shows each mode:
* Status at resetting. It is available as either an 8- or 16-bit bus according

to the setting.
Since mode 7 represents single-chip mode, no external memory can be added.

Table 13.1: H8/3048 Operating Mode
The internal ROM and RAM are always connected to the CPU through
the 16-bit data bus irrespective of the mode setting. "Disabled" in the "Internal
ROM" column means that the internal ROM, though it exists, is disabled by
being disconnected from the CPU. In this case, an external ROM must be
connected. When the internal ROM and RAM are enabled, no external memory
can be added to the same address. If the same address is used, the internal
memory has priority, disabling reading/writing from/to the externally
connected memory.
13.2 Pins for Memory Connection
Table 13.2 shows the pins relating to memory connection provided for
the H8/3048 and their functions.
Connected memory size

Since there are 24 address buses (A0 to A23), up to 16Mbytes of
memory can be connected. If the memory to be connected is 1Mbyte or
smaller, only 20 address buses (A0 to A19) are required and the remaining 4
pins can be used for other purposes.
Data bus width

Since the H8/300H is a 16-bit CPU, it has 16 pins (D0 to D15) for
reading and writing 16-bit data. If word data is allowed to be divided into two
by the MOV.W instruction, only 8 data bus pins (D8 to D15) are required and
the remaining 8 pins (D0 to D7) can be used for other purposes.
As described above, the use of pins determines whether the memory
address is 16M or 1M and the data bus is either 16 or 8 bits. So you have to
figure out the most effective use with the limited number of pins.

Table 13.2: Pins Relating to Memory Connection
Address strobe
Indicates that an address is valid and that it is external when it is at low
level. It is not set at low level if an address is internal (internal ROM or RAM).
When the CPU is reading or writing data from/to the internal ROM or RAM,
reading/writing is not available externally. The RD, HWR and LWR signals
are not changed to low level, either.
Read/write signals
When the data bus width is 8 bits (RD and HWR are used):
Data buses D8 to D15 are used, and D0 to D7 are not.

When the data bus width is 16 bits (RD, HWR and LWR are used):
The RD signal is used as the read signal for both 8- and 16-bit widths,
the HWR signal is used for writing to an even-numbered address, and the LWR
signal is used for writing to an odd-numbered address. During 16-bit data
writing, both the HWR and LWR signals are output. For details, refer to the
section describing connection between the CPU and memory.
13.3 Read Timing from External Memory
Figure 13.1 shows the read timing from an external memory. This is an
example for 24-bit address and 16-bit data buses. Reading is completed in a 3-
system clock time (3-state access).
To read data or instructions from the memory, the setup time and hold time of
the read data must be satisfied.

Figure 13.1: Read Timing from External Memory
13.4 Write Timing to External Memory
Figure 13.2 shows the write timing to an external memory. This is an

example for 24-bit address and 16-bit data buses.
Writing is completed in a 3-system clock time (3-state access).
Figure 13.2: Write Timing to External Memory

Figure 13.3 shows the read/write timings including waits. If the WAIT
input is at low level at the trailing edge of T2, the CPU inserts a wait state to
slow reading/writing. When the WAIT input is returned to high level,
reading/writing is completed.
Depending on the address output by the CPU, users have to design
circuits to input WAIT signals if the memory connected to the address is slow,
or to prevent WAIT signals from being input if it is fast.
The H8/3048 is provided with a wait state controller so that the wait state can
be input without creating such circuits.
Figure 13.3: Read/Write Timings Including Waits
Since the H8/3048 has an internal wait controller, waits can be inserted
in various ways.
Wait state controller enable register (WCER)

Determines for which area the wait state controller is enabled from area
0 to area 7.
WCER H'FFFFEF address

Figure 13.4: Wait State Controller Enable Register (WCER)
The wait state controller is enabled for the area with "1" written and
disabled for that with "0". By default, it is enabled for all areas.
Wait control register

Determines how to insert waits for the wait-enabled area.
WCR H'FFFFEE address
Figure 13.5: Wait Control Register (WCR)
Wait mode select 1 and01 (WMS1 and WMS0)
Programmable wait mode

Without using the WAIT pin, forcibly inserts the wait set by the wait
count.
Pin wait mode 1

Waits for the wait cycle specified by the program and inserts an
additional wait depending on the WAIT pin status (Figure 13.3).
Pin auto wait mode

The WAIT signal input to the WAIT pin only determines whether to
insert a wait state or not, and how many states to be inserted is determined by
the wait count. Wait is inserted as necessary.
Wait count 1 and01 (WC1 and WC0)

This determines how many wait states to be inserted in a programmable
wait or pin auto wait mode.
By default, the wait controller is enabled for all areas and three states
are set to be inserted in programmable wait mode. In other words, three wait
states are forcibly inserted in all areas. Change the setting as soon as possible
after resetting if necessary.
13.5 Sample Memory (EPROM)
The HN27C4001G is used here as an EPROM example.

The HN27C4001G has a 4Mbit capacity and 524288 word × 8 bit
configuration. Figure 13.6 shows the pin assignment.
Figure 13.6: NH27C4001G Pin Assignment Diagram
There are 19 address input pins, A0 to A18.Since addresses are input in

19-bit units, this memory has 512-kbyte (to be more precise, 524,288)
addresses. The address count of the memory IC is determined by the address
pin count.
There are 8 data pins, I/O0 to I/O7, meaning that the memory uses 8
bits per address. Since this is a ROM, it is a read only memory when connected
to a CPU and the data pins are set to output. They are changed to input pins for
writing by an EPROM writer. Here, we consider the case in which it is
connected to a CPU and serves as a ROM only.
The Vpp pin is designed to apply the write voltage (12V) for writing by
an EPROM writer. It is fixed to high or low level for operation as a ROM with
connection to a CPU.

CE (Chip Enable) is a memory select signal and the memory is selected
when it is set at low level. This is used to assign a specific address by adding
an address-decoded signal.
OE (Output Enable) is an output enable signal and read data is output
from a data pin when it is set at low level.
The table below summarizes this.
In read mode, the CPU reads data from the EPROM and sets both CE
and OE at low level.
In output disable mode, the memory is selected but read data is not
output to an I/O pin. The I/O pin is set in high impedance mode (disconnected
state).
In standby mode, the memory is not selected. When CE is set at high
level, the system is set in standby mode irrespective of the OE setting. Since
the memory IC is not operating in this mode, power consumption is low.
Table 13.3 shows the HN27C4001G read timing. There are 100ns and
120ns types.
Table 13.3: HN27C4001G Read Timing
Read timing waveform

Figure 13.7 shows the HN27C4001G read timing.
Read data is output from an I/O pin when the access time (tACC), CE output
delay time (tCE) and OE output delay time (tOE) are satisfied.

Figure 13.7: Read Timing Waveform
13.6 Sample Memory (SRAM)
The HM628512BI is used here as a static RAM example. It has a 4Mbit

memory capacity and 524288 word × 8 bit configuration. Figure 13.8 shows
the pin assignment.
Figure 13.8: HN628512BI Pin Assignment
There are 19 address pins, using 512 kbytes, and 8 data pins, using 8
bits per address.

CS (Chip Select) is a memory select signal and is the same as CE of the
EPROM. The memory is selected when it is set at low level. This is used to
assign a specific address by adding an address-decoded signal.
OE (Output Enable) is an output enable signal and read data is output
from a data pin when it is set at low level. The function and name are the same
as for OE of the EPROM.
Writing is enabled when WE (Write Enable) is set at low level. Table
13.4 summarizes this.
Table 13.4: HM628512BI Modes
In read mode, the CPU reads data from the SRAM and sets both CS and
OE at low level.
In output disable mode, the memory is selected but read data is not
output to an I/O pin. The I/O pin is set in high impedance mode (disconnected
state).
Write operation takes two forms. When CS is set at low to set WE at
low, OE is capable of writing at either high or low. Writing with OE set at high
is called the "OE clock" mode since it is set at low for reading and high for
writing. Writing with OE set at low, on the other hand, is called the "OE low
fixed" mode since it is set at low for both reading and writing. Writing is
generally conducted in OE clock mode.
In non-selection mode, the memory is not selected. When CS is set at
high, the system is set in non-selection mode irrespective of the OE or WE
setting. Since the memory IC is not operating in this mode, power consumption
is low.
Table 13.5 shows the HM628512BI read cycle. There are 70ns and 80ns types.
Table 13.5: HM628512BI Read Cycle

Read cycle timing
Figure 13.7 shows the read timing waveform. Read data is output to an
I/O pin when the address access time (tAA), chip select access time (tCO) and
output enable access time (tOE) are satisfied.
Figure 13.9: Read Timing Waveform
Table 13.6 shows the HM628512BI write cycle.

Table 13.6: HM628512BI Write Cycle
Figure 13.10 shows the write cycle waveform of the OE clock.

The important parameters for the write timing are input data set time
(tDW) and input data hold time (tDH).
Writing is conducted at either the CS or WE leading edge, whichever is
earlier. The input data set time (tDW) and input data hold time (tDH) must be
satisfied for this write timing.

Figure 13.10: Write Cycle Waveform (OE Clock)
13.7 Connecting CPU to Memory (Connecting EPROM Using 8-bit

Data Bus)
The following conditions are assumed here for connecting a CPU to a

memory:
CPU: H8/3048F (clock frequency: 10MHz)
16Mbyte memory space (24 address pins)
Internal ROM disabled (internal ROM is not used but an
EPROM is connected externally)
8-bit data bus (D8 to D15 used)
RD, HWR and CS0 to CS7 are used as control signals
Memory: HN27C4001G-10 for EPROM (access time: 100ns)
HM628512BI-8 for SRAM (access time: 85ns)
First, let's consider how to connect a CPU to a memory using an 8-bit data bus.
Address assignment
What should be determined first is to which addresses the memory is to
be connected.
As described in "Exception Handling", a program operating based on
resetting and the reset vector must be located in a ROM. Since the reset vector
is between H'000000 and H'00003, a ROM must be connected to starting from
the H'000000 address if only one ROM is connected.
In internal ROM enable mode, the internal ROM addresses are from
H'000000 to H'01FFFF. In internal ROM disable mode, the HN27C4001G

must be connected between H'000000 and H'01FFFF. The internal ROM is
assumed to be disabled here.
Generally, a memory is assigned to one of the spaces obtained by
equally dividing the CPU memory space by the memory capacity. Since the
CPU memory space is 16Mbytes and the EPROM capacity is 512kbytes, the
CPU memory space is divided into 32 equal parts. The smallest addresses are
from H'000000 to H'07FFFF. This is shown in Figure 13.11.
Figure 13.11: Address Assignment
Next, let's develop an address decode circuit. The EPROM should be

designed to operate only when the address output by the CPU is the EPROM
address (from H'000000 to H'07FFFF) and operation is enabled only when the
CE pin of the EPROM is set at low level. The address decode circuit is
designed to set CE at low level when the address output by the CPU is the
EPROM address.
Then, how can you determine that the address output by the CPU is the
EPROM address? The EPROM address is represented as follows in binary
notation:
H'000000: 0000 0000 0000 0000 0000 0000

H'07FFFF: 0000 0111 1111 1111 1111 1111
Accordingly, you can determine that it is the EPROM address when the
upper 5 bits (A23 to A19) of the address are all 0. On the other hand, you can
determine that the address of the address bus is valid when AS is set at low
level. As a result, CE of the EPROM is set at low level under the following
conditions:
AS is at low level and A23 to A19 are also at low level
Figure 13.12 shows a sample circuit to satisfy them.

Figure 13.12: Address Decode Circuit
The more memories that are connected, the harder it is to develop

decoders as shown above for each memory. By using the HD74AC138, a
standard logic IC, you can develop select signals for 8 memories. Figure 13.11
shows the HD74AC138 pin assignment and truth values are shown in Table
13.7.
Figure 13.13: HD74AC138 Pin Assignment

Table 13.7: HD74AC138 Truth Value Table
Table 13.8 shows the AC characteristics.

Table 13.8: AC Characteristics of HD74AC138
A decode circuit using the HD74AC138 is shown in Figure 13.14.
Figure 13.14: Decode Circuit Using HD74AC138
Figure 13.15 shows connection between H8/3048 and HN27C4001G.

Figure 13.15: Connection Between CPU and EPROM
The memory address pins are connected to the corresponding address

pins of the CPU (A0 to A0, A1 to A1, etc.) from A0 to A18.
The memory data pins are connected to the corresponding data pins of
the CPU (I/O0 to D8, I/O1 to D9, etc.) from I/O0 to I/O7, to D8 to D15.
Address-decoded signals are input to the memory CE pin.
RD signals of the CPU are input to the memory OE pin. When the CPU
is in read mode, the RD signal and OE are set at low and reading starts.
This completes logical connection between the CPU and the memory.
Next, it must be calculated whether the speeds of the CPU and the memory
match. Since an EPROM is connected, the CPU read timings are calculated
here.
Figure 13.16 shows CPU timings required for calculation.

Figure 13.16: CPU Read Timings
The most important parameters in CPU read timings are read data setup
and hold times.
Setup time calculation

A setup time of 20ns is required for the trailing edge of T3.
The time from start of reading to the trailing edge of T3 is obtained as
follows by subtracting the clock trailing time (10ns) from 2.5 clocks (250ns):
Time to trailing edge of T3 = 250ns − 10ns

= 240ns
Since 20ns (min.) is required as the setup time, this requirement is

satisfied if data arrive at the CPU 220ns after the start of reading. This is shown
in Figure 13.17.

Figure 13.17: Setup Time Calculation (1)
Data are output from the memory only when all the access time, OE
output delay time and CE output delay time requirements are satisfied.
Address delay time + Access time = 30ns + 100ns (max.)
= 130ns (max.) ...............
Refer to Figure 13.18
Time until the read signal is output + OE output delay time

= 50ns + 30ns (max.) + 60ns (max.)
= 140ns (max.) ............... Refer to Figure 13.19

Time until the address strobe is output + Decoder delay time + CE output delay
time
= 50ns + 30ns (max.) + 10.5ns (max.) + 100ns (max.)
= 190.5ns (max.) ............... Refer to Figure 13.20
The longest time for data to be output is 190.5ns due to the CE output
delay time. As for the setup time, it causes no problem since the calculation
results are 190.5ns (max.) against the requirement of 240ns (max.), providing
an allowance of about 50ns.
Hold time calculation

The input data hold time required by the H8/3048F is 0ns (min.) for the
address strobe leading edge. In other words, it is acceptable as long as data are
not changed before the address strobe leading edge. The following three factors
change data in the memory:
- An address is changed
- CE is set at high level
- OE is set at high level

An address is changed after the address hold time has passed following
the address strobe leading edge. As a result, the hold time of 0ns (min.) is
secured.
On the other hand, CE is set at high level after the decoder delay time
has passed following the address strobe leading edge. As a result, the hold time
of 0ns (min.) is also secured.
As for OE, RD is used as it is. RD is set at high level at the same time
AS is set at high level. The memory outputs data for 0ns (min.) after OE is set
at high level. As described above, the hold time of 0ns (min.) is satisfied in all
cases.
Consequently, you can see that the requirements for both setup and hold
times are satisfied regarding EPROM reading.
This method has a wide range of uses and can be applied to various
connections between the CPU and the memory. The setup time required by the
CPU, however, may not be satisfied if the address decoder delay time is long.
In addition, the address strobe (AS) is used in the address decode circuit and
delayed AS tightens the requirement for the setup time.
To simplify a decode circuit, the H8/3048 is provided with signals from
CS0 to CS7. These signals are obtained by decoding the upper 3 bits of the
CPU addresses. Since 3 bits are decoded, the 16Mbyte memory space is
divided into 8 equal parts. These are called area 0 to area 7. When the CPU
accesses area 0, CS0 is set at low level. This is shown in Table 13.9.
Table 13.9: Address Decoding Using Chip Select Signals
In the case of the H8/3048, the CS0 to CS7 signals are available instead
of the AS signals. In this case, 3 bits of addresses need not be decoded. In
addition, the CS0 to CS7 signals are output faster than the AS signals and at the
same timing as address signals, allowing for setup time and enabling slower
memory to be connected.
In order to use the CS0 to CS7 signals, you must set the bus controller
accordingly.
Since CS0 to CS3 are commonly used with port 8, set the
corresponding bit of the P8DDR at 1 (output).

Figure 13.21: Port 8 Data Direction Register (P8DDR)
CS0, CS1, CS2 and CS3 correspond to P84DDR, P83DDR, P82DDR

and P81DDR, respectively, and are switched to chip select pins when 1 is
written. In internal ROM disable mode, however, the CS0 pin is set at 1 and
enabled by default.
The data direction register is a write-only register and thus incapable of
reading. This means that the bit handling instruction is not available for it. CS0
to CS3 can be used as chip select signals simply by setting the P8DDR.
CS4 to CS7, on the other hand, can be used as chip select signals
simply by setting the chip select control register.
Figure 13.22: Chip Select Control Register (CSCR)
CS7E, CS6E, CS5E and CS4E correspond to CS7, CS6, CS5 and CS4,
respectively, and are switched to chip select pins when 1 is written.
Since the EPROM is connected to the H'000000 address, it is assigned

as area 0 and uses CS0.If CS0 is L and both A20 and A19 are 0, it is the
EPROM address. Figure 13.23 shows a decode circuit using CS0.
Figure 13.23: Decode Circuit Using CS0

13.8 Connecting CPU to Memory (Connecting SRAM Using 8-bit Data
Bus)
This section considers a case for connecting a 512kbyte SRAM

(HM628512BI-8) to a CPU. Although you only need take read timings into
account for connecting to an EPROM, both read and write timings must be
matched for a RAM. Since there is no specific address for a RAM to be
connected, locate it next to the EPROM between H'080000 and H'0FFFFF.
The SRAM address is where CS0 = L, A20 = 0 and A19 = 1.
For connection to the CPU, connect the high-write (HWR) of the CPU to the
write enable (WE) of the memory. As with the EPROM, connect the read (RD)
of the CPU to the output enable (OE) of the memory. Connection between the
CPU and the SRAM is shown in Figure 13.24.
Figure 13.24: Connection Between CPU and SRAM
Timing calculation (read timings)

Read timings are calculated in the same way for both EPROM and
SRAM. As described earlier, the address access time for the EPROM is 100ns
and both the setup and hold times are satisfied. Since it is 85ns at the slowest
for the SRAM (HM628256BI), requirements are completely satisfied. Specific
calculations are omitted here.
Timing calculation (write timings)

Figure 13.25 shows the CPU write cycle waveform required for timing
calculation.
Figure 13.25: CPU Write Cycle Waveform
The following are important for write timings as specified by the

SRAM standard:
Input data setup time (tDW) = 35ns (min.)
Input data hold time (tDH) = 0ns (min.)
Writing is conducted at either the CS or WE leading edge, whichever is
earlier.
WE inputs the HWR signals of the CPU as they are. CS is created
based on CS0 and address signals and delayed by the decoder delay time. As a
result, writing is conducted at the WE (HWR) leading edge. The setup time is
the shortest when write data is output the latest and the WE leading edge is the
earliest. This is shown in Figure 3.26.
You can see that the setup time of 90ns is secured, causing no problem.
Figure 13.26: SRAM Data Setup Time

As for the hold time, there is no problem since the hold time of tWDH =
20ns (min.) is provided for the write data output by the CPU against the WE
leading edge.
13.9 Connecting CPU to Memory (16-bit Data Bus)
When connecting a CPU and a memory using a 16-bit data bus, use a
pair of memories having 8 bits per address, or use a memory having 16 data
pins. The example described here uses a pair of memories having 8 bits per
address, which are connected as memories at even- and odd-numbered
addresses, respectively.
To read/write 16-bit data, two addresses must be accessed
simultaneously. It is impossible, however, to output two addresses to the
address bus simultaneously. Remember that the upper digits of 16-bit data in
the memory must be stored in an even-numbered address and the lower in an
odd-numbered address (even-numbered address + 1). An "even-numbered
address" and an "even-numbered address + 1" are the same from A23 to A1 in
binary notation and only A0 differs. No problem arises if A0 is not used, since
A1 to A23 are the same. A0 = 0 represents an even number and A0 = 1 an odd
number. A combination of an "odd-numbered address" and an "odd-numbered
address + 1 (even-numbered address)" does not make A1 to A23 the same,
disabling access as 16-bit data. This situation is not limited to the H8/3048 but
common to all 16-bit microcomputers.
HWR and LWR are used instead of the A0 signal. HWR = L represents
8-bit writing to an even-numbered address (A0 = 0) and LWR = L means that
to an odd-numbered address (A0 = 1).
HWR = LWR = L means writing to both even- and odd-numbered
addresses. Only the RD signal is used for reading by the CPU. During reading,
data are always handled as 16 bits without distinguishing between 8- and 16-bit
data. Sixteen bits are read even if the MOV.B instruction is used for reading
from the memory. Non-used 8 bits are not read into the CPU although they are
output from the memory. Reading data not required for the memory will not
have a negative effect. For writing, however, 8- and 16-bit writing must be
clearly distinguished since it changes the contents of the memory. This is
shown in Table 13.10.
Table 13.10: Reading/Writing on 16-bit Data Bus

Figure 13.27 shows an example to connect the CPU and SRAMs using a 16-bit
data bus.
Figure 13.27: Connection Between CPU and SRAMs (16-bit Data Bus)
The capacity becomes 1Mbyte since two SRAMs are connected and the
addresses are between H'100000 and H'1FFFFF since CS0 = 0 and A20 = 1.
Address, CS and OE signals are commonly input to two memories. For
the memory at an even-numbered address, HWR is input to the WE pin and the
data pins are connected to the upper 8 bits of the CPU. As for the memory at an
odd-numbered address, on the other hand, LWR is input to the WE pin and the
data pins are connected to the lower 8 bits of the CPU.
13.10 I/O Port Expansion
External expansion of the H8/3048 memory decreases the number of

pins available as I/O ports, which may require ports to be externally expanded.
This section describes how to expand 8 input-only pins and 8 output-only pins
using standard CMOS logic.
Since the memory-mapped I/O method is employed, this I/O function is also
connected by assigning addresses to the memory map as with a ROM and
RAM described earlier. Since the internal peripheral functions are located at
area 7, it is assumed here that the I/O ports to be externally expanded are also
connected to area 7.
HD74AC244 for input ports

The HD74AC244 Octal Buffer/Line Driver is a CMOS logic chip
having eight 3-state outputs. Figure 13.28 shows the pin assignment.

Figure 13.28: HD74AC244 Pin Assignment Diagram
Table 13.11 lists its functions.

Table 13.11: Function Table
Notes: X = Either "H" or "L"

Z = High impedance
Four buffers are configured into two pairs and each output pin is
controlled by the OE1 or OE2 signal, which is transferred from input to output
when the OE1 or OE2 pin is set at low. When the OE1 or OE2 pin is set at
high, the output pins are set in the high-impedance state.
Since the OE1 and OE2 pins are used as 8-bit input-only pins, it is
assumed here that they are short-circuited to serve as one OE pin. Eight input
pins are connected to external signals and eight output pins to the CPU data
bus. Input data is output to the data bus when OE is set at low and the
following two conditions are satisfied at the same time:
• The CPU outputs the address of this input-only port

• The RD signal of the CPU is set at low and in the read state
Accordingly, the OE signal is created based on address-decoded and RD
signals. Unlike the memory, the OE signal is regarded to have both CE and OE
functions.
The connection outline to the CPU is shown in Figure 13.29.
Figure 13.29: Connection Outline to CPU
HD74AC373 for output ports

The HD74AC373 Octal Transparent Latch is a D-type latch having
eight 3-state outputs. Figure 13.30 shows the pin assignment and Table 13.12
lists its functions.
Figure 13.30: Pin Assignment Diagram

Table 13.12: Function Table
Notes: X = Either "H" or "L"

Z = High impedance
O0 = O0 level before the input conditions shown in
the table are fixed
Figure 13.31 shows the logic diagram.
Figure 13.31: Logic Diagram
When using this IC for output ports, connect D0 to D7 to the data bus
and use O0 to O7 as signals to be externally output. When the OE pin is set at
high, output enters the high-impedance state. The OE pin, however, is fixed at
low here since the output pins need not be set to high impedance.
When LE is changed from high to low, the output data at that time is
maintained.
LE is changed to high when the following two conditions are satisfied:
• The CPU outputs the address of this output-only port
• The HWR signal of the CPU is set at low and in write state
Accordingly, the LE signal is created based on address-decoded and
HRW signals. Unlike the memory, the LE signal is regarded to have both CS
and WE functions. Figure 13.32 shows connection outline to the CPU.

Figure 13.32: Connection Outline to CPU
Address decoder
Both input and output ports have a capacity of only one address when
considered as memory. If you attempt to fully decode them so that they only
have one address, all of the 21 address buses must be decoded, making an
extremely complicated circuit. Here, we use CS7 only and omit the address
decoder. As a result, addresses between H'E00000 and H'FFFFFF of area 7 are
all used for expanded I/O ports excluding those for the internal RAM and I/O.
They are used as input ports for reading and output ports for writing. As for
parts that have overlapping addresses, the internal RAM or I/O port has
priority, disabling the CS7, RD and HWR signals to be output.
Addresses between H'FFFF10 and H'FFFF1B on the boundary between
the internal RAM and I/O ports are assumed to be used here. The 8-bit absolute
addressing instruction is available for these addresses. Figure 13.33 shows an
expanded I/O circuit.
Since the CS7 pin is set to input at resetting, pull it up to the power supply.

Figure 13.33: Expanded I/O Circuit
Note the following when using these I/O ports:

• Develop a program assuming that the address range is between
H'FFFF10 and H'FFFF1B.
• The addresses of the input and output ports are the same. They are used
as input ports for reading and output ports for writing.
• The BTST instruction is available for input ports.
• Since output ports are dedicated for output, they are incapable of
reading the current output state.
• The BTST, BSET, BCLR and BNOT instructions are not available for
output ports.
• The default values of output ports vary and the output state is not fixed
even after the CPU is reset.
• Instead, they are set by a program.
• The CS7 signal is not output by default. Before using the expanded I/O
ports, set CS7E (b7) of CSCR (H'FFFFFF5F address) of the bus
controller at 1.

There is a CPU having 16 address pins and 8 data pins. A memory of
up to (64k) bytes can be connected to it.

Since there are 16 address pins, the memory addresses are represented by 16
bits.
To be precise, a memory of 65536 bytes can be connected since there are 0 to
65535 addresses.
This is generally referred to as 64kbytes.

There is a memory having 10 address pins and 8 data pins.
This memory uses (8) bits per address and has a capacity of (1024) addresses.
Since it has 10 address pins, it has a capacity of 1024 addresses (1k) from 0 to
1023.
Eight bits are used for one address since there are 8 data pins.

Up to (64) of 256kbyte memories can be connected to a CPU having a
16Mbyte memory space.
Dividing 16M by 256k makes 64.

To be precise, 16M represents 16777216 and 256k represents 262144.

In order to read data from an EPROM, both (CE) and (OE) pins must
be set at low level.
The memory IC starts operation when CE (Chip Enable) is set at low level.
Reading is enabled when OE (Output Enable) is set at low level.

Writing to an SRAM is conducted at the leading edge of either the (CS)
or (WE) pin, whichever is earlier.
The memory IC starts operation when CS (Chip Select) is set at low level.
Writing is enabled when WE (Write Enable) is set at low level.

When connecting a CPU to a memory using a 16-bit data bus, do not
use the (A0) pin in the CPU address bus.
Connect the (upper) 8 bits of the CPU data bus to the memory at an even-
numbered address and the (lower) 8 bits to the one at an odd-numbered
address.
A0 is not available since two addresses must be specified for reading/writing

16-bit data simultaneously and addresses of A0 = 0 and A0 = 1 are
read/written at a time.

Connect them so that the contents at the even-numbered address are treated as
upper and those at the odd-numbered address as lower.

The CS0 to CS7 signals of the H8/3048 are obtained by decoding the
upper (3) bits of addresses.
By decoding the upper 8 bits of addresses, the entire memory space can be
divided into 8 equal parts.
Signals correspond to addresses as follows:
CS0: Addresses whose upper 3 bits are 000 (H'000000 to H'1FFFFF)
CS1: Addresses whose upper 3 bits are 001 (H'200000 to H'3FFFFF)
......
CS7: Addresses whose upper 3 bits are 111 (H'E00000 to H'FFFFFF)

Giao Trinh He Thong Nhung - VDK H8

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Chapter 1

This chapter lets you understand that the microprocessor is built of a

1.1 Microprocessor Configuration

The microprocessor is said to be a "computer built around ICs."

Figure 1.1 Microprocessor configuration

All these components of a microprocessor are fabricated of a single IC.

Input device (Input)

Output device (Output)

1.2 Stored Program Computers

The stored program computer provides a most precise concept of the

Figure 1.2 Operating principles of a stored program computer

Mask ROM (Mask ROM)

When a memory IC is manufactured in the factory, programs are

EPROM (Erasable & Programmable ROM)

OTPROM (One Time Programmable ROM)

EEPROM (Electrically Erasable & Programmable ROM)

Flash memory (Flash Memory)

Static RAM (Static RAM)

Dynamic RAM (Dynamic RAM)

Table 1.1 summarizes features of key ROM and RAM devices.

1.4 Single-Chip/Multi-Chip Microprocessors

Putting a CPU, ROM, RAM, and data input/output circuitry into a

Single-chip microprocessors are used as built-in controllers. When a

Kinds of internal ROM

Microprocessors and memory

1. What are the three key ICs needed to make up a microprocessor?

2. Fill the blanks with appropriate words or phrases.

Mask ROM Advantage (Inexpensive, large-sized )

EPROM Advantage (Erasable and programmable)

Mask ROM is volume-produced at factory at low cost, and features

Disadvantage (Limited internal functionality )

2.1 Kinds of Data Handled by Microprocessors

Before starting to consider how data is represented in binary numbers,

Figure 2.1 Kinds of data

2.2 Numeric Representation in Unsigned Binary Number

Unsigned binary numbers do not allow for the positive or negative

10110010 in binary, for example, is converted to a decimal equivalent as

Table 2.1 Ranges of unsigned binary numbers

This calculation, on the other hand, yields an incorrect result. The

Figure 2.2 Carry in a binary number

Next, examples of subtraction of unsigned binary numbers are given

This calculation yields an incorrect result due to its failure to subtract a

When a carry or borrow occurs in the course of a calculation in the

2.3 Numeric Representation in Signed Binary Number

Signed binary numbers distinguish between positive and negative, but

Only the most significant bit is treated as being negative. Accordingly,

10000000 represents -128

Table 2.2 Ranges of signed binary numbers

Figure 2.3 8-bit binary numbers

Examples of addition of signed binary numbers are given below.

This calculation, on the other hand, gives an incorrect result, because

Next, examples of subtraction of signed binary numbers are given below.

Twos complement notation

2.4 BCD Code

2.5 ASCII Code

The ASCII (American Standard Code for Information Interchange)

Character code of 1 00110001

2.6 Numeric Representations

While the computer internally operates on the basis of binary numbers,

Table 2.4 Correspondence among binary, hexadecimal and decimal

In programs, H 'and B' designate hexadecimal notation and binary

Binary notation Decimal notation Decimal Hexadecimal

Binary notation 01001110