Laboratory Manual for

Communication System

B. E.
SEM. VI (EC)

Supported by

Reviewed by
Dr. Nikhil Kothari

January 2010

Faculty of Technology
Dharmsinh Desai University
Nadiad
 LAB MANUAL

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 LAB 01

Analog Sampling & Reconstructions

AIM: To study sampling of analog signals and reconstruction.

EQUIPMENTS: Experimental' kit DCL.-01.

Power supply.
20 MHz Dual Trace

APPARATUS: Connecting Chords.

THEORY:
Sampling of the signal is fundamental operation in signal processing. A continuous
time signal is first converted to discrete time signal by sampling process. The
sufficient no. of samples of the signal must be taken so that the original signal is
represented in its samples completely. It should be possible to recover or
reconstruct the original signal completely from its samples. The no. of samples to
be taken depends on maximum signal frequency present in the signal. Sampling
theorem gives the complete idea about sampling and reconstruction.
The kit is used to study Analog Signal Sampling and its Reconstruction. It
basically consists of functional blocks, namely Function Generator, Sampling
Control Logic, Clock section, Sampling Circuitry and Filter Section.

FUNCTION GENERATOR:

This Block generates two sine wave signals of 1 KHz and 2KHz frequency. This
sine wave generation is done by feeding 16 KHz and 32KHz clock to the shift
register. The serial to parallel shift register with the resistive ladder network at
the output generates 1 KHz and 2KHz sine waves respectively by the serial shift
operation. The R-C active filter suppresses the ripple and smoothens the sine

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wave. The unity gain amplifier buffer takes care of the impedance matching
between sine wave generation and sampling circuit.

SAMPLING CONTROL LOGIC:

This unit generates two main signals used in the study of Sampling Theorem,
namely the analog signals (5V pp, frequency 1 KHz and 2KHz) & sampling signal
of frequency 2KHz, 4KHz, 8KHz, 16KHz, 32KHz, and 64KHz.

The 6.4 MHz Crystal Oscillator generates the 6.4 MHz clock. The decade
counter divides the frequency by 10 and the ripple counter generates the basic
sampling frequencies from 2KHz to 64KHz and the other control frequencies.

From among the various available sampling frequencies, required sampling

frequency is selected by using the Frequency selectable switch. The selected
sampling frequency is indicated by means of corresponding LED.

CLOCK SECTION:

This section facilitates the user to have his choice of external or internal clock
feeding to the sampling section by using a switch (SW4).

SAMPLING CIRCUITRY:

The unit has three parts namely, Natural Sampling Circuit, Flat top Sampling
Circuit, and Sample and Hold Circuit.

The Natural sampling section takes sine wave as analog input and samples the
analog input at the rate equal to the sampling signal. For sample and hold
circuit, the output is taken across a capacitor, which holds the level of the
samples until the next sample arrives. For flat top sampling clock used is
inverted to that of sample & hold circuit. Output of flat top sampling circuit is
pulses with flat top and ton corresponds to the level of analog signal at the
instant of rising edge of the clock signal.

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BLOCK DIAGRAM:

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PROCEDURE:

1. Refer to the Block Diagram & carry out the following connections and
switch settings.
2. Connect power supply in proper polarity to the kit DCL-01 & switch it on.
3. Connect the 1 KHz; 5Vpp Sine wave signal, generated onboard, to the
BUF IN post of the BUFFER and BUF OUT post of the BUFFER to the IN
post of the Natural Sampling block by means of the Connecting chords
provided.
4. Connect the sampling frequency clock in the internal mode INT CLK
using switch (SW4).
5. Using clock selector switch (S1) select 8 KHz sampling frequency.

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 6. Using switch SW2 select 50% duty cycle.
7. Connect the OUT post of the Natural sampling block to the input IN1
post of the 2"d Order Low Pass Butterworth Filter and take necessary
observation as mentioned below.

OBSERVATIONS:

Observe the following waveforms in order for every setting and plot it on
the paper. a. 1 KHz Analog Input waveform.
b. Sampling frequency waveform.
c. Natural sampling signal and its corresponding reconstructed output
of 2"d order
Low Pass Butterworth Filter.

CONCLUSION:

ASSIGMENT:
1. How flat top sampling is performed using natural sampling and sample &
hold sampling?
2. What is sampling theorem?
3. Why practical sampling frequency should be greater than twice of the
maximum signal frequency (Theoretical sampling frequency) ?

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[B] Study Effect of Various Sampling Frequencies.

PROCEDURE:

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1. Refer to the BLOCK DIAGRAM AN CARRY OUT CONNECTIONS and switch
settings.
2. Connect power supply in proper polarity to the kit DCl-01 & switch it on.
3. Connect the 1 KHz,5Vpp S.ine wave signal, generated onboard, to the BUF
IN. post of the BUFFER arid the BUF OUT post of the BUFFER to the
IN pas: of Natural sampling block by means of the Connecting chords
provided. Connect the sampling frequency signal in the internal mode
INT CLK using Switch (SW4).
4. Using switch SW2 select 50% duty cycle.
5. Connect the Sampled Output OUT to the input of the IN 1 post of 2nd Order
Low Pass Butterworth Filter
6. Using clock selector switch select various sampling frequency and see the
effect on resultant output

CONCLUSION:

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[C] Study of Second Order & Fourth Order Low Pass Filter.

PROCEDURE :

1. Refer to the BLOCK DIAGRAM AN CARRY OUT CONNECTIONS and switch

settings.
2. Connect power supply in proper polarity to the kit DCl-01 & switch it on.
Connect The 1 KHz,5Vpp S.ine wave signal, generated onboard, to the BUF
IN.
Post of the BUFFER arid the BUF OUT post of the BUFFER to the IN pas: of
Natural Sampling block by means of the Connecting chords provided.
Connect the sampling Frequency signal in the internal mode INT CLK using
Switch (SW4).
3. Using switch SW2 select 50% duty cycle.
4. Connect the Sampled Output OUT to the input of the IN 1 post of 2nd Orser
Low Pass Butterworth Filter.

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 5. Now observe the same output with 4th order filter and see the difference
between outputs.

CONCLUSION :

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 LAB 02
TDM Pulse Amplitude Modulation and Demodulation
AIM : Study of TDM Pulse amplitude modulation and demodulation.

EQUIPMENTS: Experimental' kit DCL.-02.

Power supply.
20 MHz Dual Trace

APPARATUS: Connecting Chords.

THEORY:
It's often practical to combine a set of low-bit-rate streams, each with a fixed and
pre-defined bit rate, into a single high-speed bit stream that can be transmitted
over a single channel. This technique is called time division multiplexing (TDM)
and has many applications, including wire line telephone systems and some
cellular telephone systems. The main reason to use TDM is to take advantage of
existing transmission lines. It would be very expensive if each low-bit-rate stream
were assigned a costly physical channel (say, an entire fiber optic line) that
extended over a long distance.
Transmitter:
Consider the conditions at a transmitter, where two messages are to be sampled
and combined into a two-channel PAM/TDM signal. If two such messages were
sampled, at the same rate but at slightly different times, then the two trains of
samples could be added without mutual interaction. This is illustrated in Figure
1

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The width of these samples is δt, and the time between samples is T. The
sampling thus occurs at the rate (1/T) Hz. Figure 1 is illustrative only. To save
cluttering of the diagram, there are fewer samples than necessary to meet the
requirements of the sampling theorem. This is a two-channel time division
multiplexed, or PAM/TDM, signal. One sample from each channel is contained in a
frame, and this is of length T seconds. In principle, for a given frame width T, any
number of channels could be interleaved into a frame, provided the sample width
δt was small enough.
Receiver:
Provided the timing information was available - a knowledge of the frame period
T and the sampling width δt - then it is conceptually easy to see how the samples
from one or the other channel could be separated from the PAM/TDM signal. An
arrangement for doing this is called a de-multiplexer. An example is illustrated in
Figure 2.

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The switching function s(t) has a period T. It is aligned under the samples from
the desired channel. The switch is closed during the time the samples from the
desired channels are at its input. Consequently, at the switch output appear only
the samplesof the desired channel. From these the message can be
reconstructed.

In TDM-PAM systems, for proper recovery of information, the TX clock and RX

clock, TXSYNC and RXSYNC should be perfectly synchronized. For this purpose,
the TX clock and TXSYNC can be transmitted along with the data but it calls for
another two lines of transmission. For conserving the line, a PLL is used at the
receiver for the recovery of the clock from the TXSYNC. By this method, one line
can be effectively conserved.

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CIRCUIT DIAGRAM:

PROCEDURE:
1. Refer to the Block Diagram (Fig. 2) & Carry out the following connections
and switch settings.

2. Connect power supply in proper polarity to the kit DCL-02 & switch it on.

3. Connect 250Hz, 500Hz, 1 KHz, and 2KHz sine wave signals to the
multiplexer input channel CHO, CHI, CH2 and CH3 by means of the
Connecting chords provided.

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4. Connect the multiplexer output TXD of the transmitter section to the
demultiplexer input RXD of the receiver section.

5. Connect the output of the Demultiplexer CHO, CHI, CH2, and CH3 to the
input of the filter section IN O, IN 1, IN 2, IN 3.

6. Connect the Channel Identification Signal TXSYNC of the transmitter

section to the PLL Input post PLL IN.

7. Set the PLL Input Switch SW1 to L2 position.

8. Connect the SYNC and CLOCK generated by the PLL circuitry to RXSYNC
and RXCLK o f the receiver respectively.

9. Set the amplitude o f the input sine wave as desired.

10. Take observations as mentioned below.

1 1. I f the reconstructed signal appears to be improper press RESET switch to

get proper signal reconstruction.

OBSERVATIONS:
Observe the following waveforms on oscilloscope and plot it on the paper.

a. Input Channel CHO, CHI, CH2, CH3.

b. Transmitter Clock TX CLK.

c. Channel Identification Signal TX SYNC.

d. Multiplexer Output TXD.

e. Demultiplexer Input RXD.

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f. SYNC and CLOCK generated by PLL.

g. Demultiplexer output CHO, CHI, GH2, and CH3.

h. Reconstructed signal OUT O,OUT 1,OUT 2,

OUT

CONCLUSION:

ASSIGMENT:

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 LAB 03

Pulse Amplitude modulation and demodulation

AIM: Study of Pulse Amplitude Modulation and Demodulation.

EQUIPMENTS: Experimental' kit DCL.-08.

Power supply.
20 MHz Dual Trace

APPARATUS: Connecting Chords.

BLOCK DIAGRAM:

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THEORY:

Pulse amplitude modulation is a technique of communication in which, high

frequency square wave is modulated by low frequency analog signal. The pulses
sample the modulating signal. The PAM signal is nothing but the high frequency
square wave in which the amplitude of each pulse is equal to that of the
information signal at that respective sampling instant. In Pulse Amplitude
Modulation , the signal is sampled at regular intervals and the amplitude of each
sample is made proportional to the amplitude of the signal at that instant of
sampling . This amplitude of each sample is hold for the sample duration to make
pulses flat top. This provides the pulse modulated signal output at the PAM
OUTPUT Post. The pulse are flat top sampled.

Flat top sampled PAM signal can be passed through 4th order butter worth
filter. It gives demodulated output at filter output post, which is same as original
signal. The Pulse Amplitude Demodulator consists of Active Low Pass Butterworth
filter. It filters out the sampling frequency and their harmonics from the
modulated signal and recovers the base band by integrated action.

PROCEDURE:

1. Refer to the block diagram (fig. 1) and carry out the following connections
and switch settings.
2. Select 16KHz sampling frequency by jumper JP1.
3. Connect the 1KHz , 2Vp-p sine wave signal generated onboard to PAM in
post.
4. Observe the Pulse Amplitude Modulation output at PAM OUT post.

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5. Short the following posts with the connecting chords provided as shown in
block diagram.
PAM OUT and AMP IN
AMP OUT and FIL IN
6. Keep the amplifier gain control potentiometer P5 to maximum completely
clockwise.

OBSERVATIONS :

1. Observe the Pulse Amplitude Demodulated signal at FIL OUT , which is the
same As the input signal.

1. Repeat the experiment for different input signal and sampling

frequencies.

CONCLUSION :.

ASSIGMENT:
1. What is sampling ? how it is useful in pulse amplitude modulation?

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2. Which type of sampling we are getting as a out put of PAM?
3. How to get demodulated out put?

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 LAB 04

Pulse width modulation and demodulation

AIM : Study of Pulse Width Modulation and Demodulation.

EQUIPMENTS: Experimental' kit DCL.-08.

Power supply.
20 MHz Dual Trace

APPARATUS: Connecting Chords.

BLOK DIAGRAM:

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THEORY :

PULSE WIDTH MODULATION

This technique of modulation controls the variation of duty cycle of the square
wave according to the input modulating signal. Here the amplitude variation of
the modulation signal is reflected in the ON period variation of square wave.

PULSE WIDTH DEMODULATION

The input signal is Pulse Width Modulated , so the ON time of the signal is
changing according to the modulating signal. In this demodulation technique
during the ON time of PWM signal one counter is enabled . At the end of ON time
, counter gives a particular count, which directly corresponds to the amplitude of
the input signal. Thus train of varying pulse widths gives varying count values and
accordingly DAC gives outputs. This is then filtered to get original signal.

PROCEDURE :

1. Refer to the block diagram (fig. 1) and carry out the following connections and
switch settings.
2. Connect the power supply with proper polarity to the kit DCL – 08 and switch it
on.
3. Put jumper JP3 to 2nd position.
4. Select 1KHZ 1Vp-p sine wave signal generated onboard.

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5. Connect this signal to PWM/PPM in.
6. Observe the Pulse Width Modulation output at PWM OUT post. Note that
since the sampling frequency is high , only blurred band in waveform will be
seen due to persistance of vision. In absense of input signal only square wave
of fundamental frequency and fixed on time will be observed and no width
variations are present.
7. To observe the variation in pulse width , apply 1-30Hz sine wave signal to
PWM/PPM IN post. Vary the frequency from 1-30 Hz.
8. Short the following posts with the connecting chords provided as shown in
block diagram.
PWM OUT and BUF IN
BUF OUT and PWM DMOD IN.
DMOD OUT and FIL IN

OBSERVATIONS:

1. Observe the Pulse Amplitude Demodulated signal at FIL OUT , which is the
same
As the input signal.
2. Repeat the experiment for different input signal and sampling frequencies.

CONCLUSION:

ASSIGMENT:

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1. Why we require to use butter worth filter?
2. Describe the procedure for performing pulse width modulation?
3. Draw the waveforms of PWM modulation and PWM demodulation?

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 LAB 05
Pulse position modulation and demodulation

AIM : Study of Pulse Position Modulation and Demodulation.

EQUIPMENTS: Experimental' kit DCL.-08.

Power supply.
20 MHz Dual Trace

APPARATUS: Connecting Chords.

BLOCK DIAGRAM:

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THEORY :

MODULATION

In this technique of modulation, the position of TTL pulse is changed on time scale
according to the variation of input modulation signal amplitudes. The pulse
positions are directly proportional to the instantaneous values of the modulating
signal. Width and amplitude of the pulses remain same.

DEMODULATION

This pulse position modulated signal is converted into PWM pulse form using
monostable multivibrator . This signal is then demodulated using the same
technique of PWM demodulation. The input signal is Pulse Width Modulated , so
the ON time of the signal is changing according to the modulating signal. In this
demodulation technique during the ON time of PWM signal one counter is
enabled . At the end of ON time , counter gives a particular count, which directly
corresponds to the amplitude of the input signal. Thus train of varying pulse
widths gives varying count values and accordingly DAC gives outputs. This is then
filtered to get original signal.

PROCEDURE:

1. Refer to the block diagram (fig. 1) and carry out the following connections and
switch settings.
2. Connect the power supply with proper polarity to the kit DCL – 08 and switch it
on.
3. Put jumper JP3 to 2nd position.

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4. Select 1KHZ 1Vp-p sine wave signal generated onboard.
5. Connect this signal to PWM/PPM in.
6. Observe the Pulse Position Modulated output at PPM OUT post with shifted
position on time scale . Note that amplitude and width of pulses are same only
position is shifted which is proportional to input signal.
7. To observe the variation in pulse position , apply 1-30Hz sine wave signal to
PWM/PPM IN post. Vary the frequency from 1-30 Hz.
8. Short the following posts with the connecting chords provided as shown in
block diagram for demodulation sections .
PPM OUT and BUF IN
BUF OUT and PPM DMOD IN.
DMOD OUT and FIL IN

OBSERVATIONS:

1. Observe the Pulse Amplitude Demodulated signal at FIL OUT , which is the
same
As the input signal.
2. Repeat the experiment for different input signal and sampling frequencies.

CONCLUSION:

ASSIGMENT:

1. Sketch waveforms of PPM modulation and PPM demodulation?

2. In PPM width and amplitude are varying or not?

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3. How to receive original signal in PPM?

LAB 06

Pulse Code Modulation and Demodulation

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AIM : To study Pulse code modulation and demodulation.

EQUIPMENTS: Experimental' kit DCL.-03 & DCL.-04.

Power supply.
20 MHz Dual Trace

APPARATUS: Connecting Chords.

THEORY:

Pulse code modulation is a digital communication of signals such as speech, audio,

video etc. And for all modern digital system, sampling is the first step. The
sequence of numbers obtained by sampling takes continuous amplitude values.
To represent the continuous amplitudes, we needs infinite number of bits. For
practical purpose we need to restrict the number of bits for representing a signal
and this involves “quantization” of the amplitude values. The basic form of
encoding sampled data is Pulse Code Modulation (PCM). The analog to digital
convertor converts the analog samples to digital bits. The analog to digital
convertor IC AD673 forms the heart of this logic, the device performs both the
quantizing and encoding operations. Thus the analog to digital convertor assigns
the code words for all the samples. The digital to analog convertor logic converts
the 7 bit coded sequence obtained at the output of the detect/correct logic to
analog samples. This logic is built around the digital to analog converter IC, DAC
0800. It reproduce the multiplexed sample levels at the receiver.

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BLOCK DIAGRAM:

PROCEDURE:

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 1. Refer to the Block Diagram carry out the following connections. Connect
power supply in proper polarity to the kits DCL-03 and DCL.04 and
switch it on.
2. Connect sine wave of frequency 500Hz and 1 KHz to the input CHO and
CH1 of the sample and hold logic.
3. Connect OUT 0 to CHO IN & OUT 1 to CH1 IN.
4. Set the speed selection switch SW1 to FAST mode. Select parity
selection switch to NONE mode on both the kit DCL-03 and DCL-04 as
shown in switch setting diagram.
5. Connect TXDATA, TXCLK and TXSYNC of the transmitter section DCl-03
to the corresponding RXDATA, RXCLK, and RXSYNC of the receiver
section DCl-04.
6. Connect posts DAC OUT to IN post of demultiplexer section on DCl-04.
Ensure that FAULT SWITCH SF1 as shown in switch setting diagram
introduces no fault.
7. Take the observations as mentioned below.
8. Repeat the above experiment with DC Signal at the inputs of the
Channel CH 0 and CH 1.

OBSERVATION:
ON KIT DCl-03

A Input signal CH 0 and CH 1.

B Sample and Hold output OUT 0 and OUT;

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 C Multiplexer clock CLK 1 and CLK 2
D Multiplexed data MUXOUT
E PCM Data TX DATA,TXCLK,SYNC

ON KIT DCl-04

A RXCLK, RXSYNC. RXDATA

B DAC OUT
C Demultiplexer clock CLK 1 and CLK 2
D Demultiplexer Data CH 0 and CH 1
E Received sign3! OUT 0 and OUT 1

CONCLUSION:

ASSIGMENT:
1. What is pulse code modulation?
2. Define term Quantization Noise.
3. Draw the wave form for multiplexer output.

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 LAB 07

Delta Modulation and Demodulation

AIM: To Study Delta Modulation and Demodulation.

EQUIPMENTS: Experimental' kit DCL.-07,

Power supply,
20 MHz Dual Trace

APPARATUS: Connecting Chords.

THEORY:

DELTA MODULATION:

Delta modulation is the differential pulse code modulation scheme in which the
difference signal is encoded into just a single bit. In digital modulation system, the
analog signal is sampled and digitally coded. This code represents the sampled
amplitude of the analog signal. The digital signal is sent to the receiver through
any channel in serial form. At the receiver the digital signal is decoded and filtered
to get reconstructed analog signal. Sufficient number of samples are required to
allow the analog signal to be reconstructed accurately. Delta modulation is a
process of converting analog signal into one bit code, means only one bit is sent
per sample. This bit indicates whether the signal is larger or smaller than the
previous samples. The advantage of DM is that the modulator and demodulator
circuits are much simpler than those used in traditional PCM.

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Delta modulation is an encoding process where the logic levels of the transmitted
pulses indicate whether the decoded output should rise or fall at each pulse. This
is a true digital encoding process compared to PAM, PWM and PPM.

If signal amplitude has increased in DM then modulated output is a logic level 1. If

the signal amplitude has decreased the modulator output is logic level 0. Thus the
output from the modulator is a series of zeroes and ones to indicate rise and fall
of the waveform from the previous value.

The block diagram of Delta Modulation illustrates the components at the

transmitter end of the channel and the receiver the base band signal a(t) and its
quantized approximation i(t) are applied as inputs to the comparator. A
comparator as its name suggests simply makes a comparison between inputs. The
comparator has one fixed output c(t) when a(t) > i(t) and the different output
when a(t) < i(t) the comparator output is then latched in to a D-flip flop which is
clocked by the selected transmitter clock. Thus the output of the D-flip/flop is
latched 1 or 0 synchronous with the clock edge. This binary data stream is
transmitted to the receiver and is also fed to unipolar to bipolar converter. This
block converts a logic `0' to positive voltage level and a logic '1' to negative

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voltage level. Then unipolar to bipolar output is fed to the input of integrator. The
integrator output is then connected to the negative terminal of voltage
comparator, thus completing the modulator circuit. The waveform of the Delta
Modulator is as shown in the figure.

Slope overload error

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 (b) Delta modulator output

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DELTA DEMODULATION

The Delta Demodulator consists of a D-flip/flop, unipolar to bipolar converter

followed by an integrator and a 2"d/ 4Ih order low pass butterworth filter. The
Delta Demodulator receives the data stream from D-flip/flop of Delta Modulator.
It latches this data at every rising edge of receiver clock. This data stream is then
fed to unipolar to bipolar converter, which changes the output from D-flip/flop to
either - ve voltage or +ve voltage for logic '1' and '0' respectively. As it has been
seen in case of modulator when the output from unipolar to bipolar c nverter is
applied to integrator, its output tries to follow the analog signal in ramp ~ashion
and hence is a good approximation of the signal itself. The integrator output
contains sharp edges, which is smoothened out by the 2nd order, and 4th order
low bass butter worth filter whose cut-off frequency is just above the audio band.

DM Unipolar to
D F/F Integrator
Bipolar
Signal
Converter

2nd
Signal
order/4th
Order Filter

Fig. 1.2 Block Diagram of Delta Demodulator

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The practical use of Delta Modulation is limited due to following drawbacks:

i) NOISE: A noise is defined, as any unwanted random waveform accompanying

the information signal. When the signal is received at the receiver irrespective of
any copy channel it is always accompanied by noise.

ii) DISTORTION: Distortion means that the receiver output is not the true of the
analog input signal at the transmitter. In Delta modulation, when the analog
signal is greater than the integrator output the integrator ramps up to meet the
analog signal. The ramping rate of integrator is constant. Therefore if the rate of
change of analog input is faster than the ramping rate, the modulator is unable to
catch up with the input signal. This causes a large disparity between the
information signal and it's quantised approximation. This error phenomenon is
known as Slope over loading (as shown in fig. (a) ) and causes the loss of rapidly
changing information. The problem of slope overload can be solved by increasing
the ramping rate of the integrator. But as it can be seen from the figure the effect
of the large step size is to add large sharp edges at the integrator output and
hence it adds to noise.

iii) Another problem of Delta Modulation is that it is unable to pass DC

information. This is not a serious limitation of the speech communication..

PROCEDURE:

1. Refer to the block diagram and carry out the following connections.

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2. Connect the power supply with the proper polarity to the Kit DCL-07 and
switch it on.
3. Select sine wave input 250Hz of OV through pot P8 and fed it to input
buffer section. Then give buffer output to Delta modulator input.
4. Then select clock rate of 8 KHz by pressing SW1.
5. Then observe the Delta modulated output and compare it with the clock
rate selected. These waveforms are as shown in figure. It is half the
frequency of clock rate selected.
6. Observe the integrator output test point.
It can be observe that as the clock, rate is increased amplitude of triangular
waveform decreases. This is called minimum step size. Then increase the
amplitude of 250Hz sine wave upto 0.5V. Signal approximating 250Hz is
available at the integrator output. This signal is obtained by ;ntegrating the
digital output resulting from Delta modulation.
7. Then go on increasing the amplitude of selected signal through the
respective pot from 0 to 1V. It can be observed that the digital high makes
the integrator output to go upward and digital low makes the integrator
output to go downwards. Observe that the integrator output follow the
input signal. Adjust P12 to get a stable waveform if required. The
waveforms are as shown in the figure. Observe the waveforms at various
test-points in the Delta modulator section.

8. Increase the amplitude of 250Hz sine wave through pot P8 further high and
observe that the integrator output cannot follow the input signal. State the
reason.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 40
9. Repeat the above mention procedures with different signal sources and
selecting the different clock rates and observe the response of Delta
Modulator.

10. Connect Delta modulated output to the input of Delta Demodulator

section.
11. Connect output of Delta demodulator to the input of output buffer section.
And give buffer output to the 4th order low pass butterworth filter through
2"d order low pass butter worth filter.
12. Then observed various tests points in Delta Demodulator section and
observed the reconstructed signal through 2"d and 4th order low pass butter
worth filter. Observe the waveforms.

OBSERVATION:

Observe the following signal on oscilloscope and plot it on the paper.

A Sampling clock.
B Integrator output at feedback loop for
demodulator.
C Delta Modulator Output.
D Delta Demodulator Output.
E Filter Output.

CONCLUSION:

ASSIGMENT:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 41
 LAB 08
Adaptive Delta Modulation and Demodulation

AIM: To Study of Adaptive Delta Modulation and Demodulation with Continuous

Variable Slope Delta Modulator (CVSD)

EQUIPMENTS: Experimental' kit DCL.-07,

Power supply,
20 MHz Dual Trace

APPARATUS: Connecting Chords.

THEORY:

Delta modulation has the delightful elegance of primitive simplicity yet it suffers
from severe limitations on account of which it finds almost no application in real
systems. Here, we consider a modification of DM called Adaptive Delta
Modulation in which step size is not kept fixed. Rather, when slope overload
occurs the step size becomes progressively larger, there by allowing quantized
signal to catch up with original signal more rapidly.

The CVSD is the simple alternative to more complex conventional conversion

techniques in system requiring digital communication of analog signals. The CVSD
A/D is well suited for the requirements of digital communications. A Delta
Modulator consists of a comparator in the forward path and an integrator in the
feedback path of a simple control loop. The input to the comparator is the simple
analog signal and the integrator output. The comparator output is the difference
between the input voltage and the integrator output. That sign bit is the digital

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 42
output and also control the direction of ramp in the integrator. The output of
comparator is fed to the sampler. Then the sampler output is fed to the slope
polarity switch and level detect algorithm. The level detect algorithm is again fed
to the slope magnitude control followed by slope polarity switch. The output
slope polarity switch is fed to the integrator in the control loop. With no input at
the transmitter a continuous 1 and 0 alternations are transmitted. The
outstanding characteristic is its ability to transmit the intelligible voice out at
relatively low data rate. Companded PCM for telephone quality transmission
requires about 64Kbits/sec. data rate/channel. CVSD produces equal quality at
32Kbit/sec.

In CVSD Decoder CVSD mod output is fed to the input of comparator. The
comparator output is fed to the internal shift register. Then the output of internal
shift register is fed to the digital logic followed by slope polarity switch and
integrator. The output of integrator is fed to the low pass filters for the
reconstruction of original signal.

PROCEDURE:

Adaptive Delta Modulation & Demodulation:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 43
1. Refer to the block diagram (Fig. 7.1) and carry out the following
connections.
2. Connect the power supply with the proper polarity to the Kit DCL-07 and
switch it ON.
3. Select sine wave input 250Hz of 1.8V through pot P8 and fed it to input
buffer section. Then give buffer output to Delta modulator input.

4. Then select clock rate of 8 KHz by pressing SW1.

5. Connect Delta modulated output to the input of Delta Demodulator

section.
6. Connect output of Delta demodulator to the input of output buffer
section. And give buffer output to the 4th order low pass butter worth
filter through 2"d order low pass butter worth filter.
7. If you observe the distorted sine wave at the output of filter due to slope
overload vary the gain of integrators to maximum in both the blocks of
Delta by pot P12 in the circuits till the good recovery of output.

8. Repeat the above mention procedures with different signal sources and
selecting the different clock rates and observe the response of Adaptive
delta modulation.
9. We will get better recovery of signal as we go on increasing the clock rates
(e.g. 64 KHz).

OBSERVATION:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 44
Observe the following signal on oscilloscope and plot it on the paper.

A Sampling clock.
B Integrator output at feedback loop for
demodulator.
C Adaptive Delta Modulator Output.
D Adaptive Delta Demodulator Output.
E Filter Output.

CONCLUSION:

ASSIGMENT:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 45
 LAB 09

DATA FORMATTING AND REFORMATTING

AIM : Study of Data formatting and Reformatting.

[A] Non Retum to Zero - Level (NRZ-L),

Non Return to Zero - Mark (NRZ-M),

Non Return to Zero - Space (NRZ-S),

Unipolar to Bipolar-Bipolar to Unipolar

EQUIPMENTS: Experimental' kit DCL.-05,

Power supply,
20 MHz Dual Trace

APPARATUS: Connecting Chords.

THEORY:

NON-RETURN TO ZERO signals are the easiest formats that can be generated.
These signals do not return to zero with the clock. The frequency component
associated with these signals are half that of the clock frequency. The following
data formats come under this category. Non-return to zero encoding is
commonly used in slow speed communications interfaces for both synchronous
and asynchronous transmission. Using NRZ, logic 1 bit is sent as a high value and
a logic 0 bit is sent as a low value.

A) NON-RETURN-TO-ZERO – LEVEL(NRZ-L):

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 46
 This is the most extensively used waveform in digital logics the data format is
vary simple where all “ones” are represented by “HIGH” and all “zeroes” by
“LOWS” the data format is directly got at the output of all digital data
generation logics and hence very easy to generate. Here all the transitions
take place at the rising edge of the clock.

B) NON-RETURN TO ZERO – MARK (NRZ-M):

These waveforms are extensively used in magnetic tap recording in this data
format, all “one” are marked by change in levels and all “zero” by no
transitions. And the transitions take place at the rising edge of the clock.

C) NON-RETURN TO ZERO – SPACE (NRZ-S):

This type of waveform is marked by change in levels for “zero” and no
transition for “one” and the transitions take place at the rising edge of the
clock. This format is also used magnetic tap recording.

D) UNIPOLAR AND BIPOLAR:

Unipoolar signals are those signals, which have transition between 0 to +VCC.
Bipolar signals are those signals, which have transition between +VCC to –
VCC.

For the decoding the NRZ coded data, first of all the clock is recovered from
the incoming coded data by using PLL techniques.

PROCEDURE:

1. Refer the block diagram and carry out the following connections,
2. Connect clock and DATA generated on DCL 05 to coding clock in
and DATA INPUT respectively by means of the connecting-chords provided.
Connect the cod3d data. NRZ-l on DCL-05 to the corresponding data input
NRZ-L, of the decoding logic onDCL-06

3. Keep the switch SW2 for NRZ-l to ON position for decoding logic.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 47
 4. Observe the coded and decoded output on oscilloscope.
5. Similarly perform for NRZ- M,NRZ – S and bipolar to unipolar.

Figure: Connections fro NRZ-L Coding / Decoding Techniques

OBSERVATION:
On DCL 05

A Coded data NRZ-L

B Coded data NRZ-M

C Coded data NRZ-S

On DCL 06

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 48
 D Decoded data OUT 1'

E Decoded data OUT 2

F Decoded data OUT 3

[B] Coding techniques for phase encoded format.

Biphase Mark
Biphase level
Biphase space

PROCEDURE :
As above make the connections and use different switching for biphase mark,
biphase space and biphase level.

OBSERVATION:
On DCL 05

A Coded data BIO-L

B Coded data BIO-M

C Coded data BIO-S

On DCL 06

D Decoded data OUT 5

E Decoded data OUT 6

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 49
 F Decoded data OUT 7

CONCLUSION:

ASSIGMENT:

LAB 10
(a) Amplitude Shift Keying

AIM: AMPLITUDE SHIFT KEYING MODULATION TECHNIQUES

EQUIPMENTS: Experimental' kit DCL.-05 & DCL-06

Power supply,
20 MHz Dual Trace

APPARATUS: Connecting Chords.

THEORY:

Carrier modulation is a technique by which digital data is made to modulate a

continuous wave carrier. For all types of carrier modulation, the carrier frequency
should be at least 2 times that of modulating frequency. In amplitude shift keying,

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 50
the carrier is transmitted when the modulating data is “one” and the carrier is
rejected from transmission when the data is “zero“. In DCL-05 the ASK
Modulators employs an Analog Multiplexer as a modulating switch, which can
switch between carrier and ground, for every “one” to “zero” transitions. The
carrier frequency chosen for ASK modulation is 1MHZ.

ASK DEMODULATOR block on DCL-06 employs an envelop detector to recover the

data from the modulated carrier. The ASK modulated input is fed to the half wave
rectifier. The rectified input is fed to the filter, where the original data is
recovered. The threshold detector is used to recover the original amplitude levels
of the data. So whenever the sine wave is transmitted, the detector identifies it as
a “one” and whenever the carrier is absent; the detector identifies it as a “zero”.

BLOCK DIAGRAM:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 51
PROCEDURE:

1. Refer to the block diagram and carry out the following connection and
switch setting.
2. Connect power supply in proper polarity to the kits DCL-05 and DCL-06 and
switch it ON.
3. Connect clock and data generated on DCL-05 to coding clock in and data
input respectively by means of the connecting-chords provided.
4. Connect the NRZ-L data input to the control input of the carrier modulator
logic.
5. Connect carrier component SIN2 to INPUT1 and GROUND to INPUT2 of the
carrier modulator logic.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 52
 6. Connect ASK modulated signal modulator output on DCL-05 to the ASK IN
of the ASK demodulator on DCL-06.
7. Observe various waveforms as mentioned below.

OBSERVATION:

Observe the following waveform on CRO and plot it on the paper.

ON KIT DCL-05

A input NRZ-L Data at control input

B Carrier frequency SIN 2.
C ASK modulated signal at modulator output.
ON KIT DCL-06

A ASK Modulated signal at ASK IN.

B ASK Demodulated signal at ASK OUT.

CONCLUSION:

ASSIGMENT:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 53
 LAB 10

(b) FREQUENCY SHIFT KEYING

AIM : FREQUENCY SHIFT KEYING MODULATION TECHNIQUES

EQUIPMENTS: Experimental' kit DCL.-05 & DCL-06,

Power supply,
20 MHz Dual Trace

APPARATUS: Connecting Chords.

THEORY:

In Frequency Shift Keying modulation techniques, the modulated output shifts

between two frequencies for all “one” to “zero” transitions. The carrier
frequencies chosen for FSK modulation are 500KHZ and 1 MHZ. Note that the
above frequencies are greater than twice the modulating frequency. Note that
the FSK may be thought of as an FM system in which the carrier frequency is
midway between the mark and space frequencies, and modulation is by a square
wave.

BLOCK DIAGRAM:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 54
PROCEDURE:

1. Refer to the block diagram and carry out the following connection and
switch
settings.

2. Connect power supply in proper polarity to the kits DCL-05 and DCL-06
and
switch it ON.

3. connect CLOCK and DATA generated on DCL-05 to coding clock in and

data input respectively by means of the connecting-chords provided.
4. Connect the NRZ-L data input to the control input of the carrier
modulator logic.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 55
 5. Connect carrier component SIN 1to INPUT1 and SIN 2 to INPUT2 of the
carrier modulator logic.
6. Connect FSK modulated signal modulator output on DCL-05 to the FSK
IN of the FSK demodulator on DCL-06.
7. Observe various waveforms as mentioned below.

OBSERVATION:

Observe the following waveform on CRO and plot it on the paper.

ON KIT DCL-05

A input NRZ-L Data at control input

B Carrier frequency SIN 1 and SIN 2.
C FSK modulated signal at modulator output.

ON KIT DCL-06

A FSK Modulated signal at FSK IN.

B FSK Demodulated signal at FSK OUT.
C Observe output of phase detector, lpf, vco on test point provided.

CONCLUSION:

ASSIGMENT:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 56
Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 57
 LAB 10

(c) PHASE SHIFT KEYING

AIM : PHASE SHIFT KEYING MODULATION TECHNIQUES

EQUIPMENTS: Experimental' kit DCL.-05 & DCL-06,

Power supply,
20 MHz Dual Trace

APPARATUS: Connecting Chords.

THEORY:

In Phase Shift Keying (PSK) modulation technique, the modulated output switches
between in-phase and out-of phase component of the carrier for every “one” to
“zero” transitions of modulating signal. The carrier frequency chosen for PSK
modulation are 1MHZ (0 Degree) and 1 MHZ (180 Degree).

The phase detector works ion the principle of squaring loops. First step in PSK
detection is the square wave conversion using a Schmitt trigger. This enables the
PSK detector to be built around digital IC’s. The Bi phase splitter basically doubles
the frequency component of the modulated data and also ensures that the out of
phase component of the modulation signal does not reach the PLL. The PLL
recovers the carrier frequency from the output of the phase splitter, but the
frequency of the recovered carrier is twice that of the transmitted carrier. So
Divide by 2 counter is used to divide the frequency of the PLL output by 2, thus
recovering the reference carrier. The delay flip-flop used to compare the phase of
the incoming data and the reference carrier thereby recovering the data.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 58
BLOCK DIAGARAM:

PROCEDURE:

1. Refer to the block diagram and carry out the following connection and
switch
setting.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 59
 2. Connect power supply in proper polarity to the kits DCL-05 and DCL-06
and
switch it ON.

3. connect CLOCK and DATA generated on DCL-05 to CODING CLOCK IN

and DATA INPUT respectively by means of the connecting-chords
provided.
4. Connect the NRZ-L data input to the CONTROL INPUT of the carrier
modulator logic.
5. Connect carrier component SIN 2 to INPUT1 and SIN 3 to INPUT2 of the
carrier modulator logic.
6. Connect PSK modulated signal modulator output on DCL-05 to the PSK
IN of the PSK demodulator on DCL-06.
7. Observe various waveforms as mentioned below.

OBSERVATION:

Observe the following waveform on CRO and plot it on the paper.

ON KIT DCL-05

A input NRZ-L Data at control input

B Carrier frequency SIN 2 and SIN 3.
C PSK modulated signal at modulator output.

ON KIT DCL-06

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 60
 A PSK Modulated signal at PSK IN.
B PSK Demodulated signal at PSK OUT.
C Observe output of sine to square convertor, squaring loop, divide by 2 on
test point provided.

CONCLUSION:

ASSIGMENT:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 61
 LAB 11

Framing and Marker

AIM: To study of Framing and Marker in Time Division Multiplexing.

1. FRAMING

EQUIPMENTS: Experimental' kit DCL.-09,

Power supply,
20 MHz Dual Trace

APPARATUS: Connecting Chords.

THEORY:

This is an advanced experiment on TDM. This experiment examines the method of

synchronous multiplexing. A ‘FRAME’ plays a vital role in synchronous TDM, which
repeats after ‘T’ seconds. The frame has ‘n’ bits and frame rate is ‘1/T’ frames per
second. The total data rate is ‘n/T’ bits per second. Asynchronous multiplexing
can occupy one or more bits in every frame. A signal occupying one bit per frame
will have a data rate of ‘1/T’ bits per seconds and a signal occupying ‘m’ bits per
frame will have a data rate of ‘m/T’ bits per seconds.

The repetition rate of frame depends upon the channel sampling frequency. Since
we are transmitting audio signal on these channel we should sample at least twice
the highest frequency component in audio signal, which is 4 KHz. This determines
frame frequency of 8 KHz, within the period of 125 micro-secs. We transmit 8
channels; each channel ON period comes to about 125/8 micro-sec. this
corresponds to the frequency of 8 KHz. Lastly we transmit 8 bits per channels,
data rate can be derived as 15.625 micro-sec/8 and 1/1.953125 micro-sec=512
KHz.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 62
NOTE: Keep the switch fault in OFF position.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 63
BLOCK DIAGRAM: Framing in TDM

PROCEDURE:

Refer to the block diagram and carry out the following connection and switch
faults.

1. Connect the power supply with proper polarity to the kit DCL – 09 and
switch it on.
2. Observe frame frequency at FRAME CLK (8 KHz) and slot frequency at MUX
CLK (64 KHz) simultaneously on oscilloscope. Draw the waveforms. You
should get 8 periods of slot frequency. Similarly observe the data clock at
TX DATA CLK (512 KHz) and compare it with the slot frequency at MUX CLK
(64 KHz).

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 64
 3. Observe the multiplexed data at TDM TX. This clearly indicated the frame
pattern as explained above. Compare it with the frame frequency at FRAME
CLK (8 KHz).

CONCLUSION:

ASSIGMENT:

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 65
 2. MARKER

EQUIPMENTS: Experimental' kit DCL.-07,

Power supply,
20 MHz Dual Trace

APPARATUS: Connecting Chords.

.
THEORY:

Marker used in TDM is a unique bit pattern placed at some fixed position in the
frame and is used to determine the start of the frame at the receiver. Some times
a different marker is used in alternate frames to counter the possibility of data
bits containing the marker sequence generating a false marker.

Marker is supposed to be unique bit pattern in the data stream, which is

identified at the receiver to identify the beginning of frame. If the marker pattern
is not matching at receiver section synchronization will not be established.

Individual bits of Marker are available at receiver section, which can be studied by
various patterns of the marker bits.

NOTE: Keep the switch fault in OFF position.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 66
BLOCK DIAGRAM: Marker in TDM

PROCEDURE:

1. Refer to the block diagram and carry out the following connections ad
switch settings.
2. Connect the Power Supply with proper polarity to the kit DCL-09 and switch
it on.
3. Set both the marker with the help of DIP switches SW7 and SW8.
4. Connect SINE OUT post to ANALOG/AUDIO IN post.
5. Keep the sine wave signal amplitude at 2Vpp (P1 completely clockwise) and
frequency at 1 KHz (P2 completely anticlockwise).
6. Connect post TDM TX to post TDM RX.
7. Observe the signal at TDM TX on oscilloscope. Clearly observe the marker
data transmitted in the first sot of each frame. Marker SW& is individually
Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 67
 available at MARKER OUT and marker DETECTION PULSE a receiver only if
marker settings for transmitter and receiver matches.
8. The marker is demultiplexed and detected at the receiver side.
9. Change the setting of the corresponding marker at transmitter or receiver
section switch SW7 or SW8 and carefully observe what effect markers have
on received data (channel indication LED), received marker bits and analog
output at AUDIO OUT post.
10. Marker bits at MARKER TX and MARKER RX can be changed depending
upon marker setting.

CONCLUSION:

ASSIGMENT:

1. What is the significance of framing?

2. What is the use of marker in frame?
3. What if the marker bits are not same at transmitter and at receiver?

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 68