University of Nottingham Malaysia Campus

Department of Electrical and Electronic Engineering

H62ELD Electronic Engineering

Computer Aided Design Laboratory – Stage 2

1 Objectives

The objectives of the second stage of this laboratory are to:

• develop further your design skills in synchronous sequential logic, using both
schematic entry and VHDL
• gain further experience of solving digital design problems, using a CAD tool
• develop further your report writing skills.

Counters are a class of circuit that are able to count input pulses and produce an output
which is determined by the number of pulses which have occurred at the clock input. For
example; a decade counter will count from zero to nine and output a four-bit number
between zero and nine, further input pulses will cause it to cycle through the sequence
again. However, a four bit binary counter will count from zero to fifteen before cycling
round the count. With suitable inputs and outputs counters may also be cascaded to
increase the length of the count. For a typical TTL 4-bit counter look at a 74ALS193A.

The second stage of the CAD laboratory involves the design of counters using both
schematic entry and VHDL. You should come to the laboratory session with a finished
design ready to do the schematic entry or VHDL coding. If you do not do this then you
will not have time to complete the work. You are also encouraged to use the laboratory
outside the supervised laboratory sessions.

2 Schematic

The first part of this stage of the CAD laboratory involves the design and schematic entry
of a positive edge triggered 3-bit synchronous up/down counter. This part should not be
solved using VHDL. The counter should count from zero through to seven and the
direction of the count is determined by an
external input U/D . If U/D = 1 the count
is in an upward direction ie 1, 2, 3, …, if U/D
U/D = 0 then the count is downwards ie
6, 5, 4, … The counter should be designed Clock:
such that if the direction changes during a
count, for example when the count is five,
the counter should just change direction Count: 3 4 5 4 3
as shown in figure 1. The design should be
implemented using D-type latches as the Figure 1 Three-bit counter
memory element.

D-type Latch

There are several D-type latches in the CAD tool library, choose one which is appropriate
for your needs (don’t forget the need for the circuit to start correctly).

When you have entered the design, you will be able to simulate your design and verify
its operation (use both functional and post-layout simulations). Explore what happens as
the clock frequency is increased.

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3 VHDL

The second and major part of this stage is a graded exercise with a number of objectives
of increasing sophistication. It is not expected that all students will complete all the
objectives. You are strongly advised to ensure that one section is complete and verified
as working correctly before moving on to a more sophisticated section.

The exercise is based on a 16-bit counter and the objectives are as follows:

1. A basic +’ve edge triggered 16 bit binary counter.

2. As 1 but with the ability to change count direction using an U/D input (ie a 16 bit
version of part 1).

3. As 2 but with an asynchronous active low clear input ( CLR ). When CLR = 0 the
count should be set to zero. When CLR = 1 the count should proceed in the
direction determined by U/D .

4. As 3 but with an output ( ZERO ) which is 0 when the count is equal to 0 and 1 at
all other times.

For each objective you should use the simulator to demonstrate that your design meets
the specification using both functional and post-layout simulations. Stage 2 Report

The report for this exercise should cover all stages of the laboratory.

For part 1 show how you have designed the circuit for the 3-bit up/down counter, the
final circuit obtained and the simulations that verify your design. You should also explore
what happens to your circuit when the U/D input is changed between 0 and 1.

For part 2 you should provide a complete VHDL listing for the objectives which you were
able to verify. This should be accompanied by an explanation of how you have
implemented the design. However, the focus should be on demonstrating that your
design meets the specification for all objectives completed.

Report Structure

The report should be structured as a formal laboratory report with a title page, an
abstract of about 200 words and an introduction. The main body of the report should
contain the details of the designs and simulations in stages 1 and 2. These should be
followed by a discussion of your results and conclusions drawn. Marks will be awarded
for presentation and the standard of English. Please pay particular attention to figure
numbers and captions as well as references.

In your discussion you should compare schematic entry with VHDL. I would also
appreciate any suggestions that you have for improving the CAD exercise.

Department of Electrical and Electronic Engineering

Other aspects

While it is acceptable and encouraged for students to work in groups and to discuss the
design, an individual design and report are required. Your report should reflect your
work, anything which is the work of others or which others have contributed to should be
duly referenced and you are referred to the School and University guidelines on
plagiarism (for further details see:
http://www.nottingham.edu.my/students/MISC/UGHB.pdf
http://hermes.eee.nott.ac.uk/current/Handbook/plagiarism.htm
http://www.nottingham.ac.uk/quality-manual/assessment/offences.htm ).

Overall, the length of your report, excluding figures and appendices, should not exceed
about ten pages of A4. This length is a guideline not a fixed target; you should aim for
quality not quantity.

The normal laboratory hand-in rules apply to this report. It should be handed in at the
end of 1 week after your last timetabled CAD laboratory. The usual penalty of 5% per
working day will be applied for late submission.

Submit the paper copy of your report to the Faculty Office as the receipt from this will be
used to confirm submission date.

Department of Electrical and Electronic Engineering