Organic Electronics 8 (2007) 431–438

www.elsevier.com/locate/orgel

Device and circuit simulation of printed polymer electronics

a,*
Matthias Bartzsch , Heiko Kempa b, Michael Otto c, Arved Hübler a,
Dirk Zielke d
a
Chemnitz University of Technology, Institute for Print and Media Technology, Reichenhainer Strasse 70, D-09107 Chemnitz, Germany
b
Fraunhofer Institute Reliability and Microintegration, Branch Lab Chemnitz Reichenhainer Strasse 88, D-09126 Chemnitz, Germany
c
Printed Systems GmbH Altchemnitzer Strasse 27, D-09120 Chemnitz, Germany
d
University of Applied Sciences Bielefeld, Department of Electrical Engineering and Information Technologies,
Wilhelm-Bertelsmann-Strasse 10, D-33602 Bielefeld, Germany

Received 23 October 2006; received in revised form 8 February 2007; accepted 13 February 2007
Available online 20 February 2007

Abstract

For the electrical simulation of all printed polymer circuits an AIM-SPICE model was developed, which is based on an
a-silicon approach. By fitting the parameters to the behaviour of our polymer devices, we obtain a model, which allows to
model all-printed polymer transistors and circuits.
 2007 Elsevier B.V. All rights reserved.

PACS: 72.80.Le; 85.40.e; 85.30.Tv

Keywords: Organic electronics; Printed electronics; Device simulation; Organic field effect transistor (OFET)

1. Introduction most promising in this context, as their main advan-

The technology for printed organic electronics
has rapidly developed in recent years. First devices
and circuits for applications like RFID have been
presented [1,2]. Due to intrinsic drawbacks of
organic materials compared to their inorganic coun-
terparts in terms of electronic properties, future
applications are foreseeable in fields where low-cost
manufacture is more important than extremely high
performance [3]. Mass printing technologies are
*
Corresponding author. Tel.: +49 (0) 371 531 32126; fax: + 49
(0) 371 531 23619.
E-mail address: matthias.bartzsch@mb.tu-chemnitz.de (M.
Bartzsch).
tage compared to other fabrication methods, e.g.
lithographic structuring used in silicon-based indus-
try, is the possibility to produce a huge amount of
samples with one printing form [4].
To avoid a ‘‘trial and error strategy’’ which
would involve the fabrication of many different
printing forms, it is helpful to have some reliable
and easy to use simulation tools for printed circuits
at hand. By means of simulations the device and cir-
cuit layout can be verified and optimized without
performing a large number of cost and time con-
suming experiments. In order to support our daily
work in roll-to-roll printing of organic circuits, we
have developed an easy to use and easy to parame-
terize model which describes the static and dynamic

1566-1199/$ - see front matter  2007 Elsevier B.V. All rights reserved.
doi:10.1016/j.orgel.2007.02.005
432 M. Bartzsch et al. / Organic Electronics 8 (2007) 431–438
behaviour of organic devices and circuits with suffi-
cient accuracy.
2. Experimental
Our transistors and circuits were fabricated solely
by means of fast, continuous mass-printing pro-
cesses on a printing machine which was especially
designed and set up for the purpose of printing elec-
tronic devices (Fig. 1). The machine is capable of all
conventional mass-printing techniques due to its
modular setup, i.e. offset, flexographic and gravure
printing and has a small web width of 35 mm in
order to work with small amounts of experimental
materials.
The thin-film transistors (TFTs) are built up in
top-gate configuration on a PET-substrate. Source
and drain electrodes are offset printed from a
re-formulation of a water-based dispersion of poly-
(3,4-ethylenedioxythiophene) doped with poly-
(styrene-sulfonate) (PEDOT:PSS, Baytron P).
Poly(9,9-dioctylfluorene-co-bithiophene) (F8T2)
solved in xylene was gravure printed as semicon-
ducting layer. For the gate dielectric a double layer
approach with a low-k and a high-k dielectric was
used [5]. Veres et al. [6] found that a semiconduc-
tor/low-k dielectric interface shows superior proper-
ties in terms of field effect mobility compared to
semiconductor/high-k dielectric interfaces. This
effect has also been observed in our device setup
[5]. However, due to the high roughness of our
source/drain structures, an additional layer of a
Fig. 1. Laboratory printing machine for the fabrication of all-
printed electronic devices.
high-k dielectric material has been deposited on
top of the low-k dielectric in order to guarantee suf-
ficient insulation and capacitance. A combination of
gravure and flexographic printing processes was
used to deposit the dielectrics. The gate electrodes
were manually dispensed from carbon black. Details
of the involved printing processes will be described
elsewhere [7].
The transistors had a channel length of 100 lm
and a channel width of 30,000 lm. In order to dem-
onstrate the applicability of our model for logic cir-
cuits we have chosen a seven-stage ring oscillator as
a demonstrator (Fig. 2). The ring oscillator incorpo-
rated eight inverter stages, where one of them was
used as a buffer stage for uncoupling of the signal.
Each inverter stage consisted of a load and a drive
transistor with a channel width of 6000 lm and
30,000 lm, respectively. The channel length was
100 lm for both the load and the drive transistor.
Standard characterizations of the individual
TFTs and inverter stages were carried out using
two Keithley source meters, whereby the measured
transistors and inverters, respectively, were electri-
cally separated from the surrounding circuitry.
The ring oscillator signal was traced with a Keithley
source meter controlled by an appropriate software,
making use of its large input impedance. All mea-
surements were carried out in a Suess Microtech
probe station.
Fig. 3 shows the output characteristics variation
of the D-TFTs of an oscillator circuit. The variation
of approx. 25% in the output characteristics is
mainly a consequence of two effects. The first one
is the non-uniformity of the semiconducting layer
which causes voids because of wetting problems.
Because of this effect the effective channel width is
reduced. The second effect that influences the varia-
Fig. 2. Circuitry of the seven-stage ring oscillator (top) and
schematic of a printed ring oscillator (bottom).
 M. Bartzsch et al. / Organic Electronics 8 (2007) 431–438 433

printed TFTs with an a-silicon model developed

by Lee et al. [15]. It is based on the assumption that
the drain current ID is composed of two contribu-
tions, i.e.
I D ¼ I leakage þ I ab ð2Þ
One of them is due to the accumulation of carriers
(Iab), while the other one is due to the intrinsic con-
ductivity of the organic semiconductor (Ileakage). An
inversion of carriers is not included in this model as
this effect is not observed in a-silicon as well as in
organic semiconductors.
Fig. 3. Output characteristics of the D-TFTs at VGS = 60 V. The accumulation current Iab can be calculated
from the carrier concentration ns. The carrier con-
centration ns is composed of the free carrier concen-
tion of transistor characteristics is the variation in tration nsa and the carriers from deep traps nsb
the thickness of the insulating layer. nsa  nsb
ns ¼ ð3Þ
nsa þ nsb
2.1. Device model
In order to calculate the free carrier concentration,
For the simulation of the behaviour of organic the carrier equilibrium approach is used
field effect transistors (OFETs) usually a common  GAMMA
e0 er  V gte V gte
set of equations known as gradual channel (or nsa ¼ ð4Þ
e  tox VAA
Shockley) approximation is used. Within this frame-
work, the drain current (ID) can be described as where e is the elementary charge, VAA the charac-
function of the drain/source voltage (VDS) and the teristic voltage for field effect mobility and GAM-
gate/source voltage (VGS): MA the power law mobility parameter. Vgte is
8 given by
>
> 0 jV DS j < jV TH j
>
>
>
  2 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3
< e0 er W V DS  2
l  V DS V GS  V TH  jV GS  V TH j > jV DS j VMIN 4 V gt V gt
ID ¼
>
tox L 2 V gte ¼ 1þ þ DELTA þ 2
1 5
>
> e0 er W 2 VMIN VMIN
>
> 2
:l    ðV GS  V TH Þ jV GS  V TH j < jV DS j
tox 2  L
ð5Þ
ð1Þ
where VMIN is the convergence parameter, DEL-
where l is the mobility, tox and er the thickness and TA the transition width parameter and
relative dielectric constant of the gate oxide, VTH
the threshold voltage and W and L are the channel V gt ¼ V GS  V TH ð6Þ
width and length. In order to determine the trap carrier concentration
This model describes the above threshold region nsb a special approach for a-silicon [15] is used. The
well, as long as the source/drain-contact exhibits conductivity of the channel gchi can be calculated
ohmic characteristics [8]. However, for the sub- using the carrier concentration ns,
threshold behaviour of an OFET the parasitic
effects like surface traps and gate-voltage-dependent gchi ¼ e  ns  W  l=L ð7Þ
mobility have to be considered.
Taking into account the resistance of the drain and
A number of physical approaches which describe
source areas (RD and RS), the effective conductivity
the carrier concentration in different organic semi-
gch is given by
conductors have been reported [8–11]. However,
the parameters for these models are hard to deter- gchi
gch ¼ ð8Þ
mine and the models are unhandy for circuit simu- 1 þ gchi ðRS þ RDÞ
lations. On the other hand, there are papers, so that the contribution of the drain current Iab can
which show that the behaviour of organic semicon- be written as
ductors is similar to that of amorphous silicon [12–
14]. For this reason we attempt to describe our I ab ¼ gch V dse ð1 þ LAMDA  V ds Þ ð9Þ
434 M. Bartzsch et al. / Organic Electronics 8 (2007) 431–438

with
V DS
V dse ¼  ð10Þ
M 1=M
1 þ ðV DS =V SATE Þ
and
V SATE ¼ ALPHASAT  V gte ð11Þ
where LAMBDA is the output conductance param-
eter, M the knee shape parameter and ALPHASAT
the saturation modulation parameter.
The leakage current Ileakage is due to the intrinsic
conductivity of the organic semiconductor and can
be described as Fig. 4. Mean value of the mobility of the D-TFTs as a function
of the gate voltage.
I leakage ¼ SIGMA0  V DS ð12Þ
where SIGMA0 is the minimum leakage current Table 1
parameter. Fitted model parameters
Parameter Value Description
2.2. Parameter extraction l 1.66 · 103 cm2/Vs Mobility
Alphasat 0.48 Saturation modulation
The simulations of our devices were carried out parameter
Lambda 0.0042 V1 Output conductance
using the Spice-version of AIM-Software. The soft-
parameter
ware includes various TFT models for amorphous M 2.88 Knee shape parameter
as well as for poly-silicon. For our purpose the Defo 0.6 eV Dark fermi level position
AFET 15 model was used, which was originally VFB 65.60 V Flat band voltage
developed for amorphous silicon TFTs. V0 0.14 V Characteristic voltage for
deep states
The parameters for the AFET 15 model were
VTH 2.97 V Threshold voltage
determined in two steps. Firstly, the mobility was SIGMA0 1.19 · 103 A Minimum leakage current
calculated from the measured output and transfer parameter
characteristics. In order to do so, the mobility is
derived from Eq. (1):
With these values, a good agreement between
oI DS L
l¼ for jV GS  V TH j > jV DS j ð13Þ simulation and experimental results could be
oV G WC i V DS achieved. Figs. 5 and 6 show the output and transfer
and characteristics, respectively, of the F8T2-model-
 pffiffiffiffiffiffiffi2 TFT and the means of the measured values of the
o I DS 2L
l¼ for jV GS  V TH j < jV DS j drive transistors.
oV G WC i
ð14Þ
The mean value of the mobility of the D-TFTs
is shown in Fig. 4. The mobility strongly depends
on the gate voltage, a behaviour which is often
reported for organic [16,17] as well as for a-silicon
[11] TFTs.
In a second step the parameter extractor of AIM-
Spice was used to fit the whole parameter set for the
AFET 15 model. While the AFET 15 model is valid
for n-semiconductors, it had to be taken into
account that F8T2 is a p-type semiconductor, i.e.
all currents and voltages had to change sign. The
obtained values for the fit parameters are summa- Fig. 5. Simulated and measured output characteristics of a
rized in Table 1. typical D-TFT.
 M. Bartzsch et al. / Organic Electronics 8 (2007) 431–438 435

Table 2
AFET 15 model parameter fit for a F8T2 transistor
Parameter Value
RI 198 kX m2
CI 7.1 lF/m2
SigmaI 3.97 · 1013 A

Fig. 6. Simulated and measured transfer characteristics of a

typical D-TFT.

2.3. Circuit simulations

For the purpose of circuit simulations the TFT-

model was extended with parasitic gate/source and
gate/drain resistors and capacities in order to
describe the non ideal organic insulator (Fig. 7).
Furthermore it was necessary to parameterize the
leakage current.
In order to calculate the parasitic elements as
functions of the channel width and length, the fol- Fig. 8. SPICE model for an inverter with F8T2-TFTs.
lowing linear approaches were used
C GS ¼ C GD ¼ C I  W  F ð15Þ
RI
RGS ¼ RGD ¼ ð16Þ
W  ðF þ LÞ
W
SIGMA0 ¼ sigmaI ð17Þ
L
Here, W, L and F are the channel width and length
and the finger width, respectively of the TFT. The
obtained fit parameters are summarized in Table 2.
Using the described transistor model, a single
inverter stage was simulated. The SPICE model of
an inverter is shown in Fig. 8. Fig. 9 shows the sim- Fig. 9. Measured inverter transfer characteristics and simulations
with different load resistances.
ulated as well as the measured characteristics.
Although the agreement of the simulation with the
experimental results is satisfactory, unfortunately there is a large variation of the characteristics
among different inverters, which is due to the varia-
tion of the transistor characteristics (see Fig. 3).
However, it can be seen from Fig. 9 that the H-level
of the inverter is strongly depending on the output
load. Obviously, an 11 GX load resistance is
approx. equal to the input resistance (which is deter-
mined by the gate/source resistance) of a following
inverter stage.
The results of a simulation of a chain of 7 inter-
connected inverters are shown in Figs. 10 and 11 for
supply voltages of 40 and 80 V, respectively.
Fig. 7. Equivalent circuit of the F8T2-TFT. Simulated transfer characteristics after the 1st,
436 M. Bartzsch et al. / Organic Electronics 8 (2007) 431–438
Fig. 10. Transfer characteristics of 7 interconnected inverters at
USS = 40 V.
Fig. 11. Simulated transfer characteristics of 7 interconnected
inverters at USS = 80 V.
2nd, . . ., 7th inverter stages are plotted. For com-
parison, the measured characteristics after 7 invert-
ers is included in Fig. 10.
For a supply voltage of 40 V (Fig. 10) there is
hardly any interval in which the inverter gain (the
slope of the output characteristics, dVout/dVin) is
higher than 1. Therefore, the inverter chain does
not work as an amplifier and no oscillation can be
sustained. This situation is different for a supply
voltage of 80 V (Fig. 11). Here the output swing
of inverter 7 is higher than the input swing (the gain
is higher than 1) within the input voltage range of
12 to 52 V. In this interval the amplification
after all inverter stages is higher than one (the max-
imum gain is about 10) and, thus, if the output of
Fig. 12. CV-measurement of the gate capacitance of a typical D-
TFT.
inverter 7 is fed back into the input of inverter 1,
the circuit is oscillating with this amplitude (see
Fig. 13). Provided that the amplification of the
inverter chain is greater then one, the oscillator fre-
quency is strongly dependent on the gate capaci-
tance, which results from two contributions. One
contribution is the overlap capacitance between
the gate and the drain/source electrode structures
and the second contribution is the gate-channel
capacitance. Fig. 12 shows the quasistatically mea-
sured gate capacitance of a typical D-TFT. It can
be seen that the capacitance is strongly dependent
on the gate/source-voltage. However, the low gate
capacitance at positive gate voltages reflects the
overlap capacitance, whereas the increase of the
gate capacitance towards negative gate voltages is
due to the channel capacitance, which increases
upon accumulation of charge carriers.
The initial increase of the capacitance when mea-
sured towards positive gate voltages (circles in
Fig. 12) is due to a measurement artifact which is
based on the initial load of the capacitor during
the start phases. This initial load to a voltage of
60 V has not been completely finished, when the
CV-measurement is started. Thus, the first measure-
ment points are corrupted by the initial load cur-
rent. Another artifact is the significant decrease
for higher (positive) voltages which can not be
explained yet and is also not seen in simulation.
Nevertheless, the simulated CV-curve, which is also
plotted in Fig. 12, is in reasonable agreement with
the experimental data, at least for negative gate
voltages. This result confirms our approach to use
the a-silicon trap distribution model [15].
Using the F8T2 transistor model we were able to
simulate the printed ring oscillator circuit and pre-
dict the supply voltage that is needed for the oscilla-
 M. Bartzsch et al. / Organic Electronics 8 (2007) 431–438 437

Table 3
Comparison of simulated and measured frequency and amplitude
of a seven-stage ring oscillator
Supply Simulated Measured
voltage
RL = 1 RL = 1 GX
f in VO, PP f in VO, PP f in VO, PP
Hz in V Hz in V Hz in V
40 V – – – – – –
60 V 1.1 20 1.2 11 1.1 11
80 V 1.8 35 2.1 25 2.5 17

3. Conclusions

We have developed an easy to use model in order

Fig. 13. Spice simulation of a 7 stage ring oscillator for different to describe the behaviour of printed organic circuits
supply voltages for RL = 1. which is based on an existing model for a-silicon
[15]. With the model it is possible to simulate device
parameters of printed transistors and inverters with
tion. In Fig. 13 the simulated output signal is
high accuracy. Furthermore, more complex circuits
shown. The amplitude of the oscillation is in a good
can be easily simulated both in terms of static and
agreement with the prediction from the static simu-
dynamic behaviour. Qualitative agreement with
lations (see Figs. 10 and 11). However the amplitude
experimental data is obtained in this case, however
of the measured output signal is lower (Fig. 14). The
some quantitative deviations occur which are sub-
reason for this deviation could be an input resis-
ject to future study. We have also used the model
tance of our measurement equipment, which we
for devices based on poly(3-hexylthiophene)
estimate to be approx. 1 GX. This load on the out-
(P3HT) and poly(triarylamin) (PTAA) with similar
put of the oscillator can be responsible for the lower
results.
oscillation amplitude and a slightly higher
Future development of circuit simulation should
frequency.
be aimed at the requirements of the fabrication of
Table 3 shows the simulated and measured fre-
more complex circuits. Furthermore, it is desirable
quencies and amplitudes of our ring oscillator for
to model the trap-behaviour with a specific poly-
different load resistance. A reasonable agreement
mer-related approach, taking advantage of the
between simulated and measured values can be
parameters having a physical background and thus
observed.
allowing for an understanding of the interrelation
of technological changes and parameter variations.

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