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ECEN 665

Edgar Sánchez-Sinencio

Low Noise Amplifier


LNA

Part of the material here provided is based on Dr. Chunyu Xin’s dissertation
Ideal characteristics of LNA in Receivers

‡ min F
‡ Large voltage gain to reduce Ftot
‡ Handling large signals without significant distortion
‡ must present 50 ohms to the input source

Real characteristics of LNA in Receivers


• F and power consumption trade-offs P
F
• Gain and input matching trade-offs Zin
G

Analog and Mixed-Signal Center, TAMU 2


Practical Requirements of LNA in Receivers
‡ Signal coming from antenna is very small: -
100dBm(3.2uV)~-70dBm(0.1mV), amplification is needed for
the following stage (mixer) to handle a reasonable signal
magnitude. (Gain requirement)
‡ The received signal should have certain SNR to be reliable
detected. Noise comes from the environment and the circuit
itself. Noise floor is determined by thermal noise and system
bandwidth (KTB). Noise added by the LNA circuit should be
as small as possible. (Noise requirement).
‡ Large signal or blocker can occur at the input of LNA. Large
signal performance of LNA should be good enough. (Linearity
requirement)
‡ Reasonable ( or minimum) power consuming (Power constrain)
Analog and Mixed-Signal Center, TAMU 3
A Conceptual LNA Structure

LNA consists of: Important terms:


Amplifier S matrix:
‡ Input/output match network Source reflection coefficient: Γs
[S ] = ⎛⎜⎜ 11 21 ⎞⎟⎟
s s
‡ Amplifier transistor (s) Load reflection coefficient: ΓL ⎝ s12 s22 ⎠

‡ Power source Input reflection coefficient: Output reflection coefficient:


s12 s21ΓL s s Γ
Γout = s22 + 12 21 s
‡ Load Γin = s11 +
1 − s22ΓL 1 − s11Γs

Analog and Mixed-Signal Center, TAMU 4


Remarks on LNAs:
NFrec-front = (1/GLNA) (NF subsequent -1) + NFLNA

‡ Narrow band (NB) LNA are typically used in Wireless Commercial


Communications, i.e. Bluetooth, Wi-Fi, GSM.

‡ For NB the impedance matching and power gain are usually optimized
at one frequency. The output load stage and the input matching usually
involve LC networks.

‡ For wide band LNA the input matching stage and load are
optimized for a frequency band, thus the input matching and load
impedance behave as low-Q ( wide bandwidth) filters

Analog and Mixed-Signal Center, TAMU 5


LNA Metrics: Gain
‡ Gain is the ratio of output signal and input signal. It defines and
small signal amplification capability of LNA.

‡ For IC implementation, LNA input is interfaced off-chip and usually


matched to specific impedance (50ohm or 75ohm). Its output is not necessary
matched if directly drive the on-chip block such as mixer. This is characterized
by voltage gain or transducer power gain by knowing the load impedance level.

‡ Transducer power gain: Power delivered to the load divided by power


available from source.

1 − Γs 1 − ΓL
2 2
For unilateral device
GT =
2
s21 i.e. S12~0
1 − s11Γs 1 − s22 ΓL
2 2

Analog and Mixed-Signal Center, TAMU 6


LNA Metrics: Two-Port Noise Figure
‡ Noise factor (NF) is defined by the ratio of output SNR and input
SNR. Noise figure (F) is the dB form of noise factor.
‡ Noise figure shows the degradation of signal’s SNR due to the
circuits that the signal passes.
SNRi
F= NF (dB) = 10 log F
SNRo
Rn 2
F = Fmin + Ys − Yopt
Gs
Rn is a fictitious resistance called optimum noise resistance
LNA noise matching:
The source impedance 1/Ys of the LNA can be transformed to
an optimal value such that the noise figure is minimum.

Analog and Mixed-Signal Center, TAMU 7


Notation for the Noise Figure

Gs is the source conductance,


Rn is a fictitious noise resistance ,
Gu is the equivalent ( fictitious) uncorrelated noise conductance
Thus one can write the noise factor as:

F= 1+ (Gu/Gs) +(Rn/Gs)[ (Gs+Gc)2 +(Bs+Bc)2 ]

Note that Gs and Bs can be changed independently. i.e.


Bs= -Bc = Bopt

Analog and Mixed-Signal Center, TAMU 8


Minimum Noise Figure

BS = − Bc = Bopt
Gu
GS = + GC = Gopt
2

Gn
Fmin = 1 + 2 Rn [Gopt + GC ]
Detail NF expressions are given in the next pages.

Analog and Mixed-Signal Center, TAMU 9


LNA Metrics: Why are gain and low noise critical?

Sensitivit y = Noisefloor ( dBm ) + SNR + NFtot


-174dBm+10logBW

System SNR is determined by Noise factor of cascaded system:


BER requirement of a specific FafterLNA − 1
modulation scheme, for example: Ftot = FLNA +
G LNA
1e-3 1e-6 ‡ LNA’s noise factor directly appears in
QPSK 7dB 11dB the total noise factor of the system.
16QAM 12dB 16dB
‡ LNA’s gain suppress the noise coming
64QAM 17dB 21dB from following stages

Analog and Mixed-Signal Center, TAMU 10


ELEN 665 (ESS)
TWO-PORT NOISE COMPONENTS
vn
iin iout
Noiseless
ins Ys in Network.
Current
Gain = Ai

N o ,total 2 = i 2ns + in + Ys vn ; N o ,source = i 2ns


2

i +Y v
2
N
F = o ,total = 1 + n 2 s n
N o ,source ins

where in and vn are partially correlated

in = ic + iu ; ic = Yc vc
vn = vc + vu

Analog and Mixed-Signal Center, TAMU 11


Then
i u2 + Yc + Ys vn2
2
iu2 + Yc + Ys vc2 + vu Ys
2 2 2

F =1+ 2
=1+
ins ins2
in2 2 vc
2
vu2
+ Yc + Ys +
2
Ys
F = 1 + 4kTB 4kTB 4kTB
ins2
4kTB
G + Yc + Ys Rc + Ru Ys G + Yc + Ys Rn
2 2 2

F =1+ u =1+ u
Gs Gs
where
iu2 vc2
Gu = , Rc =
4kTB 4kTB
vu2 ins2
Ru = , Gs =
4kTB 4kTB
and
vn2
Rn =
4kTB

Analog and Mixed-Signal Center, TAMU 12


Yc ,s = Gc ,s + jBc ,s , then

F =1+
[ 2 2
]
Gu + (Gc + Gs ) + (Bc + Bs ) Rc + (Gs2 + BS2 )Ru
Gs
Optimal source admittance :

Now if
∂F ∂F
= 0 and =0
∂Gs ∂Bs
Bopt = − Bc = Bs
Gu
Gopt = Gs = + Gc2
Rn
then
⎡⎛ G ⎞
12

Fmin = 1 + 2 Rn [Gopt + Gc ] = 1 + 2 Rn ⎢⎜⎜ u
+ Gc ⎟⎟ + Gc ⎥
2

⎣⎢⎝ n ⎠ ⎥⎦
R

Analog and Mixed-Signal Center, TAMU 13


F = Fmin +
Rn
Gs
[
(Gs − Gopt )2 + (Bs − Bopt )2 ]

For the MOSFET noise model, we have to take into account two sources.

2 4kTγg do B
i 2
nd = 4kTγg do B ; v nd = ; γ = 2 3 for saturation and long channels
g m2
2 ω2C gs
i ng = 4kTγg g B ; g g =
5 g do

Correlation coefficient
*
ing ind
c=
[i 2
ng
2
⋅ i nd ]
12

vn2 γg
Rn = = 2do
4kTB g m

Analog and Mixed-Signal Center, TAMU 14


ingc gm δ
Yc = jωC gs + g m = jωC gs + c ωC gs
ind g do 5γ
⎛ δ ⎞
Yc ≅ jωC gs ⎜⎜1 − α c ⎟⎟ = jBc
⎝ 5γ ⎠
Gc ~ 0
γg do γ 1
Rn = =
g m2 α gm

Gu =
(
δω2C gs2 1 − c
2
) ; ωT ≅
gm
5 g go cgs
Bopt = − Bc
Yopt = Gopt + jBopt = Gopt − jBc

Gopt =
Gu
Rn
+ Gc2 = αωC gs
δ

1− c
2
( )
Fmin = 1 + 2 Rn [G opt +Gc ] ≅ 1 +

5ωT
(
γδ 1 − c
2
)
Analog and Mixed-Signal Center, TAMU 15
LNA Metrics: Non-linearity model
f1 f 2
f1 f 2 f1+f2
f2-f1 2f1-f2 2f2-f1
2f1 2f2

In-band blocker
Output spectrum with two tone input -23dBm
Wanted Signal
-102dBm
‡ Usually distortion term: 2f1-f2, 2f2-f1
fall in band. This is characterized by 3rd IM3
order non-linearity. f=2f1-f2
‡ Large in-band blocker can desensitize
the circuit. It is measured by 1-dB f 1 f2
compression point.

Analog and Mixed-Signal Center, TAMU 16


LNA Metrics: Linearity measurement
‡ 1dB compression: Pout (dB)
1dB
P1dB@output
Measure gain compression for large input signal
‡ IIP3/IIP2:
Measure inter-modulation behavior Pin (dB)
P1dB@input
‡ Relationship between IIP3 and P1dB
Pout (dBm)
OIP2
For one tone test: IIP3-P1dB=10dB
OIP3
For two tone test: IIP3-P1dB=15dB

l
ta
en
IIP3~ -10dBm~8dBm

am
nd
Fu
IM3 IM2
Pin(dBm)
IIP3 IIP2

Analog and Mixed-Signal Center, TAMU 17


CMOS LNA Topologies
Resistive Termination Common Shunt-series Source
Gate Feedback Degeneration
VDD
VDD

VDD
ZL ZL
OUTPUT
OUTPUT
VBB VDD RL
M2
Rf
VBB
OUTPUT

VBB
INPUT RL
M1
M1 Lg
INPUT
Rs
M1 INPUT
INPUT OUTPUT C1
R1

Ls
1
Z in = Rs Z in =
g m1 Rf
Z in ≈
Z in = jω (Lg + Ls ) +
1 g
4γ R + m Ls
F ≥ 2+
1 γ 1+ L jωC gs C gs
α g m1 Rs F ≥ 1+ R1
α
NF: > 6dB 4.8dB Moderate < 2dB

Analog and Mixed-Signal Center, TAMU 18


LNA Topologies (cont’d)

‡ Narrowband LNA: inductive degenerated


‡ Broadband LNA: common-gate and series-shunt feedback
‡ Bipolar LNAs also have corresponding configurations

Focusing on inductive degenerated LNA


‡ Input match
‡ Noise match
‡ Linearity

Analog and Mixed-Signal Center, TAMU 19


A Popular Narrow Band LNA:
Inductive Source Degenerated LNA

Analog and Mixed-Signal Center, TAMU 20


Source Degenerated LNA
Input impedance
VDD

Z in = jω (Lg + Ls ) +
1 g
+ m Ls ZL
jωC gs C gs OUTPUT

VBB
1 g
ωo = ωT = m
(Lg + Ls )Cgs C gs
Lg
Z o = ωT Ls
INPUT
Cgs

Zo: 50Ohm, 75Ohm Ls

Wo: 900MHz, 1.9GHz, 2.4GHz, 5GHz

Analog and Mixed-Signal Center, TAMU 21


SOURCE DEGENERATED LNA ANALYSIS

Io
Lg Vin Lg Io

s Zin Cgs gmVgs


Iin
Ls
Ls
Writing KCL and KVL
1 g
I o = g mVgs = I in × g m = m I in (1)
sC gs sC gs
⎡ 1 ⎤
Vin = ⎢ s (Lg + Ls ) + ⎥ I in + I o sLs (2)
⎣ sC gs ⎦
Solving (1) and (2)
V 1 g L LG+Ls
Z in = in = s( LG + LS ) + + m s
I in sC gs C gs Cgs g m Ls
⎡ Zin
1 ⎤ g m LS C gs
Z in ( jω) = j ⎢(LG + LS )ω − ⎥+
⎣ ωC gs ⎦ C gs

Analog and Mixed-Signal Center, TAMU 22


Matching occurs when Z(jωo)=Rs , Rs is the resistor associated in the input
voltage source. That is

1 1
(LG + LS )ωo = ; ωo2 =
ωoC gs (LG + LS )Cgs
and
g m LS
Rs =
C gs
which implies that :
1
LG = 2 − LS
ωoC gs

Analog and Mixed-Signal Center, TAMU 23


Source Degenerated LNA (cont’d)
Input impedance-non-idealities
Z in = jω (Lg + Ls ) +
1 1
+ + ωT Ls + RLg + Rg + RLs + Rg , NQS
jωC gs jω 1
ωT RLs
1
ωo = gm
ωT =
(Lg + Ls )⎛⎜⎜ C gs // ω 1R ⎞ Lg RLg
⎟⎟ C gs
⎝ T Ls ⎠
Cgs
Z in = ωT Ls + RLg + Rg + RLs + Rg , NQS

Inductance loss: RLg: offset Zin Ls


R poly , shW
RLs: offset Zin and w0 Rg = 2
ZIN RLs
12n L
Gate resistance Rg: offset Zin
1
NQS gate resistance: Rnqs: offset Zin Rg , NQS =
5g m

Analog and Mixed-Signal Center, TAMU 24


Source Degenerated LNA (cont’d)
Noise factor

RL Rg γ χ ⎛ ωo ⎞
F = 1+ + + ⎜⎜ ⎟⎟ Lg RLg
Rs Rs α QL ⎝ ωT ⎠
ωo (Ls + Lg )
Cgs
1
QL = =
Rs ωo Rs C gs Ls

δα 2 δα 2
χ = 1 + 2 c QL

+

(
1 + QL2 )
ZIN RLs

There is a optimal QL to minimize F


Is this F the minimum achievable one?
D.K. Shaeffer, T.H. Lee, “A 1.5V 1.5GHz CMOS Low Noise Amplifier”, IEEE JSSC, Vol. 32, No. 5. May 1997

Analog and Mixed-Signal Center, TAMU 25


Source Degenerated LNA (cont’d)
Achieve minimum noise figure: trading input match

Rn 2
F = Fmin + Ys − Yopt
Gs

Inductive Source degeneration:


The degeneration inductance modifies the input reflection coefficient
without affecting the optimal input reflection coefficient for minimum
noise figure.

Analog and Mixed-Signal Center, TAMU 26


Source Degenerated LNA (cont’d)
Linearity Different width of transistor

IIP3 (dBm)
V 2
=
4 Veff
(2 + θVeff )(1 + θVeff ) > 8 Veff 20
3 θ 3 θ
IIP 3, strong , MOS

1 16
Veff = VGS − Vth θ=
Esat L 12

‡ IIP3 independent of W 8

4
3
16 PD2 ⎛ 1⎞
( )
0
V 2
(V ) =
2
2 + ρ ⎜⎜1 + ⎟⎟
3 Po θ ⎝ ρ⎠
IIP 3, LNA 2 2
-4

-8
3 vsat Esat
ρ = θVeff Po = VDD 0.4 0.5 0.6 0.7 0.8 0.9 1

2 ωo Rs VGS
MOS transistor’s IIP3 v.s. gate drive voltage
Esat ~ 1V/um L~0.35um-0.18um

Analog and Mixed-Signal Center, TAMU 27


Source Degenerated LNA (cont’d)
Differential v.s. Single-ended

Single-ended
Differential
9 reject common mode noise 9 compact layout size
and interferer 9 less power for same NF
8 double area and current and linearity

9 shield the bond wire 8 susceptive to bond wire


and PCB trace
8 need balun at input
‡ drive single-balance
8 common-mode stability mixer
8 linearity limited by bias ‡ output balun drive
current double-balance mixer

Analog and Mixed-Signal Center, TAMU 28


Differential LNA Common-mode Stability
Issue
VBB VBB

Lg Lg Lg
M1 M1 M1
C1 C1 C1

Ls Ls Ls
Zin,com
C2

2C2

Typical differential LNA Common-mode half circuit


C1 + C2 g m
Z in ,com = jω (Lg + Ls ) +
g
+ Ls − 2 m
jωC1C2 C1 ω C1C2

Analog and Mixed-Signal Center, TAMU 29


Differential LNA Common-mode Stability
Issue (cont’d)
C1 + C2 g m
Z in ,com = jω (Lg + Ls ) +
g
+ Ls − 2 m
jωC1C2 C1 ω C1C2
Real part:
gm ⎛ 1 ⎞
Rin ,com = ⎜⎜ Ls − 2 ⎟⎟
C1 ⎝ ω C2 ⎠

‡ For passive termination, the real part of the source impedance will
always be positive. IF Rin,com happens to be negative and cancel the real
part of source impedance, oscillation MAY occur.
‡ When design differential LNA, not only pay attention to differential
operation, but also check common-mode stability!

Analog and Mixed-Signal Center, TAMU 30


Variant of Inductive Degenerated LNA

LSP LD
Vo
‡ nMOS-pMOS shunt input
VBB ‡ Current reuse to save power
VIN
‡ Larger area due to two degeneration
inductor if implemented on chip
‡ NF: 2dB, Power gain: 17.5dB, IIP3: -
LSN
6dBm, Id: 8mA from 2.7V power supply

Single-ended version of current-


reuse LNA (bias not shown)
F. Gatta, E. Sacchi, et al, “A 2-dB Noise Figure 900MHz Differential CMOS LNA,” IEEE JSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452

Analog and Mixed-Signal Center, TAMU 31


Variant of Inductive Degenerated LNA
(cont’d)
LD
Vo

‡ Inter-stage inductor with


VBB parasitic capacitance form
impedance match network between
Interstage
Inductor
input stage and cascoded stage
boost gain lower noise figure.
VIN

‡ Input match condition will be


affected
LSN

Inter-stage Inductor gain boost

Analog and Mixed-Signal Center, TAMU 32


Design Procedure for Inductive
Source Degenerated LNA

Analog and Mixed-Signal Center, TAMU 33


Targeting Structure
VDD Noise factor equations:
RL ⎛ ω0 ⎞
F = 1 + κ nf ⎜⎜ ⎟⎟
Vo ⎝ ωT ⎠
γ 1
[
1 − 2 c χ d + 4(Q 2 + 1)χ d2 ]
VB
M2
κ nf =
α 2Q
δ
Lg
1
M1 Q=
2 Rsω0C gs
χd = α
Rs Cgs

VIN Ls
Linearity: Voltage Gain:
⎛ ωT ⎞ RL
Inductive degenerated IIP3 ∝ Vgs − Vth AV = j ⎜⎜ ⎟⎟
CMOS LNA ⎝ ω0 ⎠ Rs

Analog and Mixed-Signal Center, TAMU 34


Targeted Specifications

Frequency 2.4 GHz ISM Band


Noise Figure 1.6 dB
IIP3 -8 dBm
Voltage gain 20 dB
Power < 10mA from 1.8V

Analog and Mixed-Signal Center, TAMU 35


Step 1: Know your process
‰ A 0.18um CMOS Process:
‰ tox = 4.1e-9 µm
‰ ε = 3.9*(8.85e-12)F/m
Process related ‰ µ = 3.274e-2 m^2/V.s
‰ Vth = 0.52 V
‰ α = gm/gdo
‰ δ/γ ~ 2
Noise related ‰ γ~3
‰ c = -j0.55
Important design guide plots obtained from simulation or
measurements
Analog and Mixed-Signal Center, TAMU 36
Step 2: Obtain design guide plots
gm, gdo, α, Vgs-Vth vs. current density plot
1.4 2.0
g do
W 1.8
1.2
Gate overdrive voltage (V) and α

1.6

gm/W and gdo/W (mS/µm)


1.0 1.4

gm 1.2
0.8
g do 1.0
0.6
gm 0.8
Vgs − Vth
0.4 W 0.6
0.4
0.2
0.2
0.0 0.0
0 60 120 180 240 300 360 420 480 540 600
Current density (µA/µm)

Analog and Mixed-Signal Center, TAMU 37


Step 2: Obtain design guide plots (cont’d)

Insights:

„ gdo increases all the way with current density Iden


„ gm saturates when Iden larger than 120µA/µm
‰ Velocity saturation, mobility degradation ---- short channel effects
‰ Low gm/current efficiency
‰ High linearity
„ α deviates from long channel value (1) with large Iden

Analog and Mixed-Signal Center, TAMU 38


Step 2: Obtain design guide plots (cont’d)

fT and Cgs vs. gate overdrive voltage

50 1.5
fT

Capacitance density (fF/µm)


45 1.4
Cut-off frequency (GHz)

40 1.3
C gs W 1.2
35
1.1
30
1.0
25
0.9
20 0.8
15 0.7
10 0.6
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Gate overdrive voltage (V)

Analog and Mixed-Signal Center, TAMU 39


Step 2: Obtain design guide plots (cont’d)

Insights:

‰ fT increases with Vod when Vod is small and saturates


after Vod > 0.3V --- short channel effects
‰ Cgs/W increases slowly after Vod > 0.2V
‰ fT begins to degrade when Vod > 0.8V
„ gm saturates
„ Cgs increases

Analog and Mixed-Signal Center, TAMU 40


Step 2: Obtain design guide plots (cont’d)
κnf vs input Q and current density
3-D plot for visual
15 inspection
Current density
14

13 47µA/µm
⎛ ω0 ⎞
Noise factor scaling coefficient

12
F = 1 + κ nf ⎜⎜ ⎟⎟
⎝ ωT
11

10
88µA/µm ⎠
9 135µA/µm
1
8 Q=
7
184µA/µm 2 Rsω0C gs
6 300µA/µm

4
3
2-D plots for
1 2 3 4 5 6 7 8 design reference
Quality factor

Analog and Mixed-Signal Center, TAMU 41


Step 2: Obtain design guide plots (cont’d)

Insights:
Design trade-offs
‰ Iden↑- F↓
‰ Q↑- F↑
‰ For large Iden ( 300 µA/µm) there is an optimal value
of Q --- maybe too large for a practical design

‰ For fixed Iden, increasing Q will reduce the size


of transistor thus reduce total power ---- noise
figure will become larger

Analog and Mixed-Signal Center, TAMU 42


Step 2: Obtain design guide plots (cont’d)
Linearity plots :IIP3 vs. gate overdrive and transistor size

20x2.5µm 30x2.5µm 40x2.5µm


18
16
14
12
IIP3 (dBm)

10
8
6
4
2
0
-2
0 0.1 0.2 0.3 0.4 0.5
Gate overdrive voltage (V)

Analog and Mixed-Signal Center, TAMU 43


Step 2: Obtain design guide plots (cont’d)

Insights:
„ MOS transistor IIP3 only, when embedded into actual circuit:
‰ Input Q will degrade IIP3
‰ Non-linear memory effect will degrade IIP3
‰ Output non-linearity will degrade IIP3
„ IIP3 is a very weak function of device size
„ Generally, large overdrive means large IIP3
‰ But the relationship between IIP3 and gate overdrive is not monotonic
‰ There is a local maxima around 0.1V overdrive

Analog and Mixed-Signal Center, TAMU 44


Step 3: Estimate fT and calculate κnf
50 1.5
fT

Capacitance density (fF/µm)


45 1.4
Cut-off frequency (GHz)

40 1.3

fo = 2.4 GHz F = 1.45


C gs W 1.2
35
1.1
30
1.0
25
0.9
20 0.8
15 0.7
10 0.6

= (F − 1) = 7.5
fo
κ nf
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Gate overdrive voltage (V)

fT
‰ Small current budget ( < 10mA )
does not allow large gate over drive :
‰ 0.2 V ~ 0.4 V C gs W = 1.3 fF / µm
‰ fT ~ 40 GHz

Analog and Mixed-Signal Center, TAMU 45


Step 4: Determine Iden, Q and Calculate
Device Size
20x2.5µm 30x2.5µm 40x2.5µm
1.4 2.0 18
g do
W 1.8 16
1.2
Gate overdrive voltage (V) and α

1.6 14

gm/W and gdo/W (mS/µm)


1.0 1.4 12
1.2

IIP3 (dBm)
0.8 gm 10
g do 1.0 8
0.6
gm 0.8 6
Vgs − Vth
W 0.6
0.4 4
0.4 2
0.2
0.2 0
0.0 0.0 -2
0 60 120 180 240 300 360 420 480 540 600
Current density (µA/µm)
0 0.1 0.2 0.3 0.4 0.5
Gate overdrive voltage (V)

Select Iden = 70 µA/µm If Q = 4, IIP3 will have enough margin:


Estimated IIP3:
IIP3( read from curve ) – 20log(Q)~ -4dBm
Specs require: -8 dBm

Analog and Mixed-Signal Center, TAMU 46


Step 4: Determine Iden, Q and Calculate
Device Size (cont’d)
15
Current density
14

13 47µA /µm
Now we can do calculations:
Noise factor scaling coefficient

12
11
88µA/µm
10
1
135µA/µm
C gs =
9
~ 166 fF
2QRsωo
8
184µA /µm
7

6 300µA /µm

4
3
166 fF
1 2 3 4 5 6 7 8
W= = 128µm
1.3 fF / µm
Quality factor

Q=4 and Iden = 70µA/µm meet the


noise factor requirement
I DS = 128µm × 70( µA / µm) = 8.9mA

Analog and Mixed-Signal Center, TAMU 47


Step 5: Calculate Lg, LS and Required Load
‰ Verify cut-off frequency
‰ gm is about 50mA/V for the determined
current density and device size

‰ fT = gm/(Cgs*2pi) = 48 GHz --- Verified !

⎛ ωT ⎞ RL
Rs AV = j ⎜⎜ ⎟⎟
Ls = ≈ 0.2nH ⎝ ωo ⎠ Rs
ωT
1
Lg = 2 − Ls ≈ 26nH ωo
ωo C gs RL = AV Rs ≈ 30Ω
ωT

Analog and Mixed-Signal Center, TAMU 48


Step 6: Simulation Verification
Usually simulation-hand calculation iterations are
necessary to obtain satisfactory design
Parameters Calculation Simulation
W 128um 127.5um
Ids 8.9mA 8mA
gm 50mA/V 50.7mA/V Deviate from
hand-calculation
Cgs 166fF 151fF
most
Ls 0.2nH 0.2nH
Possible reason:
Lg 26nH 16nH Cgd is not
RL 30 Ohm 40 Ohm considered for
hand calculation

Analog and Mixed-Signal Center, TAMU 49


Step 6: Simulation Verification (cont’d)

Simulation plots for IIP3, Av, NF and S11


20 25.0 0.88

P1dB=-20 dBm 20.0 AV


0
Output Voltage (dBV)

15.0 0.86

Noise Figure (dB)


S11 and AV (dB)
-20 10.0
0.84
IIP3=-6.4 dBm 5.0
-40
0.0
0.82
-60 -5.0
NF
-10.0
-80 S11 0.80
-15.0

-100 -20.0 0.78


-40 -35 -30 -25 -20 -15 -10 -5 0 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60

Input Power (dBm) Input Frequency (GHz)

Analog and Mixed-Signal Center, TAMU 50


Step 6: Simulation Verification (cont’d)

Comparison between targeted specs and simulation results

Parameter Target Simulated


Noise Figure 1.6 dB 0.8 dB
Current drain < 10mA 8 mA
Voltage gain 20 dB 21 dB
IIP3 -8 dBm -6.4 dBm
P1dB --- -20dbm
S11 --- -17 dB
Power Supply 1.8V 1.8V

Analog and Mixed-Signal Center, TAMU 51


Summary for LNA Design Procedure
‰ Design mixed with simplified equations and
simulation plots normalized to unity device size help to
gain insights and consider all the important design
specification at the same time.
‰ Several iterations is generally required from hand
calculation to simulation to arrive at satisfactory or
optimal design.
‰ Secondary effects such as gate poly resistance can be
considered during simulation and can also be considered
by add more margin in the design specifications.

Analog and Mixed-Signal Center, TAMU 52


LNA in BiCMOS Technology

Analog and Mixed-Signal Center, TAMU 53


Advantages of BiCMOS Process
„ Higher gm/DC current (Low Power)
„ Translinear property
„ Outstanding Vbe matching between adjacent devices
„ Highly accurate low- and high-frequency equivalent circuit models based
on physical device behavior
„ Design flexibility due to availability of multiple device types
„ Availability of higher quality passive devices (thick metal inductors, high-
value MIM capacitors, etc.) is more common in BiCMOS processes.
„ First-pass design success thanks to high-quality equivalent circuit models.
„ Wider dynamic range operation for a given lithographic generation.
„ Higher speed devices available in BiCMOS for a given lithographic
generation.

While pure CMOS process has higher level system integration and lower cost which in some
cost-sensitive designs will out run BiCMOS process.

Analog and Mixed-Signal Center, TAMU 54


Variations of Bipolar LNAs

Cascode LNA Matched LNA Transformer Feedback


‰ Increased Gain ‰ Increased Gain ‰ Lower Gain
‰ Potentially Unstable ‰ Potentially Very Unstable ‰ Improved Linearity
‰ Lowered Headroom ‰ Lowered Headroom ‰ Excellent Headroom
‰ Complexity

Analog and Mixed-Signal Center, TAMU 55


Principle of Out-of-band Termination
In-band property, determined
Volterra Analysis gives: by LNA specs

1
IIP3 =
6 Re[Z1 (ω )]⋅ H (ω ) ⋅ A1 (ω ) ⋅ ε (∆ω ,2ω )
3

Out-of-band parameters, can


2 g 22 be modified w/o affecting in-
ε (∆ω ,2ω ) = g 3 − [2k (∆ω ) + k (2ω )] band property
3

For BJT g3 is positive, by tuning out-of-band termination impedance


at 2ω and ∆ω, ε (∆ω ,2ω ) can be made small thus increase IIP3.

Analog and Mixed-Signal Center, TAMU 56


Input Termination Techniques

‰ IIP3 improves for a ‰ Stability issues ‰ Extra external


narrow range of ∆ω ‰ High NF component
‰ Slow gain switching ‰ Lower gain ‰ Extra pin
‰Extra external
components

Analog and Mixed-Signal Center, TAMU 57


Example: Cellular-Band LNA Design

‰ Two gain modes


‰Out-of-band termination improve
linearity: IIP3=+11.7dBm/+23.0dBm
‰ Power gain: 15.7dB/-3.1dB
‰ Noise figure: 1.4dB/3.2dB
‰ Current: 5.4mA/0

V. Aparin, P. Gazzerro, Z. Jianjun, S. Bo, S. Szabo, E. Zeisel, T. Segoria, S. Ciccarelli, C. Persico, C. Narathong, R. Sridhara, “A
highly-integrated tri-band/quadmode SiGe BiCMOS RF-to-baseband receiver for wireless CDMA/WCDMA/AMPS applications
with GPS capability,” 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pp.234-5

Analog and Mixed-Signal Center, TAMU 58


Wide Band LNA

Analog and Mixed-Signal Center, TAMU 59


Design considerations
Resistive Termination Common Gate Shunt-series Feedback
VDD
VDD

ZL
OUTPUT
RL
VBB VDD
M2 Rf OUTPUT

VBB
INPUT RL
M1 M1
INPUT

Rs
INPUT M1 OUTPUT R1

„ Broadband impedance match: resistive termination,


common gate, feedback
„ Noise figure is usually high
„ Broad gain flatness requires resistive load

Analog and Mixed-Signal Center, TAMU 60


Broad Band LNA: Noise Cancellation

‡ 0.25um CMOS
‡ NF: 2.4dB
‡ -3dB BW: 2M-1.6GHz
‡ IIP3: 0dBm
‡ Voltage Gain: 13.7dB

F. Bruccoleri, E.A.M. Klumperink, B. Nauta, “Noise Cancelling in Widband CMOS LNAs,” ISSCC 2002 Session 24.6

Analog and Mixed-Signal Center, TAMU 61


Distributed Amplifier as LNA
Why distributed?

‡ GBW Limits for traditional amplifier: gm/C


‡ In distributed circuits the parasitic cap C is absorbed
into the distributed structure, So breaking the gain-
bandwidth relationship.
‡ Ideally bandwidth should be infinity
‡ In practice bandwidth will be limited by the loading
character of the transmission line.

Analog and Mixed-Signal Center, TAMU 62


Distributed Amplifier as LNA (cont’d)
Transmission line modeling on Silicon
Coplanar Strip line

Micro strip line

‡ Shrinking of feather size make dielectric


material thicker.
‡Top metal far away from lossy silicon
substrate.
‡ Tline loss is reduced

Analog and Mixed-Signal Center, TAMU 63


Distributed Amplifier as LNA (cont’d)
Transmission line modeling on Silicon

Characteristic Impedance of Coplanar Stripline

130 Characteristic Impedance of Micro Stripline



120
8µ 70
110
11µ 60
Zo (Ohms)

Z o (O h m s)
100
50
14µ
90
40
80 30
70 20
60
4 9 14 19 24 29
4 8 12 16 20 24 28 Width of signal line (M1)
Line spacing (µ m)

Loss: 0.8dB/mm at 30GHz

Analog and Mixed-Signal Center, TAMU 64


Distributed Amplifier as LNA (cont’d)
Artificial or real T-line?
‡ Artificial line uses lumped inductors and capacitors: have
good model from foundry.
‡ Real T-line uses metal lines to form energy transmission
path: currently no models from foundry, has to be modeled by
designers.
‡ The quality of lumped on-chip inductors limits the
frequency operation: low Q and low self-resonate frequency.
‡ For higher and higher frequency, spiral inductor structure
can not be modeled use lumped inductance any more.
‡ Artificial line: low frequency operation ( <10GHz)
‡ Real transmission line: high frequency (>10GHz)

Analog and Mixed-Signal Center, TAMU 65


Distributed Amplifier as LNA (cont’d)
Distributed LNA
0 xd ld
Output

ld 2 ld 2
T
Z d Z dL

lg 2
Input

xg lg lg 2
Zs 0
Z gT

‰ Cgs and Cds absorbed into the T-line


N 2 g m2 Z cd Z cg
‰ Under phase sync condition, maximum gain obtained : G=
4
ln (α d ld ) − ln (α g l g )
‰ Optimal number of sections (loss line) :
N=
α d ld − α g l g

Analog and Mixed-Signal Center, TAMU 66


Distributed Amplifier as LNA (cont’d)
Distributed LNA
15 17
10
15
5 S21
S21, S11, and S22 (dB)

Noise Figure (dB)


13
0
S11
-5 11
-10
9
-15

-20
7
S22
-25 5
-30
1 3 5 7 9 11 13 15 17 19 21 23 25 27 3
Frequency (GHz) 2 4 6 8 10 12 14 16 18 20 22 24 26
Frequency (GHz)

‰ Extremely wide band and gain flatness (1 – 20 GHz)


‰ Good matching over wide band (1 – 15 GHz)
‰ High noise figure at lower portion of frequency

Analog and Mixed-Signal Center, TAMU 67


Wide-band LNA Using LC Lumped
Matching Network
In the literatures
‰ MOS Implementation [1] ‰ Bipolar Implementation [2]

[1] A. Bevilacqua and A. M. Niknejad, “An Ultra-Wideband CMOS LNA for 3.1 to 10.6GHz Wireless Receivers”, ISSCC 2004.
[2] A. Ismail and A. Abidi, “A 3 to 10GHz LNA using a Wideband LC-ladder Matching Network”, ISSCC 2004

Analog and Mixed-Signal Center, TAMU 68


Insight of LC Lumped Matching Network
--An Alternative Implementation Method

„ Impedance match based on LC ladder network


„ An alternative method: using the well-known Smith Chart
„ More straight forward and have well defined performance
„ Required VSWR can be drawn on Smith Chart
„ Visualize the matching goal

Analog and Mixed-Signal Center, TAMU 69


Wide-band Match Procedure Using
Smith Chart TLine
L2
Cc
M1
L2
Step1
Cc
M1

L1
Step 1: Series inductance makes the S11
C1 RB RB

conductance at the frequency edge Finish VB


S11
VB

has the same real part


Step 2: Parallel inductor and
capacitor brings the frequency edge
S11 close together (forms a circle) L2
Cc
M1
Step 3: Series inductance again
L1
brings the circle center to pure C1 RB
S11
resistance point Step3
VB Cc
M1

Step4: A quarter-wave transmission L2 RB


line is used to rotate the circle to Cc
M1
S11
VB
the center of the smith chart. L1
RB
Start
S11 C1

Step2 VB

Analog and Mixed-Signal Center, TAMU 70


Implementation of Lumped Matched
LNA
VDD

Rd C2
Ld

Cc RFOUT
Quarter wave
M2
L3
transmission line
L2
Cc
M1
RFIN
L1
C1 RB
Bondwire
VB

Current drain: 5mA from 1.8V power supply

Analog and Mixed-Signal Center, TAMU 71


Simulation Results of the Lumped
Matched LNA

Analog and Mixed-Signal Center, TAMU 72


Design Examples

Analog and Mixed-Signal Center, TAMU 73


BT/WiFi Receiver Block Diagram
15dB 18dB
I Mixer LPF
φ ADC
RF
Filter
0
φ Gain Signal Level
LNA 90
Control Measurement
φ
φ
ADC
Q Mixer LPF
Synthesizer
Attenuator(-15dB) & VCO

‡ Bandwidth compatible (2.4GHz) ‡ Pmin <-80dBm


‡ Sharing Front-end is possible (save power) ‡ Pmax >-20dBm
‡ Multi-standard system delivers flexibility ‡ LNA switch gain at -40dBm

Analog and Mixed-Signal Center, TAMU 74


Differential LNA using BJT cascode
Proposed LNA
VDD
‡ Differential structure Ld Ld
Cd Cd
‡ MOS transistor is more linear Vo+

‡ Inductor degeneration LNA_cas_bias Q1 Q2


Vo-

M5 M7
„ Cascoded BJT: better matching Bond wire
Cm M9

‡ On-chip input matching Vin+


M6 M8

M1 M2
„ Noise figure: 1.6dB Vin- LNA_bypass
Rb Rb
LNA bypass switches and attenuator
Rb Ls Ls
‡ Power/Voltage gain: 15dB Rb
Vbb

‡ Power consumption: 16mW


i_tail
LNA_rf_bias

M3 M4
„ NMOS attenuator for low gain(-15dB)

Analog and Mixed-Signal Center, TAMU 75


Differential LNA using BJT cascode (cont’d)
LNA Layout

‡ Symmetrical layout
3nH
‡ Deep trench lattice under spiral Gain S.W.
inductor
‡ Inductors are placed far apart

580um
to avoid coupling (~200um) Q1, Q2

‡ Differential inputs are M1, M2


decoupled by GSGSG pattern
1nH

G S G S G
570um

Analog and Mixed-Signal Center, TAMU 76


Testing Setup
Input matching (S11)

S-parameter network
analyzer (HP 8719ES)
S11 better than -11dB

High gain mode Low gain mode


Testing board * LNA is tested together with mixer

Analog and Mixed-Signal Center, TAMU 77


Testing Setup (cont’d)
Gain of the front-end

Signal generator Testing board Oscilloscope

RF IN

IF OUT I&Q

Conversion gain: 33dB

* LNA is tested together with mixer

Analog and Mixed-Signal Center, TAMU 78


Testing Setup (cont’d)
IIP3/IIP2 60

IIP3=-13dBm
40

20

Output (dBm)
Testing board Spectrum 0

Analyzer -20

-40

-60

RF IN
-80
-50 -45 -40 -35 -30 -25 -20 -15 -10

2-Tone Input Power (dBm)

Signal generator Power


combiner
80

60

IIP2=10dBm
40

Output (dBm)
20

IF OUT I&Q
-20

-40

-60

-60 -50 -40 -30 -20 -10 0 10 20


2-Tone Input Power [dBm]

* LNA is tested together with mixer

Analog and Mixed-Signal Center, TAMU 79

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