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Analog-to-Digital Conversion
R. Jacob Baker and Vishal Saxena
R
Department of Electrical and Computer Engineering
Boise State University
jbaker@boisestate.edu
Abstract :
As CMOS technology shrinks, the transistor speed increases enabling higher speed
communications and more complex systems. These benefits come at the cost of decreasing
inherent device gain, increased transistor leakage currents, and additional mismatches due to
process variations. All of these drawbacks affect the design of high-resolution analog-to-
digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology
useful in these small processes the K-Delta-1-Sigma (KD1S) modulator-based ADC was
proposed. The KD1S topology employs inherent time-interleaving with a shared op-amp and
K-quantizing paths and can achieve significantly higher conversion bandwidths when
compared to the traditional delta-sigma ADCs. The 8-path KD1S modulator achieves an SNR
of 58 dB (or 9.4-bits resolution) when clocked at 100 MHz for a conversion bandwidth of 6.25
MHz and an effective sampling rate equal to 800 MHz. The KD1S modulator has been
fabricated in a 500 nm CMOS process and the experimental results are reported. Deficiencies
in the first test chip performance are discussed along with their alleviation to achieve
theoretical performance.
Outline
Introduction
Delta-Sigma
D l Si M d l i
Modulation
Interleaved Delta-Sigma Modulators
KD1S Modulator Topology
Test Chip and Results
Conclusion
CMOS Scaling Trends
modeling!
9 Promising but cumbersome.
Not robust with further CMOS scaling and
high speed operation.
9 Need topologies which are inherently robust
to mismatches.
Delta-Sigma (ΔΣ or DS) Modulation
ΔΣ Modulator
Qe
vin + vDSM vout
H(z) ADC Digital Filter
–
DAC
STF
NTF•Qe
|VDSM(f)| |Vout(f)|
vin vin
Qe
f f
fs/2•OSR fs/2 fs/2•OSR fs/2
y2 φ1-3 9 Integrator
I
φ1-4 φ2-4 φ2-4
φ2-3
Thus the error signal
y3 φ1-4
vin φ2-4
is cycled through the integrator
φ2-1 φ1-1 φ1-1
y4
Non-overlapping Clocks within Ts/K duration.
9 True first order noise shaping.
φ2-2 φ1-2 φ1-2 y7
y6
y5
y5 b3
y4 K-Input
p
b2
y3 Wallace
b1
φ2-3 φ1-3 φ1-3 Tree Adder
y2 b0
y6 y1
y0
-K
φ2-4 φ1-4 φ1-4 Path Filter, 1-z-1
1-z
y7
φ1_2
φ1_2
φ2_2
φ2_2
φ1_3
φ1_1
φ2_3
φ2_3
φ1_4
φ1_4
φ2_4
φ2_4
φ1_1
φ1_1
φ2_1
φ2_1
Ring oscillator is used to
generator the K clock phases and Delay Delay Delay Delay
their complements.
9 GHz sampling rates as the rate is
set by the clock edge spacing. φ1
in+
A DLL can also be used for low 5x 5x
φ1
K- Clock phases
KD1S Simulation
KD1S Output Spectrum KD1S Output Spectrum
0 0
-30 -30
-40 -40
-50 -50
+20dB/dec
dB
dB
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
0 1 2 3 4 5 6 7 8 5 6 7 8 9
10 10 10 10 10
F
Frequency 8
Frequency
x 10
Initial push
~α0•vin[n] ΔQ1
φ2-2
ΔQ where
ΔQ2
φ2-3
vint
i the
is th partial
ti l settling
ttli factor
f t (initial
(i iti l push)
h)
VCM of the integrator.
ΔQ3
Integrator
φ2-4
ΔQ4
KD1S with Non-Ideal Op-amp
4CI
1-Sigma
vint The theoretical result for the K-path
VCM
φ1-1
CI
φ2-1
VCM
φ2-1
y0
Integrator are plugged into the KD1S
Integrator Modulator:
φ1-2 φ2-2 φ2-2
y1
y6
K-Deltas
KD1S: Effect of Comparator Delay (Tcomp) KD1S Output Spectrum KD1S Output Spectrum
0 0
-10
-20
-20
-30
-40
-40
-60 -50
dB
dB
-60
-80
-70
-80
-100
-90
-120 -100
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
Frequency 8 Frequency 8
x 10 x 10
-10 -10
-20 -20
-30 -30
-40 -40
dB
dB
-50 -50
-60 -60
-70 -70
-80 -80
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
Frequency 8 Frequency 8
x 10 x 10
For true noise-shaping in a process the KD1S should be clocked such that
The resultingg bit resolution decreases with an increase in comparator
p delay.
y
9 Resolution drops from 9-bits to 6-bits as we increase Tcomp from Ts/2K to Ts/2.
KD1S Test Chip
SNR (dB)
Measured SNR for a 2 MHz, 4 Vp-p input tone, and BW = 6.25 MHz
9 SNR = 30 dB, Neff = 5 bits
9 Proof of Concept: First order wideband noise-shaping achieved.
Performance lower than expected:
9 Design mistake in connection of clock phases. Lower op-amp gain.
9 Rectified in subsequent designs.
KD1S vs. Single-path DSMs
Process variation Ratio of C’s: <0.1% RC time constant: 30% Ratio of C’s: <0.1%
Cf
In order to achieve true first order noise
shaping (K
(K-times),
times), the chain of noise
vint differentiation should not be broken:
VCM
φ1-1 φ2-1 φ2-1 9 Pick current integrator output (vint),
Ci VCM y1 quantize it with comp-1 to get y1.
9 This y1 must be used by path-1 and
φ1-2 φ2-2 φ2-2 subtracted from vin.
y2 9 The result (vin-y1) is integrated and its
vin result updates vint.
9 Now path-2 must pick this vint and
quantize with comp-2, and so on….
φ2-4 φ1-4 φ1-4
Al
Always fresh
f h Q(v
Q( int) information
i f i
yK
should fed back through the DAC
(important!)
Ideal KD1S- Circular Clock Phase Diagram (CCPD)