A FTILL FUNCTION VERILOG@PLL LOGIC MODEL

MohammadAshraf, Tore Kellgren and Michael Frarz

Toshiba America Electronic Components

San Jose,California, USA

Abstract
This paper describes the full function model of a phase-
locked loop (PLL) in a logic simulator. In contrast to
conventional models that bypass the PLL function, this
Verilog model accuratelyrepresentsall major characteristics
of a PLL. It allows the simulation of the effect of the actual
filter elements. It can accurately model clock deskew of a
clock tree as well as synthesizeother frequenciesfrom the
input clock. It producesa lock detect signal after a realistic
lock sequence. The user has the option to add jitter to the
PLL output. The model performs three orders of magnitude
fasterthan an equivalent circuit model.
Introduction
On-chip phase-locked loops (PLLt) have become common
place in Application Specific Integrated Circuits (ASICs).
Initially esoteric circuitry tU requiring custom design
techniques,they are today standard offerings in gate aray
and standard cell libraries of most ASIC vendors. Their
main functions in digital circuitry uue clock deskew,
frequencysynthesisand clock recoveryfrom data signals.
Even though PLI^s are well established they are still
- advancing rapidly in various performance parameterssuch
as frequency range,jitter and lock time. Other advahcesare
on-chip filters or reduction of power supply noise
sensitivity.
However,there is one lingering shortcomingof PLI-s that is
associatedwith their logic model. Becauseof the intricate
inner workings of a PLL, an a@urate representationof its
function has commonly only been achievedwith circuit type
simulatorssuch as SPICE. Circuit models are necessary for
the design of the PLL itself but unfortunately,for chip-level
simulationsa circuit type model is not useful becausea) the
model typically is not compatiblewith a logic simulator, and
b) even if a mixed mode (analog/digital) simulator is used,
the simulation times for the PLL are exorbitant amounting
sometimesto days to only achievelock.
Most digital designers "bypass" the problem in the true
sense of word. Rather than attempting to simulate PLL
behavior in the context of a digital chip or system, they
bypass the PLL by means of a multiplexer. In fact most
logic models of PLI-s are nothing more than a bypass mux.
This method is useful to the extend that the designer can
implement his/her logic without having to worry about the
specialissuessurrounding a PLL, such as lock-up, jitter and
otherphenomena.
However, such work-arounds do not adequately represent
the real time behavior of the actual PLL and in some caaes
do not allow the simulation of a larger system at all. The
latter is particularly true where the PLL is used for
frequency synthesis with dynamic frequency switching as
for examplein the caseof a hard disk drive.
The following paper describesa Verilog logic model of the
PLL that allows the Verilog simulation of all relevant PLL
phenomenasuch as real clock deskew,frequency synthesis,
lock-up behavior including lock-detection, effects of the
filter parameterson the PLL behaviorand evenjitter.
PLL Transfer Function
Toshiba offers several PLI^s with its family of gate anay
products. These PLI-s are "metallized", i.e. they are
instantiatedon the gate array like any other macro function.
Thus they have the advantageof the faster turn-around time
of a gate array. In addition they can be instantiatedseveral
times on one array.
These PLLs are considered"analog" in that they employ an
(external) loop filter and an analog voltage-controlled
oscillator (VCO). Their phase detector is the industry
standard phase frequency detector which is a digital
function.
In order to establishthe equivalentlogic model of a PLL let
us first consider the transfer function of a linear phase-
locked loop. Figure 1 shows the familiar building blocks of
an analog PLL.
Fig. 1. Building blocks of analog PLL
A phasedetector comparesthe phaseof the reference(input)
clock, 0,, with the phaseof the feedbackclock, 0r, from the
VCO. The charge pump converts upidown phasedifference
pulsesinto constantcurrent pulsesthat charge or discharge
the capacitorof the loop filter. The resulting voltage across
the resistorand capacitor (ag filter) drives the input of the
VCO. For simplicity of argument we are only considering

15.6.1
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$5.00@ l997IEEE CIRCUITSCONFERENCE
IEEE I997 CUSTOMINTEGRATED
here the linearized model of the PLL even though the
Verilog model dealswith non-linearand startup effects.
The transfer functions in l.aplace domain (transformed Finally
variablesare in uppercase)for the building blocks can be equatio
written [2] as follows: VCO ir
Phasedetector/chargepump:

/r(r) : Ka(o,(r) - @2(r)), (1) The ec

analog
Lnop Filter: the dig
Fig,2. PLL building blocks in Verilog Verilotr
/ 1\
u/ (s): I r ( s ) [ R + ^ 1 , \L) In the Verilog model of our PLL the input signal with the inp
\ sL/ frequency, f,"u enters the industry standard phase/frequency
detector,which is made up of logic gatesjust like the actual
VCO:
circuit. The output signals,up and dn, have a duration equal
Ko to the phasedifference betweenthe input signal, f,"r, and the
@, (r) - x U, (s) . (3) output signal, f*,. For simplicity we combine these two or agai
s signals into one three-valuedsignal [-1,0,1], updn(t). Its
In (1). Iu(s)is the averagecurrentfrom the chargepump into I-aplacetransform can be written as,
the loop filter, @,(s) and @r(s) are the respectivephase UPDN (s) : @,(r) - @r(r) (7)
anglesof the referenceand the feedbackclock and Ko stands
It shor
for the combined phasedetector/charge pump gain. In (2), The chargepump is omitted, becausemathematicallyit only
Verilo
U(s) standsfor the input voltage of the VCO; R and C are represents a proportionality constant. The loop filter is
quasi-
the loop filter resistorand capacitor,respectively.s is the represented by a counter, CTR, and three identical
time 0.
l.aplacevariable.Finally,K in (3) is the gain of the VCO. multipliers, MULT. The counter produces a count
proportionalto the voltage acrossthe filter capacitor.It is a Now
By,defining the PLL loop transferfunction as
cumulative counter and does not reset. Then, for every mathe
@t(t) enablingup or down signalit will count cumulativelyup or analog
H(') : ' (4) down. The counting period was chosento be T" = lps which establ
@ , (t) is small with respectto the clock period of the PLL. Counter IQ anr
CTR can be preset at start-up and is 32 bits wide, giving
we obtainthe simpleresultfor H(s),
enough resolution and count spaceso as to avoid significant
quantization errors or overflow/underflow problems.
K'KoF(s)
H(s) - ' (s) Mathematically, the counter approximatesthe time integral
s + KoKdF(r) of the three-valued updn(t) signal coming from the phase Comb
detector.
whereF(s) is the loop filter transferfunction,

u/ (s) 1
c,o]g): (8)
F(') : :,R* (6)
il"odn(t)dt
/, (") SC For later adjustment,ccrn is multiplied by a proportionalitY
wherr
constant,I(..
PLL Transfer Function of Verilog Mo{el
cr(t):KcxcroQ). (9)
In our attempt to model this analog transfer function as
closely as possible into building blocks that can be The equivalent Laplace transform of (8) and (9) combined
expressedin Verilog modeling language,we employedthe becomes.
following analogy: The pr
physic
c-(s) -K, (10)
L\ /
T, "uPDff(s)
S

The filter resistor is representedby the two multipliers' and

MULT. Their function is to multiply the up and down
signals with the proportionality constant, K*, that later on
can be tuned for actual resistor values. The resistor
correctionis,

15.6.2
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 C^(") -- KR x UPDN(s). (11) Verilog Simulation Results
kt us now look at the actual behavior of the Verilog model
Finally, we add C*(s) and Cds) in analogy with loop filter of the PLL. Fig. 3 shows the typical signal waveforms for a
ft
equation (2). The resulting count, C(t), is analogousto the clock deskew circuit. The first signal is the input reference
VCO input voltage, Ur. clock running at L00 MHz. The second waveform depicts
Cr (r) : Cn(r) + C. (t) . (12) the feedbackclock that attemptsto lock onto the reference
clock. It is apparentthat in Fig. 3a both clocks are far apart
The equivalence of a voltage controlled oscillator in the in their respectivefrequencies.Signals three and four show
analogwoild is a numerically controlled oscillator (NCO) in the down and up output of the phasedetector, respectively
the digital domain. The NCO is modeled behaviorally in and signal 5 shows the composite count of the 32-bit
Verilog. Its output signal has a phase,0r(t), that is relatedto counter. The up signal of the phase detector is very busy
the input count, c(t), as follows: trying to pump up the counter and by that the frequency of
with the NCO. Fig. 3b shows the samesignalsbut approximately
rency 15 us later. By now both, the reference clock and the
rctuiil 0 ,(t) - :- I'c, (t)dt , (13) feedbackclock have achievedperfect lock. The down and
:qual rr"
up signalsof the phasedetectorare inactive and the counter
,l the
or again performing a I-aplace transform, settingis constant.
two
,. Its I aoo | 4so r soons
cr (t) rlrlrlrlrlrlrl,lrlrlrlrl'l'lrlr
: +'
@r(s) . (14)
T,s lret
(7) fout
It should be noted that the integral of c(t) is performed in
rrnly
Verilog by employing multiple timers during periods of up
. c r is quasi-constantc(t). The NCO producesa transition every C'-Ta
ntical
time Or(t)reachesn. (a)
;ount
t isa Now we would like to establish the approximate I 47800 | 47850 | 47900 ns
,jvery mathematical transfer function of this digital model in rlrlrlrlrlrlrlrlrlrlrlrlrlrlrlr
,rp or analogy with (a). By comparing coefficients we can then trel
vhic h establishthe values of the digital proportionality constants, I'oul
unter IQ and K*, in relation to the physicalparametersof the PLL. dn
r v ing
up
icant or(t)
lcms.
Ir'("): (4) ccrn
@'(t) (b)
regral
lhase CombinineQ), (11), (12) and (14) we get, t0 t5000

lrel
lrlrlrlrlrlrlrlr lr t I'ili't,IrIrl','llot
,"
*F'(r)
\ '/: --j-T+-
fort
(8) //(") ' (15)
r * +F',(s) dn
up
II

:rality CcrR
wherethe equivalentfilter transferfunction is definedas
LDffi
KC
(e) cr (") :Kn + T.
(c)
F'(s) : (16) Fig.3. lncking behaviorof PLL Verilogmodel
oined I/PDN(s) .s
Finally, Fig. 3c showsthe entire lock sequenceof the same
The proportionality constants,K* and I(., are related to the signals.Becauseof the time scalethe toggling signalsappear
physical parametersof the PLL as follows, all black. At start-up the up signal is continuously pumping
(10) ,&i up the frequency of the feedback clock. After 10 us the
Kn : T"KoKdR , - (17) feedback clock frequency is caught up with the reference
clock and overshoots slightly. After two more up/down
rliers,
period corrections the PLL has achieved lock. Then only

;""1*;iliffiffi'Hl"'#i;:J",i:X:
Cown
i r on
sistor
K c = \,
K"KO
C
(18);:l".?;;,Hf:?
note the last signal, LD, that indicateslock detect.After one
bounceit indicateslock at about 12 Vs.

15.6.3
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 Another application of the PLL is frequency synthesis.For
this purpose a frequency divider circuit is inserted in the
i' l ' l feedback path between the NCO and the phase detector as
.; shown in Fig. 4. The divider is implemented as a
programmablecounterusing standardflip-flop circuitry.
one other feature is the optional addition of jitter to the pLL
output. By making use of a random function generator in
Verilog, the user can add any desired jitter amplitude to the
NCO period, thus allowing realistic worst case system
simulations. Of @urse the PLL model has a bypass mode,
just as the physical PLL. This mode is selected by external
control signals.

fo*=N*fr"y The phasedetectoris equippedwith a lock detect signal that

Fig. 4. Verilog model for frequencysynthesis
Figure 5 shows the locked state of the PLL for a 4x
frequency multiplication. The first signal is again the
reference clock (25 MHr). The second signal is the
multiplied output clock, f-, (100 MHr). Finally, the last
signal, is the feedbackclock, f*, into the phasedetector.
;15100 r15150 t15200
rlrlrlrlrlrlrlrlrlrlrlrlrlrlrlrlrl
I, r e l
respondswhen the reference clock and feedback clock are in
phase (phase does not differ by more than 700 ps) for g
consecutive periods.
Finally, the model was enhanced,to allow the presettingof
the counter representingthe capacitor, to any user selected
value. This feature allows the user to shortcut the otherwise
long lockup s€quence.
Performance
Comparedto circuit simulators the performance of our pLL
simulation in Verilog was improved by almost 3 ordersof
magnitude.While an HSPICEru simulation would require
approximately 48 hours to achieve lock, the Verilog model
would completethe sametask in 4 minutes.
t15250nS
Conclusion

I
tout
The presentedVerilog model of an analog PLL accurately
fre reflects all relevant physical featuresof a PLL. In particular
it allows realistic simulation of clock deskew and frequency
Fig.5. Waveformof frequencysynthesis synthesis. It also representsaccurately the lock sequence
including the lock detectsignal,basedon the choice of filter
Other Features elements. Finally, at the user's discretion, an arbitrary
We have addedother featuresto our Verilog PLL model.As amount of random jitter can be added to the PLL output
mentioned earlier, the filter components,R and C, can be signal. The model performs almost three orders of
enteredby the user into the model,thus emulatingthe actual magnitudefasterthan an equivalentcircuit model.
lock behavior of the circuit including damping phenomena
due to the particularfilter characteristics.This capability is Reference
demonstrateci l 1 l F. M. Gardner,*Charge-pump phase-lock loops," IEEE Trans.
in Fig. 6 which showsthe lock behaviorof the
Commun.,vol. COM-28, pp. 1849-1858,Nov. 1980.
PLL for several filter characteristics.As is shown the value
of the filter capacitor is varied from L50 to 1000 pF. The I2l R. E. Best, "Phase-l.ocked [.oops: Theory, Design, and
Applications, " McGraw Hill, 1993.
resulting change in lock time and damping behavior is
displayed(in terms of output frequency,f*,) vs. time. Verilog@is a registeredtrademarkof CadenceDesign
Systems,Inc.
110
100 HSPICETMis a trademarkof Meta-Software,Inc.
90
BO
N
r70
aoo
jso
40
30
20
oooooooooo o
Ol(9$lO(ol..-@O) o

t [ps]
*,4
Fig. 6. Effect of filter parameter, C, on lock behavior.

fi:"

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